A clock synchronization method, high-speed industrial bus system, device and storage medium

Abstract

Embodiments of the present invention disclose a clock synchronization method, a high-speed industrial bus system, a device, and a storage medium. The method includes: upon receiving a standard clock moment sent by a timing module, obtaining a currently updated first local clock moment; upon startup, each node in the high-speed industrial bus system dynamically updates the local clock moment; upon detecting that network-wide clock synchronization conditions are met, obtaining a currently updated second local clock moment and the current bus moment of the high-speed industrial bus system; calculating the target bus moment of the high-speed industrial bus system upon receiving the standard clock moment based on the first local clock moment, the second local clock moment, and the current bus moment; performing local clock synchronization based on a time mapping relationship between the target bus moment and the standard clock moment, and sending the time mapping relationship to a transmission node in the high-speed industrial bus system for clock synchronization. This method can reduce control overhead when achieving accurate clock synchronization across the entire network.

Description

Technical Field

[0001] The present invention relates to the field of industrial control and communication technology, and in particular to a clock synchronization method, a high-speed industrial bus system, equipment, and a storage medium. Background Art

[0002] High-speed industrial bus (AUTBUS) is a two-wire non-bridge medium with multi-node, high bandwidth, and time-sensitive industrial fieldbus.

[0003] In the existing technology, every node in the AUTBUS system needs to support the Precision Time Protocol to achieve time synchronization across the entire network. However, the message operation mechanism of the Precision Time Protocol brings certain control overhead, which limits the maximum data throughput to a certain extent. Summary of the Invention

[0004] The present invention provides a clock synchronization method, a high-speed industrial bus system, a device and a storage medium to solve the problem that each node needs to support a precise time protocol when performing clock synchronization in an AUTBUS system.

[0005] According to one aspect of the present invention, a clock synchronization method is provided, which is applied to a high-speed industrial bus system, wherein the high-speed industrial bus system includes a master control node and at least one transmission node. The method is executed by the master control node in the high-speed industrial bus system, and comprises:

[0006] When receiving the standard clock time sent by the timing module, the first local clock time currently updated is obtained. After startup, each node in the high-speed industrial bus system dynamically updates the local clock time.

[0007] When it is detected that the network-wide clock synchronization condition is met, the currently updated second local clock time and the current bus time of the high-speed industrial bus system are obtained;

[0008] Calculating a target bus time of the high-speed industrial bus system when the standard clock time is received based on the first local clock time, the second local clock time and the current bus time;

[0009] Local clock synchronization is performed based on the time mapping relationship between the target bus time and the standard clock time, and the time mapping relationship is sent to the transmission node in the high-speed industrial bus system for clock synchronization.

[0010] According to another aspect of the present invention, a clock synchronization method is provided, which is applied to a high-speed industrial bus system, wherein the high-speed industrial bus system includes a master control node and at least one transmission node. The method is executed by the transmission node in the high-speed industrial bus system, and includes:

[0011] When a time mapping relationship sent by a master control node in a high-speed industrial bus system is detected, a standard clock time in the time mapping relationship and a target bus time of the high-speed industrial bus system that matches the standard clock time are extracted;

[0012] Local clock synchronization is performed according to the standard clock time and the target bus time.

[0013] According to another aspect of the present invention, a clock synchronization device is provided, which is applied to a high-speed industrial bus system, wherein the high-speed industrial bus system includes a master control node and at least one transmission node. The device is executed by the master control node in the high-speed industrial bus system, and includes:

[0014] A first local clock time acquisition module is used to obtain the currently updated first local clock time when receiving the standard clock time sent by the timing module. After startup, each node in the high-speed industrial bus system dynamically updates the local clock time;

[0015] The current bus time acquisition module is used to obtain the currently updated second local clock time and the current bus time of the high-speed industrial bus system when it is detected that the clock synchronization conditions of the entire network are met;

[0016] a target bus time calculation module, configured to calculate a target bus time of the high-speed industrial bus system when the standard clock time is received based on the first local clock time, the second local clock time and the current bus time;

[0017] The time mapping relationship sending module is used to perform local clock synchronization based on the time mapping relationship between the target bus time and the standard clock time, and send the time mapping relationship to the transmission node in the high-speed industrial bus system for clock synchronization.

[0018] According to another aspect of the present invention, a clock synchronization device is provided, which is applied to a high-speed industrial bus system. The high-speed industrial bus system includes a master control node and at least one transmission node. The method is executed by the transmission node in the high-speed industrial bus system. The device includes:

[0019] A target bus time extraction module is used to extract the standard clock time in the time mapping relationship and the target bus time of the high-speed industrial bus system that matches the standard clock time when detecting the time mapping relationship sent by the master control node in the high-speed industrial bus system;

[0020] The local clock synchronization module is used to synchronize the local clock according to the standard clock time and the target bus time.

[0021] According to another aspect of the present invention, a high-speed industrial bus system is provided, comprising a master control node and at least one transmission node, wherein:

[0022] The master control node is configured to obtain a currently updated first local clock time upon receiving the standard clock time sent by the timing module;

[0023] Wherein, each node in the high-speed industrial bus system dynamically updates the local clock time after startup;

[0024] The master control node is configured to, upon detecting that a network-wide clock synchronization condition is met, obtain the currently updated second local clock time and the current bus time of the high-speed industrial bus system; calculate, based on the first local clock time, the second local clock time, and the current bus time, the target bus time of the high-speed industrial bus system upon receiving the standard clock time; perform local clock synchronization based on a time mapping relationship between the target bus time and the standard clock time, and send the time mapping relationship to a transmission node in the high-speed industrial bus system;

[0025] Each of the transmission nodes is used to extract the standard clock moment in the time mapping relationship and the target bus moment of the high-speed industrial bus system that matches the standard clock moment when detecting the time mapping relationship sent by the master node in the high-speed industrial bus system; and perform local clock synchronization according to the standard clock moment and the target bus moment.

[0026] According to another aspect of the present invention, an electronic device is provided, comprising:

[0027] at least one processor; and

[0028] a memory communicatively connected to the at least one processor; wherein,

[0029] The memory stores a computer program executable by the at least one processor. The computer program is executed by the at least one processor so that the at least one processor can perform the clock synchronization method described in any embodiment of the present invention.

[0030] According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the clock synchronization method according to any embodiment of the present invention when executed.

[0031] The technical solution of the embodiment of the present invention is as follows: when receiving the standard clock moment sent by the timing module, the currently updated first local clock moment is obtained, and each node in the high-speed industrial bus system dynamically updates the local clock moment after startup; when detecting that the clock synchronization condition of the entire network is met, the currently updated second local clock moment and the current bus moment of the high-speed industrial bus system are obtained; based on the first local clock moment, the second local clock moment and the current bus moment, the target bus moment of the high-speed industrial bus system when the standard clock moment is received is calculated; local clock synchronization is performed according to the time mapping relationship between the target bus moment and the standard clock moment, and the time mapping relationship is sent to the transmission node in the high-speed industrial bus system for clock synchronization, thereby solving the problem that each node needs to support the precise time protocol when performing clock synchronization in the AUTBUS system, and realizing that when performing precise clock synchronization of the entire network in the AUTBUS system, only the master node needs to support the precise time protocol, thereby reducing the control overhead.

[0032] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present invention, nor is it intended to limit the scope of the present invention. Other features of the present invention will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0034] Figure 1 This is a flowchart of a clock synchronization method provided according to the first embodiment of the present invention;

[0035] Figure 2 This is a flowchart of a clock synchronization method provided according to the second embodiment of the present invention;

[0036] Figure 3 This is a schematic structural diagram of a clock synchronization device provided according to a third embodiment of the present invention;

[0037] Figure 4 This is a structural diagram of a clock synchronization device provided according to a fourth embodiment of the present invention;

[0038] Figure 5a This is a schematic diagram of the structure of a high-speed industrial bus system provided according to a fifth embodiment of the present invention;

[0039] Figure 5bThis is a flowchart of clock synchronization in a high-speed industrial bus system provided by Embodiment 5 of the present invention;

[0040] Figure 5c This is a timing diagram of clock synchronization in a high-speed industrial bus system according to a fifth embodiment of the present invention;

[0041] Figure 6 The figure is a schematic structural diagram of an electronic device for implementing the clock synchronization method according to an embodiment of the present invention. DETAILED DESCRIPTION

[0042] In order to enable those skilled in the art to better understand the solutions of the present invention, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the embodiments described are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts should fall within the scope of protection of the present invention.

[0043] It should be noted that the terms "first", "second", etc. in the description and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that the numbers used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0044] Example 1

[0045] Figure 1 This is a flowchart of a clock synchronization method provided according to the first embodiment of the present invention. This embodiment is applicable to the situation where the master node and the transmission node in the AUTBUS system perform clock synchronization at the application layer. Specifically, the method can be application layer clock synchronization based on the synchronization of the physical layer clock in the AUTBUS system. The physical layer clock synchronization method can be a pilot-based clock synchronization mechanism or a cyclic prefix-based clock synchronization mechanism. The method can be executed by the master node of the AUTBUS system. The AUTBUS system may include a master node and at least one transmission node. Figure 1 As shown, the method includes:

[0046] Step 110: Upon receiving the standard clock time sent by the timing module, obtain the currently updated first local clock time.

[0047] The timing module can be a master control node (CN) that imports a standard clock into the AUTBUS system through an external timing method. The standard clock can be the Beidou Positioning System (GPS) time, or the Universal Time (UTC), etc. UTC time is used as the standard clock below. UTC time can be a reference time accurate to nanoseconds generated by a signal according to the agreement between the timing parties. Specifically, UTC time can be expressed as "XX year XX month XX day - XX hour XX minute XX second XX millisecond XX microsecond XX nanosecond". The timing method of the timing module can use the second pulse (PPS) and the serial port output standard clock time (TOD) method, that is, the standard clock is imported into the CN using the PPS+TOD method. The CN can capture the arrival of the PPS and determine the first local clock time corresponding to this time. When the CN captures the PPS, it can obtain the standard clock time (denoted as UTC_T0) in the TOD.

[0048] After startup, each node in a high-speed industrial bus system dynamically updates its local clock time. In an AUTBUS system, physical layer clock synchronization can use the local clock on the network (CN) side as the clock source. This means that the bus clock (ATB) of the high-speed industrial bus system and the local clock (CNT) on the CN side are co-sourced.

[0049] In an optional implementation of an embodiment of the present invention, when the standard clock moment sent by the timing module is received, the currently updated first local clock moment is obtained, including: capturing the signal edge change of the standard clock moment sent by the timing module through a capture comparison pulse modulation CCP module; and using the count value of the CCP module corresponding to the signal edge change as the first local clock moment.

[0050] The capture function in the Capture Compare PWM (CCP) module accurately captures the edge changes of the PPS signal. When the CCP module captures the edge change, it records the local clock-driven count corresponding to the PPS moment and uses this count value as the first local clock time (denoted as CNT_T0), thereby obtaining a precise second count.

[0051] Step 120: When it is detected that the network-wide clock synchronization condition is met, the currently updated second local clock time and the current bus time of the high-speed industrial bus system are obtained.

[0052] The network-wide clock synchronization condition may be when the CN sends a time mapping relationship to the TN for clock synchronization. Specifically, the network-wide clock synchronization condition may be when the CN sends the time mapping relationship at the first symbol interruption. Sending the time mapping relationship at this time can improve the accuracy of clock synchronization. The time mapping relationship can be sent by encapsulating it into a frame and broadcasting it to the entire network.

[0053] The second local clock time (denoted as CNT_T1) may be the local clock time corresponding to when the time mapping relationship is broadcasted to the entire network. The current bus time (denoted as ATB_T1) notified to the industrial bus system may be the bus clock time corresponding to when the time mapping relationship is broadcasted to the entire network.

[0054] Step 130: Calculate the target bus time of the high-speed industrial bus system when the standard clock time is received based on the first local clock time, the second local clock time and the current bus time.

[0055] The ATB clock of the high-speed industrial bus system and the CNT clock on the communication network (CN) are co-originating, so there is no frequency offset between the two. The ATB clock can be a time representation mechanism derived from the communication mechanism within the AUTBUS network. For example, the ATB clock can be expressed in a frame-symbol-sample format, similar to the hierarchical relationship of hours, minutes, and seconds. The time represented by the frame and symbol units can be related to the specific communication configuration mode, while the sample unit can be fixed, such as 40 nanoseconds. The CNT clock can be a clock recorded using the CN's counting method.

[0056] The ATB and CNT clocks may have different representation mechanisms, but the time difference between ATB_T1 and the target bus time of the high-speed industrial bus system (denoted as ATB_T0) is the same as the time difference between CNT_T1 and CNT_T0. Therefore, the precise ATB_T0 at the time the CN receives the standard clock can be obtained based on CNT_T0, CNT_T1, and ATB_T1.

[0057] Specifically, in an optional implementation of an embodiment of the present invention, the target bus moment of the high-speed industrial bus system is calculated when the standard clock moment is received based on the first local clock moment, the second local clock moment and the current bus moment, including: calculating the local clock offset value between the second local clock moment and the first local clock moment; and determining the difference obtained by subtracting the local clock offset value from the current bus moment as the target bus moment.

[0058] The difference between CNT_T1 and CNT_T0 is the local clock offset value (denoted as ΔCNT0), that is, ΔCNT0 = CNT_T1 - CNT_T0. ATB_T0 = ATB_T1 - (CNT_T1 - CNT_T0).

[0059] Step 140: Perform local clock synchronization based on the time mapping relationship between the target bus time and the standard clock time, and send the time mapping relationship to the transmission node in the high-speed industrial bus system for clock synchronization.

[0060] The time mapping relationship may be a mapping between UTC_T0 and ATB_T0. When the CN performs local clock synchronization, the local clock may be synchronized and calibrated with the standard clock. Specifically, the difference between ATB_T0 and UTC_T0 may be added to the local clock. The CN may also send the time mapping relationship to the TN, and the TN may perform clock synchronization based on the time mapping relationship. Specifically, the TN may synchronize absolute time based on the difference between ATB_T0 and UTC_T0.

[0061] In an optional implementation of an embodiment of the present invention, before sending the time mapping relationship to the transmission node in the high-speed industrial bus system for clock synchronization, it also includes: adding the local clock offset value to the time mapping relationship so that the transmission node can perform frequency deviation correction in clock synchronization based on the local clock offset value.

[0062] After startup, each node in a high-speed industrial bus system dynamically updates its local clock time. The local clocks on the TN side and the local clocks on the CN side are not synchronized. That is, the local clocks on the TN side and the ATB are not co-originating. A frequency offset exists between the local clocks on the TN side and the ATB. When the CN sends the time mapping, sending ΔCNT0 enables the TN to perform frequency offset correction in addition to absolute time correction, improving clock synchronization accuracy and ensuring continuous clock synchronization.

[0063] The technical solution of this embodiment is to obtain the currently updated first local clock moment when receiving the standard clock moment sent by the timing module, and each node in the high-speed industrial bus system dynamically updates the local clock moment after startup; when it is detected that the clock synchronization conditions of the entire network are met, the currently updated second local clock moment and the current bus moment of the high-speed industrial bus system are obtained; based on the first local clock moment, the second local clock moment and the current bus moment, the target bus moment of the high-speed industrial bus system when the standard clock moment is received is calculated; local clock synchronization is performed according to the time mapping relationship between the target bus moment and the standard clock moment, and the time mapping relationship is sent to the transmission node in the high-speed industrial bus system for clock synchronization, which solves the problem that each node needs to support the precise time protocol when performing clock synchronization in the AUTBUS system, and achieves that high-precision clock synchronization can still be achieved when only the master node supports the precise time protocol, which can reduce control overhead.

[0064] Example 2

[0065] Figure 2 This is a flowchart of a clock synchronization method provided according to the second embodiment of the present invention. This embodiment is applicable to the situation where the master node and the transmission node in the AUTBUS system perform clock synchronization at the application layer. Specifically, the method can be an application layer clock synchronization based on the synchronization of the physical layer clock in the AUTBUS system. The method can be executed by the transmission node of the AUTBUS system. The AUTBUS system may include a master node and at least one transmission node. The technical solution in this embodiment can be combined with the various optional solutions in one or more of the above-mentioned implementation methods to achieve clock synchronization between the master node and the transmission node in the AUTBUS system.

[0066] like Figure 2 As shown, the method includes:

[0067] Step 210: When the time mapping relationship sent by the master control node in the high-speed industrial bus system is detected, the standard clock time in the time mapping relationship and the target bus time of the high-speed industrial bus system matching the standard clock time are extracted.

[0068] Step 220: Perform local clock synchronization according to the standard clock time and the target bus time.

[0069] The TN side can synchronize absolute time based on the difference between ATB_T0 and UTC_T0.

[0070] Based on the above implementation, optionally, the method further includes: extracting a local clock offset value used by the master control node to determine the target bus time in the time mapping relationship; and performing frequency offset correction in clock synchronization according to the local clock offset value.

[0071] There is a frequency offset between the local clock on the TN side and the ATB. The TN extracts ΔCNT0 from the time mapping relationship and can perform frequency offset correction based on absolute time correction based on ΔCNT0, improving clock synchronization accuracy and ensuring continuous clock synchronization. Specifically, frequency offset correction can be performed using pulse width modulation (PWM) correction.

[0072] In an optional implementation of an embodiment of the present invention, frequency offset correction in clock synchronization is performed based on the local clock offset value, including: obtaining the synchronous bus moment of the high-speed industrial bus system corresponding to the clock synchronization, and determining the bus clock offset value between the synchronous bus moment and the target bus moment; determining the phase correction in the frequency offset correction based on the target offset value between the bus clock offset value and the local clock offset value, and the frequency difference coefficient between the bus clock and the local clock of the transmission node; determining the frequency correction in the frequency offset correction based on the local clock offset value and the frequency difference coefficient.

[0073] The synchronous bus time (denoted as ATB_T2) can be the bus time of the high-speed industrial bus system when the TN side receives the time mapping relationship for clock synchronization. The bus clock offset value can be ATB_T2-ATB_T0. Specifically, the phase correction can be determined by the formula XT=ΔCNT0 / ΔF-(ATB_T2-ATB_T0) / ΔF. The frequency correction can be determined by the formula XT=ΔCNT0 / ΔF, where ΔF is the frequency difference coefficient.

[0074] The technical solution of this embodiment, when detecting the time mapping relationship sent by the master node in the high-speed industrial bus system, extracts the standard clock moment in the time mapping relationship and the target bus moment of the high-speed industrial bus system that matches the standard clock moment; performs local clock synchronization according to the standard clock moment and the target bus moment, thereby solving the problem that when performing clock synchronization in the AUTBUS system, each node needs to support the precise time protocol. When performing precise clock synchronization of the entire network in the AUTBUS system, high-precision clock synchronization can be achieved without the need for transmission nodes to support the precise time protocol, thereby reducing the control overhead.

[0075] Example 3

[0076] Figure 3This is a schematic diagram of the structure of a clock synchronization device provided according to the third embodiment of the present invention. The device is applied to a high-speed industrial bus system, which includes a master control node and at least one transmission node; the master control node in the high-speed industrial bus system executes the control. Figure 3 As shown, the device includes: a first local clock time acquisition module 310, a current bus time acquisition module 320, a target bus time calculation module 330 and a time mapping relationship sending module 340. Among them:

[0077] The first local clock time acquisition module 310 is used to obtain the currently updated first local clock time when receiving the standard clock time sent by the timing module. After startup, each node in the high-speed industrial bus system dynamically updates the local clock time;

[0078] The current bus time acquisition module 320 is used to acquire the currently updated second local clock time and the current bus time of the high-speed industrial bus system when it is detected that the network-wide clock synchronization condition is met;

[0079] a target bus time calculation module 330 for calculating a target bus time of the high-speed industrial bus system when the standard clock time is received based on the first local clock time, the second local clock time and the current bus time;

[0080] The time mapping relationship sending module 340 is used to perform local clock synchronization according to the time mapping relationship between the target bus time and the standard clock time, and send the time mapping relationship to the transmission node in the high-speed industrial bus system for clock synchronization.

[0081] Optionally, the first local clock time acquisition module 310 includes:

[0082] The signal edge change capture unit is used to capture the signal edge change of the standard clock moment sent by the timing module through the capture comparison pulse modulation CCP module;

[0083] The first local clock time acquisition unit is configured to use the count value of the CCP module corresponding to the signal edge change as the first local clock time.

[0084] Optionally, the target bus time calculation module 330 includes:

[0085] a local clock offset value calculation unit, configured to calculate a local clock offset value between the second local clock time and the first local clock time;

[0086] The target bus time determination unit is used to determine the difference obtained by subtracting the local clock offset value from the current bus time as the target bus time.

[0087] Optionally, the device further includes:

[0088] The local clock offset value sending module is used to add the local clock offset value to the time mapping relationship before sending the time mapping relationship to the transmission node in the high-speed industrial bus system for clock synchronization, so that the transmission node can perform frequency offset correction in clock synchronization based on the local clock offset value.

[0089] The clock synchronization device provided in the embodiment of the present invention can execute the clock synchronization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0090] Example 4

[0091] Figure 4 This is a schematic diagram of the structure of a clock synchronization device provided according to the fourth embodiment of the present invention. The device is applied to a high-speed industrial bus system, which includes a master control node and at least one transmission node; and is executed by the transmission node in the high-speed industrial bus system. Figure 4 As shown, the device includes: a target bus time extraction module 410 and a local clock synchronization module 420. Among them:

[0092] The target bus time extraction module 410 is configured to extract the standard clock time in the time mapping relationship and the target bus time of the high-speed industrial bus system that matches the standard clock time when detecting the time mapping relationship sent by the master control node in the high-speed industrial bus system;

[0093] The local clock synchronization module 420 is used to synchronize the local clock according to the standard clock time and the target bus time.

[0094] Optionally, the device further includes:

[0095] A local clock offset value extraction module is used to extract the local clock offset value used by the master node to determine the target bus time in the time mapping relationship;

[0096] The frequency offset correction module is used to perform frequency offset correction in clock synchronization according to the local clock offset value.

[0097] Optional frequency offset correction module, including:

[0098] A bus clock offset value determining unit is used to obtain the synchronous bus time of the high-speed industrial bus system corresponding to the clock synchronization, and determine the bus clock offset value between the synchronous bus time and the target bus time;

[0099] A phase correction unit, configured to determine a phase correction in frequency offset correction based on a target offset value between a bus clock offset value and a local clock offset value, and a frequency difference coefficient between the bus clock and a local clock of a transmission node;

[0100] The frequency correction unit is used to determine the frequency correction in the frequency deviation correction according to the local clock offset value and the frequency difference coefficient.

[0101] The clock synchronization device provided in the embodiment of the present invention can execute the clock synchronization method provided in any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0102] Example 5

[0103] Figure 5a Schematic diagram of a high-speed industrial bus system according to the fifth embodiment of the present invention. Figure 5a As shown, the high-speed industrial bus system 500 includes a master control node 510 and at least one transmission node 520, wherein:

[0104] The master control node is configured to obtain a currently updated first local clock moment upon receiving a standard clock moment sent by a timing module; wherein each node in the high-speed industrial bus system dynamically updates the local clock moment after startup; the master control node is configured to obtain a currently updated second local clock moment and a current bus moment of the high-speed industrial bus system upon detecting that a network-wide clock synchronization condition is met; calculate a target bus moment of the high-speed industrial bus system upon receiving the standard clock moment based on the first local clock moment, the second local clock moment, and the current bus moment; perform local clock synchronization based on a time mapping relationship between the target bus moment and the standard clock moment, and send the time mapping relationship to a transmission node in the high-speed industrial bus system;

[0105] Each transmission node is used to extract the standard clock time in the time mapping relationship and the target bus time of the high-speed industrial bus system that matches the standard clock time when detecting the time mapping relationship sent by the master node in the high-speed industrial bus system; and perform local clock synchronization according to the standard clock time and the target bus time.

[0106] Based on the above implementation, optionally, the master control node is used to capture the signal edge change of the standard clock moment sent by the timing module by capturing the comparison pulse modulation CCP module; and use the count value of the CCP module corresponding to the signal edge change as the first local clock moment.

[0107] In an optional implementation manner of the embodiment of the present invention, the master control node is used to calculate a local clock offset value between the second local clock time and the first local clock time; and determine the difference obtained by subtracting the local clock offset value from the current bus time as the target bus time.

[0108] In an optional implementation of an embodiment of the present invention, the master control node is used to add a local clock offset value to the time mapping relationship before sending the time mapping relationship to the transmission node in the high-speed industrial bus system for clock synchronization, so that the transmission node can perform frequency deviation correction in clock synchronization based on the local clock offset value.

[0109] In an optional implementation of the embodiment of the present invention, each transmission node is further used to extract the local clock offset value used by the master node to determine the target bus time in the time mapping relationship; and perform frequency offset correction in clock synchronization based on the local clock offset value.

[0110] In an optional implementation of an embodiment of the present invention, each transmission node is used to obtain the synchronous bus moment of the high-speed industrial bus system corresponding to the clock synchronization, and determine the bus clock offset value between the synchronous bus moment and the target bus moment; determine the phase correction in the frequency offset correction based on the target offset value between the bus clock offset value and the local clock offset value, and the frequency difference coefficient between the bus clock and the local clock of the transmission node; determine the frequency correction in the frequency offset correction based on the local clock offset value and the frequency difference coefficient.

[0111] The high-speed industrial bus system provided by the embodiment of the present invention uses a clock synchronization method between a master control node and a transmission node. Only the master control node needs to support the precise time protocol. The transmission node can perform clock synchronization based on the time mapping relationship sent by the master control node, thereby achieving the effect of reducing control overhead while ensuring high-precision clock synchronization.

[0112] Figure 5b This is a flowchart of clock synchronization in a high-speed industrial bus system according to the fifth embodiment of the present invention. Figure 5b As shown, the absolute UTC time can be imported into the time synchronization network of the AUTBUS system through the timing module, and the specific import node can be selected as the CN node. The timing module can be imported in the PPS+TOD method, where PPS provides the standard time at the quasi-second level, and TOD is the UTC time (string) output by the serial port. The CN side can capture the PPS signal edge changes through the CCP module and record the count value CNT_T0 driven by the local clock. The CN side can use PPS as the standard to perform time synchronization calibration records. Specifically, the CN side can obtain UTC_T0 from the TOD statement and align ATB_T0 with UTC_T0. In addition, the CN side can encapsulate the time mapping relationship between ATB_T0 and UTC_T0 and broadcast it to each TN node.

[0113] Specifically, the CN side can interrupt the sending time mapping relationship at the first symbol. At this time, the CN side has time ATB_T1 and CNT_T1. Based on ATB_T1, CNT_T1 and CNT_T0, the CN can determine ATB_T0. Wherein, ATB_T0=ATB_T1-(CNT_T1-CNT_T0).

[0114] Furthermore, the difference between CNT_T1 and CNT_T0 can be recorded as ΔCNT0, that is, ΔCNT0 = CNT_T1 - CNT_T0. When CN sends the time mapping relationship, it can send ΔCNT0 synchronously.

[0115] like Figure 5b As shown, the TN node can update and save the time mapping relationship to generate a timestamp. TN can also perform frequency offset correction of the second pulse through ΔCNT0. Specifically, the TN node receives the time mapping relationship, obtains the time mapping relationship between ATB_T0 and UTC_T0, and aligns the absolute time with the standard clock according to the time mapping relationship. Furthermore, the TN node determines the phase correction and frequency correction in the frequency offset correction based on ΔCNT0. Specifically, the phase correction can be determined by the formula XT=ΔCNT0 / ΔF-(ATB_T2-ATB_T0) / ΔF. The frequency correction can be determined by the formula XT=ΔCNT0 / ΔF. Wherein, ΔF is the frequency difference coefficient.

[0116] Figure 5c This is a timing diagram of clock synchronization in a high-speed industrial bus system according to the fifth embodiment of the present invention. Figure 5cAs shown, at time T0, the timing module can import UTC_T0 into the central processing unit (CPU) of the CN in the form of PPS + TOD. The CN's CPU can obtain the PPS time through the CCP module's CAP (capture function) and record CNT_T0. The CN's CPU can read the TOD statement to obtain UTC_T0. The CN's AUTBUS MAC (media access control layer) broadcasts a symbol interrupt at time T1, obtains CNT_T1 by reading the CCP module's clock, and obtains ATB_T1 by reading the bus clock of the high-speed industrial bus. Thus, the CN can convert ATB_T0 and determine ΔCNT0. At T1, the time mapping relationship between ATB_T0 and UTC_T0, as well as ΔCNT0, is encapsulated to generate a T0 mapping table for broadcast. The CN can broadcast this in a designated symbol interrupt to improve clock synchronization accuracy. For example, the broadcast can be performed in the first or third symbol interrupt. When the TN receives the T0 mapping table at time T2, it uses the symbol interrupt to retrieve the time mapping relationship between ATB_T0 and UTC_T0, as well as ΔCNT0, from the T0 mapping table. It then reads the bus clock of the high-speed industrial bus to obtain ATB_T2. The TN can then adjust the absolute time based on the time mapping relationship between ATB_T0 and UTC_T0, configure the PWM function time based on CNT0, and determine the frequency offset correction.

[0117] Example 6

[0118] Figure 6 A schematic diagram of the structure of an electronic device 10 that can be used to implement an embodiment of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processing, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0119] like Figure 6As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc., which is communicatively connected to the at least one processor 11. The memory stores a computer program that can be executed by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. Various programs and data required for the operation of the electronic device 10 can also be stored in the RAM 13. The processor 11, ROM 12, and RAM 13 are connected to each other via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0120] Multiple components in the electronic device 10 are connected to the I / O interface 15, including an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disk, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0121] The processor 11 may be any general-purpose and / or specialized processing component with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various specialized artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the clock synchronization method.

[0122] In some embodiments, the clock synchronization method can be implemented as a computer program that is tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the clock synchronization method described above can be performed. Alternatively, in other embodiments, processor 11 can be configured to perform the clock synchronization method in any other suitable manner (e.g., by means of firmware).

[0123] Various embodiments of the systems and techniques described herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0124] Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowcharts and / or block diagrams are implemented. The computer program may be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0125] In the context of the present invention, computer-readable storage media can be tangible media that can contain or store a computer program for use with an instruction execution system, device or equipment or used in combination with an instruction execution system, device or equipment. Computer-readable storage media can include but are not limited to electronic, magnetic, optical, electromagnetic, infrared or semiconductor systems, devices or equipment, or any suitable combination of the foregoing. Alternatively, computer-readable storage media can be machine-readable signal media. More specific examples of machine-readable storage media can include electrical connections based on one or more lines, portable computer disks, hard disks, random access memories (RAM), read-only memories (ROM), erasable programmable read-only memories (EPROM or flash memory), optical fibers, portable compact disk read-only memories (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0126] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0127] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

[0128] A computing system may include clients and servers. The clients and servers are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host. This server is a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services.

[0129] It should be understood that the various forms of the processes shown above can be used to reorder, add, or delete steps. For example, the steps described in the present invention can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved. This is not limited herein.

[0130] The above specific embodiments do not limit the scope of protection of the present invention. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention are intended to be included within the scope of protection of the present invention.

Claims

1. A clock synchronization method, applied to a high-speed industrial bus system, wherein the high-speed industrial bus system includes a master control node and at least one transmission node; the method is executed by the master control node in the high-speed industrial bus system, characterized in that: include: When receiving the standard clock time sent by the timing module, the first local clock time currently updated is obtained. After startup, each node in the high-speed industrial bus system dynamically updates the local clock time. When it is detected that the network-wide clock synchronization condition is met, the currently updated second local clock time and the current bus time of the high-speed industrial bus system are obtained; Calculating a target bus time of the high-speed industrial bus system when the standard clock time is received based on the first local clock time, the second local clock time and the current bus time; Local clock synchronization is performed based on the time mapping relationship between the target bus time and the standard clock time, and the time mapping relationship is sent to the transmission node in the high-speed industrial bus system for clock synchronization.

2. The method according to claim 1, characterized in that When receiving the standard clock time sent by the timing module, obtain the currently updated first local clock time, including: Capturing the signal edge change of the standard clock moment sent by the timing module by the capture comparison pulse modulation CCP module; The count value of the CCP module corresponding to the signal edge change is used as the first local clock time.

3. The method according to claim 1, characterized in that Calculating a target bus time of the high-speed industrial bus system when the standard clock time is received based on the first local clock time, the second local clock time, and the current bus time, including: Calculating a local clock offset between the second local clock time and the first local clock time; The difference obtained by subtracting the local clock offset value from the current bus time is determined as the target bus time.

4. The method according to claim 3, characterized in that Before sending the time mapping relationship to the transmission nodes in the high-speed industrial bus system for clock synchronization, the following steps are also included: The local clock offset value is added to the time mapping relationship, so that the transmitting node can perform frequency offset correction in clock synchronization according to the local clock offset value.

5. A clock synchronization method, applied to a high-speed industrial bus system, wherein the high-speed industrial bus system includes a master control node and at least one transmission node; the method is executed by the transmission node in the high-speed industrial bus system, characterized in that: include: When a time mapping relationship sent by a master control node in a high-speed industrial bus system is detected, a standard clock time in the time mapping relationship and a target bus time of the high-speed industrial bus system that matches the standard clock time are extracted; Local clock synchronization is performed according to the standard clock time and the target bus time.

6. The clock synchronization method according to claim 5, wherein: Also includes: Extracting a local clock offset value used by the master control node when determining the target bus time in the time mapping relationship; Frequency offset correction in clock synchronization is performed according to the local clock offset value.

7. The clock synchronization method according to claim 6, wherein: Performing frequency offset correction in clock synchronization according to the local clock offset value includes: Acquire a synchronous bus time of the high-speed industrial bus system corresponding to clock synchronization, and determine a bus clock offset value between the synchronous bus time and the target bus time; Determining a phase correction in frequency offset correction according to a target offset value between the bus clock offset value and the local clock offset value, and a frequency difference coefficient between the bus clock and a local clock of the transmitting node; A frequency correction in frequency offset correction is determined according to the local clock offset value and the frequency difference coefficient.

8. A high-speed industrial bus system, characterized in that: The high-speed industrial bus system includes a master control node and at least one transmission node, wherein: The master control node is configured to obtain a currently updated first local clock time upon receiving the standard clock time sent by the timing module; Wherein, each node in the high-speed industrial bus system dynamically updates the local clock time after startup; The master control node is configured to, upon detecting that a network-wide clock synchronization condition is met, obtain the currently updated second local clock time and the current bus time of the high-speed industrial bus system; calculate, based on the first local clock time, the second local clock time, and the current bus time, the target bus time of the high-speed industrial bus system upon receiving the standard clock time; perform local clock synchronization based on a time mapping relationship between the target bus time and the standard clock time, and send the time mapping relationship to a transmission node in the high-speed industrial bus system; Each of the transmission nodes is used to extract the standard clock moment in the time mapping relationship and the target bus moment of the high-speed industrial bus system that matches the standard clock moment when detecting the time mapping relationship sent by the master node in the high-speed industrial bus system; and perform local clock synchronization according to the standard clock moment and the target bus moment.

9. An electronic device, characterized in that: The electronic device comprises: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to perform the clock synchronization method according to any one of claims 1 to 4 or 5 to 7.

10. A computer-readable storage medium, characterized in that The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the clock synchronization method according to any one of claims 1 to 4 or 5 to 7 when executed.

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