A noise suppression circuit applied to a direct time-of-flight lidar

Abstract

The present invention provides a noise suppression circuit for direct time-of-flight lidar. The designed correlation detection background noise filtering circuit filters out background light noise by accumulating voltages of the specified level. When a threshold is reached, a VALID signal is generated and output to a reset signal generating circuit. This circuit eliminates dead time while significantly reducing the area of existing circuits. When integrated on-chip with a photosensitive element, it can improve the fill rate and photon detection efficiency. In addition, the circuit designed by the present invention uses TDC self-feedback to control the time window through a reset signal generating circuit. Compared with existing voltage-controlled delay unit circuits, this simplifies the circuit structure, and the window width can be precisely controlled through external programming.

Description

Technical Field

[0001] The present invention belongs to the technical field of laser radar chip design, and in particular relates to a noise suppression circuit applied to direct time-of-flight laser radar. Background Art

[0002] When operating in outdoor environments with strong background light, the single-photon avalanche diode (SPAD), a photosensitive element in a LiDAR, may be prematurely triggered by noise during the detection cycle, ignoring subsequent laser echo signals and recording erroneous information. This accumulation effect of background light causes the valid signal to be buried in the noise, reducing the signal-to-noise ratio (SNR) and affecting the LiDAR's detection range. To suppress background noise interference and extend the ranging range, considering that background light is randomly distributed throughout the time interval, while the laser signal follows a Gaussian distribution within a very narrow interval, temporal and spatial correlation detection of the incoming signal can be used to suppress background noise interference, improve the SNR, and extend the LiDAR's detection range. Another benefit of implementing a correlation detection circuit is that it allows for on-chip signal processing, reducing the amount of data required for readout and processing, lowering the readout rate requirements for the I / O interface, and simplifying the logic of subsequent processing circuits. Existing signal correlation detection circuits are generally based on shift register or classifier circuit structures.

[0003] Correlation detection circuit based on shift register structure Figure 1 As shown, each event (EVENTS) pulse shifts the logic "1" in the shift register after pulse width compression and logic tree synthesis, where the shift register is initialized to zero value through the reset signal (RST), and the data selector that can be externally programmed and controlled selects the register output corresponding to the threshold number of photons to achieve the output of VALID after the expected number of signals are detected within a certain time window, indicating that the signal is a valid signal after filtering.

[0004] The logic of the correlation detection circuit based on the classifier is as follows Figure 2 As shown, Figure 2 This paper demonstrates a correlation detection circuit structure based on a 4-bit classifier. The 4-bit classifier is composed of five 2-bit classifiers connected as shown in the figure, while the 2-bit classifier consists of a NAND gate and a NOR gate. The circuit realizes correlation detection and threshold programming control for the four event signals in the pixel through an external control signal (SEL). When the number of high input signals at the same time is greater than the threshold, the output signal VALID flips to a valid high level.

[0005] Existing time window generation circuits are generally based on Figure 3In the voltage-controlled delay unit structure shown, when a photon is detected by the front-end circuitry and the EVENTS signal is generated, the Q output of D-type flip-flop DFF1 goes high. This rising edge is delayed by the voltage-controlled delay unit (VCDU). This delayed rising edge is then detected by DFF2. DFF1 and DFF2 remain high until they are reset by the RST signal, which is delayed by the reset delay line. This creates a time window whose width is set by the control voltage VTUNE.

[0006] A drawback of existing shift register-based correlation detection circuits is that when photon signals within a window are dense and the arrival time interval is short, even if pulse compression is performed on the event signal, dead time may still exist during logic synthesis, causing the high level of the previous signal to overlap the valid rising edge of the subsequent signal, resulting in photon counting errors. If correlation detection is required for event signals in more spatial locations, the circuit area based on the classifier structure will increase exponentially, significantly affecting the fill rate when integrated on-chip and reducing photon detection efficiency. Furthermore, the use of voltage-controlled delay cells in the time window generation logic requires the addition of an additional programmable reference voltage source, which consumes a large amount of circuit area. Furthermore, this control mode is significantly affected by process, voltage, and temperature (PVT) variations, and has limited accuracy and linearity. Summary of the Invention

[0007] In order to solve the above problems existing in the prior art, the present invention provides a noise suppression circuit for direct time-of-flight lidar. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0008] The present invention provides a noise suppression circuit for direct time-of-flight laser radar, comprising:

[0009] A photon arrival signal generating circuit is used to receive a photon event signal generated after a single photon avalanche diode of a front-end circuit breaks down, and to generate a level according to the event signal to an enable signal generating circuit and a correlation detection background noise filtering circuit;

[0010] The enable signal generating circuit is used to generate an enable signal after receiving the level to control the ring oscillator to start oscillation;

[0011] The ring oscillator is configured to oscillate and generate a clock under the control of an enable signal, and output the clock to a coarse quantization circuit and a fine quantization circuit, respectively, so that the coarse quantization circuit and the fine quantization circuit respectively perform corresponding quantization on the clock to obtain respective quantized data results;

[0012] The correlation detection background noise filtering circuit is used to accumulate the voltage of the level to filter the background light noise, and generate a VALID signal when a threshold is reached and output it to the reset signal generating circuit;

[0013] The reset signal generating circuit is used to access part of the quantized data selected from the coarse quantization data of the coarse quantization circuit, thereby determining a time window, and generating a reset signal within the time window according to different situations of whether the VALID signal is input to control the reset of the photon arrival signal generating circuit, the enable signal generating circuit, the ring oscillator, the coarse quantization circuit and the fine quantization circuit, thereby controlling the width of the time window, or waiting for a global reset signal to reset all circuits in the time-to-digital converter used for the lidar chip.

[0014] Optionally, generating a reset signal to control the reset of the photon arrival signal generation circuit, the enable signal generation circuit, the ring oscillator, the coarse quantization circuit, and the fine quantization circuit according to different situations of whether the VALID signal is input within the time window, thereby controlling the width of the time window, or waiting for a global reset signal to reset all circuits in the time-to-digital converter of the lidar chip includes:

[0015] If the VALID signal is not input within the time window, then when the current time window ends, a reset signal is generated to control the reset of the photon arrival signal generating circuit, the enable signal generating circuit, the ring oscillator, the coarse quantization circuit, and the fine quantization circuit, thereby controlling the width of the time window;

[0016] If the VALID signal is input within the time window, a global reset signal is waited for to reset all circuits in the time-to-digital converter of the lidar chip.

[0017] Optionally, the photon arrival signal generating circuit is composed of a D flip-flop DFF4, and the enable signal generating circuit is composed of NAND gates NAND1 and NAND2, an OR gate OR1, a D flip-flop DFF5 and an AND gate AND1;

[0018] Among them, the data output end of the D flip-flop DFF4 is respectively connected to the input ends of the NAND gates NAND1 and NAND2, the output ends of the NAND gates NAND1 and NAND2 are both connected to the input end of the OR gate OR1, the output end of the OR gate OR1 is connected to the data input end of the D flip-flop DFF5 and the first input end of the AND gate AND1, the output end of the D flip-flop DFF5 is connected to the second input end of the gate AND1, and the reset ends of the D flip-flops DFF4 and DFF5 are connected to the output end of the reset signal generating circuit.

[0019] Optionally, the correlation detection background noise filtering circuit comprises capacitors C, Cm, inverters INV1, INVa, INVb, INVc, INVd, D flip-flop DFF6, switch and a data selector MUX2_1;

[0020] The input end of the data selector MUX2_1 is connected to the input end of the photon arrival signal generator, the output end is connected to the input end of the inverter INVa, the output end of the inverter INVa is connected to the first end of the capacitor C, and the second end of the capacitor C is connected to the switch The first end and the input end of the inverter INV1, the switch The second end of the inverter and the output end of the inverter INV1 are connected to the input end of the inverter INVd, the output end of the inverter INVd is connected to the clock end of the D flip-flop DFF6, the data end of the D flip-flop DFF6 is connected to the power supply VDD, and the reset end of the D flip-flop DFF6 is connected to the output end of the reset signal generating circuit; the inverters INVb, INVc and capacitor Cm are connected in sequence, the input end of the inverter INVb is connected to the output end of the enable signal generating circuit, and the end of the capacitor Cm not connected to the inverter INVc is connected to the input end of the inverter INV1; the output end of the D flip-flop DFF6 outputs the VALID signal.

[0021] Optionally, the reset signal generating circuit is composed of a data selector MUX8_1, an inverter INV2, a NOR gate NOR1 and a NOR gate OR3;

[0022] Among them, the input end of the data selector MUX8_1 is connected to the part of the quantized data selected from the quantized data of the coarse quantization circuit, the output end is connected to the inverter INV2, the output end of the inverter INV2 is connected to the first input end of the NOT gate NOR1, the second input end of the NOT gate NOR1 is connected to the VALID signal, the output end of the NOT gate NOR1 is connected to the first input end of the NOT gate OR3, the second input end of the NOT gate OR3 is connected to the global reset signal GBRST, and the output end of the NOT gate OR3 outputs the reset signal RST.

[0023] Beneficial effects of the present invention:

[0024] The correlation detection background noise filtering circuit designed in this invention eliminates dead time while significantly reducing the area of existing circuits. When integrated on-chip with a photosensitive element, this circuit can improve fill rate and photon detection efficiency. Furthermore, the circuit designed in this invention uses TDC self-feedback to control the time window, simplifying the circuit structure compared to existing voltage-controlled delay unit circuits. The window width can be precisely controlled through external programming. This invention also reduces chip power consumption by using the TDC to reversely start and stop within the time window.

[0025] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 This is a traditional event-driven background noise filtering circuit diagram;

[0027] Figure 2 It is a traditional correlation detection circuit structure based on a 4-bit classifier;

[0028] Figure 3 Generate circuit diagrams for traditional time windows;

[0029] Figure 4 A schematic structural diagram of a time-to-digital converter with programmable time windows proposed in an embodiment of the present invention;

[0030] Figure 5 A schematic diagram of the structure of a photon arrival signal generating circuit and an enable signal generating circuit provided in an embodiment of the present invention;

[0031] Figure 6 A schematic diagram of the structure of a correlation detection background noise filtering circuit provided in an embodiment of the present invention;

[0032] Figure 7 An internal signal timing diagram of a correlation detection background noise filtering circuit provided by an embodiment of the present invention;

[0033] Figure 8 A schematic structural diagram of a reset signal generating circuit provided in an embodiment of the present invention;

[0034] Figure 9 This is a timing diagram of the internal signals of the enable signal, reset signal, and noise filtering circuit provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] The present invention will be further described in detail below with reference to specific examples, but the embodiments of the present invention are not limited thereto.

[0036] like Figure 4As shown, the present invention provides a noise suppression circuit for direct time-of-flight laser radar, comprising:

[0037] A photon arrival signal generating circuit is used to receive a photon event signal generated after a single photon avalanche diode of a front-end circuit breaks down, and to generate a level according to the event signal to an enable signal generating circuit and a correlation detection background noise filtering circuit;

[0038] The enable signal generating circuit is used to generate an enable signal after receiving the level to control the ring oscillator to start oscillation;

[0039] The ring oscillator is configured to oscillate and generate a clock under the control of an enable signal, and output the clock to a coarse quantization circuit and a fine quantization circuit, respectively, so that the coarse quantization circuit and the fine quantization circuit respectively perform corresponding quantization on the clock to obtain respective quantized data results;

[0040] It is worth noting that after the ring oscillator starts oscillating, the waveform of its internal oscillation is a sine wave, which is converted into a square wave with a certain frequency through the inverter, and then input as a clock signal into the quantization circuit composed of a counter at the back.

[0041] The correlation detection background noise filtering circuit is used to accumulate the voltage of the level to filter the background light noise, and generate a VALID signal when a threshold is reached and output it to the reset signal generating circuit;

[0042] The reset signal generating circuit is used to access part of the quantized data selected from the coarse quantization data of the coarse quantization circuit, thereby determining a time window, and generating a reset signal within the time window according to different situations of whether the VALID signal is input to control the reset of the photon arrival signal generating circuit, the enable signal generating circuit, the ring oscillator, the coarse quantization circuit and the fine quantization circuit, thereby controlling the width of the time window, or waiting for a global reset signal to reset all circuits in the time-to-digital converter used for the lidar chip.

[0043] If the reset signal generating circuit of the present invention does not input the VALID signal within the time window, then when the current time window ends, it generates a reset signal to control the reset of the photon arrival signal generating circuit, the enable signal generating circuit, the ring oscillator, the coarse quantization circuit, and the fine quantization circuit, thereby controlling the width of the time window;

[0044] If the VALID signal is input within the time window, a global reset signal is waited for to reset all circuits in the time-to-digital converter of the lidar chip.

[0045] refer to Figure 4In the front-end circuit, its own single-photon avalanche diode is quenched, the photon arrival signal generation circuit is reset and the photon event voltage signal is transmitted to the enable signal generation circuit and the correlation detection circuit. The enable signal generation circuit generates an enable signal EN to control the start-up of the ring oscillator and generates corresponding quantized data results through coarse and fine quantization circuits. At the same time, the VALID signal generated by the correlation detection circuit completes the filtering of background light noise. The VALID signal and the corresponding quantization output signal of the coarse quantization circuit selected by external encoding are input to the reset signal generation circuit, and the corresponding reset signal is generated to perform internal self-reset of the circuit, thereby controlling the width of the time window.

[0046] The main idea of the present invention is to provide a correlation detection background noise filtering circuit based on analog logic, which filters the background noise of the photon event signal to improve the pile-up distortion effect. Compared with the traditional counter-based filtering circuit, the advantage is that it can prevent the problem of the front signal overlapping the rising edge of the rear signal when integrating the event arrival signal, eliminate the dead time and greatly reduce the area of the circuit. In the application of more event detection units in the pixel, the correlation detection background noise filtering circuit designed by the present invention has a more significant advantage in saving area; at the same time, the output signal of the corresponding quantization circuit is selected by the data selector to control the width of the time window; and the power consumption of the chip is reduced by reverse starting and stopping within the time window.

[0047] like Figure 5 As shown, the photon arrival signal generating circuit of the present invention is composed of a D flip-flop DFF4, and the enable signal generating circuit is composed of NAND gates NAND1 and NAND2, an OR gate OR1, a D flip-flop DFF5 and an AND gate AND1;

[0048] Among them, the data output end of the D flip-flop DFF4 is respectively connected to the input ends of the NAND gates NAND1 and NAND2, the output ends of the NAND gates NAND1 and NAND2 are both connected to the input end of the OR gate OR1, the output end of the OR gate OR1 is connected to the data input end of the D flip-flop DFF5 and the first input end of the AND gate AND1, the output end of the D flip-flop DFF5 is connected to the second input end of the gate AND1, and the reset ends of the D flip-flops DFF4 and DFF5 are connected to the output end of the reset signal generating circuit.

[0049] Figure 5The present invention provides a front-end circuit, a photon arrival signal generating circuit, and an enable signal generating circuit. The single-photon avalanche diode (SPAD) in the front-end circuit uses a passive quenching mode. The SPAD is equivalent to a diode, operating in Geiger mode, or reverse bias. When a photon arrives, it experiences reverse breakdown, generating a large breakdown current. The NMOS resistor below acts as a jumper, generating a high voltage across its two ends. This reduces the voltage difference across the SPAD, allowing it to exit the breakdown state. Simultaneously, the current decreases, causing the diode's positive electrode voltage to decrease, thereby restoring the reverse bias state. When a photon signal arrives and an avalanche breakdown occurs, an event signal EVENT is generated through the D flip-flop DFF3; the photon arrival signal generating circuit is composed of the D flip-flop DFF4, which outputs a low level to the enable signal generating circuit when the EVENTS signal arrives, until the D flip-flop is reset when the RST signal arrives; the enable signal generating circuit is composed of NAND gates NAND1 and NAND2, OR gate OR1, D flip-flop DFF5 and AND gate AND1. After receiving the first time signal within the time window, the enable signal EN is output as a high level until the reset signal RST arrives to complete the reset, and the EN signal returns to a low level.

[0050] like Figure 6 As shown, the correlation detection background noise filtering circuit of the present invention is composed of capacitors C, Cm, inverters INV1, INVa, INVb, INVc, INVd, D trigger DFF6, switch and a data selector MUX2_1;

[0051] The input end of the data selector MUX2_1 is connected to the input end of the photon arrival signal generator, the output end is connected to the input end of the inverter INVa, the output end of the inverter INVa is connected to the first end of the capacitor C, and the second end of the capacitor C is connected to the switch The first end and the input end of the inverter INV1, the switch The second end of the inverter and the output end of the inverter INV1 are connected to the input end of the inverter INVd, the output end of the inverter INVd is connected to the clock end of the D flip-flop DFF6, the data end of the D flip-flop DFF6 is connected to the power supply VDD, and the reset end of the D flip-flop DFF6 is connected to the output end of the reset signal generating circuit; the inverters INVb, INVc and capacitor Cm are connected in sequence, the input end of the inverter INVb is connected to the output end of the enable signal generating circuit, and the end of the capacitor Cm not connected to the inverter INVc is connected to the input end of the inverter INV1; the output end of the D flip-flop DFF6 outputs the VALID signal.

[0052] refer to Figure 6 as well as Figure 7 , Figure 6 The figure shows the correlation background noise filtering circuit provided by the present invention; Figure 7 The internal signal timing diagram of the analog circuit logic correlation detection circuit provided by the present invention when the SEL threshold is set to 3 events. Figure 6 The Nakamoto structure uses the principle of charge conservation. In the pre-charging stage of capacitors C and Cm, the switches When EN is 0, it is connected and when EN is 1, it is disconnected, so that the enable signal EN remains at a low level, turning on the switch. The inverter INV1 is composed of feedback from the output signal to the input, so that the potential of the input and output points is maintained at VDD / 2. The SEL signal is set externally to set the threshold of the number of photon arrivals within a certain width time window that meets the correlation detection requirements. At the same time, the EN signal controls the 2-to-1 data selector to select the input SEL signal to pre-charge the capacitor. During the pre-charge phase, due to the voltage difference between the two ends of capacitor C, pre-charging is completed through switch S1. During the detection phase, the enable signal EN becomes high, controls the data selector to select the input photon event arrival signal, and disconnects the switch. At this time, the inverter INV1 operates as a comparator. When a photon event signal arrives, the voltage on the input side of the capacitor corresponding to the pixel is pulled to VDD. Due to the charge conservation of the node on the output side of the capacitor in the detection state, the voltage of node X also increases. When the threshold is reached, a rising edge signal is generated through the inverter and the subsequent BUFFER, triggering the D flip-flop DFF6 to generate the VALID signal. In addition, the structure incorporates an additional small capacitor, Cm, whose input is connected to ground during the precharge phase and to a constant VDD during the detection phase. This ensures that the voltage at node X is slightly greater than VDD / 2 when the number of events reaches the threshold, based on the charge conservation principle at node X. This ensures that the inverter flips correctly and generates the correct VALID signal, suppressing circuit noise interference. Furthermore, due to the operating characteristics of capacitor Cm, its capacitance and linearity requirements are not high, so it can be implemented using a MOS capacitor, further simplifying the circuit structure.

[0053] It is worth noting that the present invention adopts reverse start, that is, the entire TDC operating mode is reverse. General forward start means that the time counting starts at the beginning of the detection cycle and stops counting when the arrival of a valid signal is detected. The recorded time is the flight time from the laser emission to the reception. However, the problem is that if no valid signal is detected during the detection cycle using forward counting, the TDC will also be in an oscillating operating mode and generate power consumption. The present invention adopts a reverse start mode, which means that during the detection cycle, the TDC only starts working when a signal is detected and does not stop until the cycle signal ends. In this way, the flight time is obtained by subtracting the recorded time from the cycle time length. The advantage of this is that the TDC will not work if no photon arrival signal is detected during the cycle, thereby reducing power consumption.

[0054] refer to Figure 8 ,like Figure 8 The reset signal generating circuit provided by the present invention is shown in FIG. The reset signal generating circuit of the present invention is composed of a data selector MUX8_1, an inverter INV2, a NOR gate NOR1 and a NOR gate OR3;

[0055] Among them, the input end of the data selector MUX8_1 is connected to the part of the quantized data selected from the quantized data of the coarse quantization circuit, the output end is connected to the inverter INV2, the output end of the inverter INV2 is connected to the first input end of the NOT gate NOR1, the second input end of the NOT gate NOR1 is connected to the VALID signal, the output end of the NOT gate NOR1 is connected to the first input end of the NOT gate OR3, the second input end of the NOT gate OR3 is connected to the global reset signal GBRST, and the output end of the NOT gate OR3 outputs the reset signal RST.

[0056] It is worth noting that: the 8-bit data generated by the counter in the 12-bit output quantized data of the TDC is output to the 8-to-1 data selector, which selects the length of the time window corresponding to the quantized data of the corresponding bit by programming and controlling the 3-bit Ws code, and generates a reset signal RST under the control of the valid event VALID signal and the global reset signal GBRST.

[0057] like Figure 9 The figure shows the internal signal timing diagram of the enable signal, reset signal and noise filtering circuit provided by the embodiment of the present invention. The figure shows the timing relationship of the two situations in which the VALID signal is valid and invalid in two time windows. After the GBRST signal completes the global reset, in the first time window WIN_unvalid, the EVENT1 event signal generates the signal Q1 through the photon arrival signal generating circuit and generates the EN signal through the enable signal generating circuit to drive the TDC to work. The correlation detection background noise filtering circuit finds that the number of photons detected in a window is less than 4 set by the external signal SEL, and the VALID signal remains at a low level and is invalid. The 7th bit CNT6 of the 12 bits of the TDC output is selected as the corresponding scalar of the time window width through the 8-to-1 data selector programming. When CNT6 is at a high level, the RST signal is triggered to reset the pixel unit to complete the detection of a time window. In the second time window WIN_valid, the VALID signal is valid, and the drive signal RST remains at a low level until the periodic signal GBRST arrives to perform a global reset. In the STOP window, the EN signal is driven to a low level to stop the TDC operation, and the reverse quantized data is read out. The corresponding photon event flight time is obtained through calculation.

[0058] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of the technical features being referred to. Thus, a feature identified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined.

[0059] Although the present application is described herein with reference to various embodiments, those skilled in the art will be able to understand and implement other variations of the disclosed embodiments in practicing the claimed application by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality.

[0060] The above is a further detailed description of the present invention in conjunction with specific preferred embodiments, and the specific implementation of the present invention should not be considered to be limited to these descriptions. For those skilled in the art of the present invention, without departing from the concept of the present invention, several simple deductions or substitutions can be made, which should be considered to fall within the scope of protection of the present invention.

Claims

1. A noise suppression circuit for direct time-of-flight laser radar, characterized in that: include: A photon arrival signal generating circuit is used to receive a photon event signal generated after a single photon avalanche diode of a front-end circuit breaks down, and to generate a level according to the event signal to an enable signal generating circuit and a correlation detection background noise filtering circuit; The enable signal generating circuit is used to generate an enable signal after receiving the level to control the ring oscillator to start oscillation; The ring oscillator is configured to oscillate and generate a clock under the control of an enable signal, and output the clock to a coarse quantization circuit and a fine quantization circuit, respectively, so that the coarse quantization circuit and the fine quantization circuit respectively perform corresponding quantization on the clock to obtain respective quantized data results; The correlation detection background noise filtering circuit is used to accumulate the voltage of the level to filter the background light noise, and generate a VALID signal when a threshold is reached and output it to the reset signal generating circuit; The reset signal generating circuit is used to access part of the quantized data selected from the coarse quantization data of the coarse quantization circuit, thereby determining a time window, and generating a reset signal within the time window according to different situations of whether the VALID signal is input to control the reset of the photon arrival signal generating circuit, the enable signal generating circuit, the ring oscillator, the coarse quantization circuit and the fine quantization circuit, thereby controlling the width of the time window, or waiting for a global reset signal to reset all circuits in the time-to-digital converter used for the lidar chip.

2. The noise suppression circuit for direct time-of-flight laser radar according to claim 1, characterized in that: The generating of a reset signal to control the resetting of the photon arrival signal generating circuit, the enable signal generating circuit, the ring oscillator, the coarse quantization circuit, and the fine quantization circuit according to different situations of whether the VALID signal is inputted within the time window, thereby controlling the width of the time window, or waiting for a global reset signal to reset all circuits in the time-to-digital converter of the laser radar chip includes: If the VALID signal is not input within the time window, then when the current time window ends, a reset signal is generated to control the reset of the photon arrival signal generating circuit, the enable signal generating circuit, the ring oscillator, the coarse quantization circuit, and the fine quantization circuit, thereby controlling the width of the time window; If the VALID signal is input within the time window, a global reset signal is waited for to reset all circuits in the time-to-digital converter of the lidar chip.

3. The noise suppression circuit for direct time-of-flight laser radar according to claim 1, characterized in that: The photon arrival signal generating circuit is composed of a D flip-flop DFF4, and the enable signal generating circuit is composed of NAND gates NAND1 and NAND2, an OR gate OR1, a D flip-flop DFF5 and an AND gate AND1; Among them, the data output end of the D flip-flop DFF4 is respectively connected to the input ends of the NAND gates NAND1 and NAND2, the output ends of the NAND gates NAND1 and NAND2 are both connected to the input end of the OR gate OR1, the output end of the OR gate OR1 is connected to the data input end of the D flip-flop DFF5 and the first input end of the AND gate AND1, the output end of the D flip-flop DFF5 is connected to the second input end of the gate AND1, and the reset ends of the D flip-flops DFF4 and DFF5 are connected to the output end of the reset signal generating circuit.

4. The noise suppression circuit for direct time-of-flight laser radar according to claim 1, characterized in that: The correlation detection background noise filtering circuit is composed of capacitors C, Cm, inverters INV1, INVa, INVb, INVc, INVd, D trigger DFF6, switch and a data selector MUX2_1; The input end of the data selector MUX2_1 is connected to the input end of the photon arrival signal generator, the output end of the data selector MUX2_1 is connected to the input end of the inverter INVa, the output end of the inverter INVa is connected to the first end of the capacitor C, and the second end of the capacitor C is connected to the switch The first end and the input end of the inverter INV1, the switch The second end of and the output end of the inverter INV1 are connected to the input end of the inverter INVd, the output end of the inverter INVd is connected to the clock end of the D flip-flop DFF6, the data end of the D flip-flop DFF6 is connected to the power supply VDD, and the reset end of the D flip-flop DFF6 is connected to the output end of the reset signal generating circuit; the inverters INVb, INVc and capacitor Cm are connected in sequence, the input end of the inverter INVb is connected to the output end of the enable signal generating circuit, and the end of the capacitor Cm not connected to the inverter INVc is connected to the input end of the inverter INV1; the output end of the D flip-flop DFF6 outputs the VALID signal.

5. The noise suppression circuit for direct time-of-flight laser radar according to claim 1, characterized in that: The reset signal generating circuit is composed of a data selector MUX8_1, an inverter INV2 and a NOR gate NOR1 and a NOR gate OR3; Among them, the input end of the data selector MUX8_1 is connected to the part of the quantized data selected from the quantized data of the coarse quantization circuit, the output end is connected to the inverter INV2, the output end of the inverter INV2 is connected to the first input end of the NOT gate NOR1, the second input end of the NOT gate NOR1 is connected to the VALID signal, the output end of the NOT gate NOR1 is connected to the first input end of the NOT gate OR3, the second input end of the NOT gate OR3 is connected to the global reset signal GBRST, and the output end of the NOT gate OR3 outputs the reset signal RST.

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