High-bandwidth photonic integrated circuits with standard-gain compensation

Abstract

Embodiments of the present disclosure relate to high-bandwidth photonic integrated circuits with etalon compensation. A photonic integrated circuit device can include one or more layers with different refractive indices, which can cause optical coupling issues and losses from layer variations. Material films can be applied to the photonic integrated circuit layers to avoid problems of increasing the optical bandwidth of the photonic integrated circuit device and reducing sensitivity to manufacturing and design processes.

Description

High-bandwidth photonic integrated circuits with standard etalon compensation Technical Field

[0001] This disclosure generally relates to optical and electrical devices, and more specifically to efficient and scalable optical structures with anti-reflective coatings. Background Technology

[0002] Typically, silicon photonic integrated circuits can achieve optical coupling to output light generated by the circuit, detect light received by the circuit, or otherwise process light within the circuit. The physical properties (e.g., refractive index) and physical dimensions of the materials used to construct photonic circuits can lead to inefficient designs or designs that are efficient but difficult to manufacture due to manufacturing variations and layout. Summary of the Invention

[0003] According to an example implementation of this disclosure, a photonic integrated circuit structure for transmitting light is disclosed. The photonic integrated circuit structure includes: a grating layer for propagating light, the grating layer being located between a first oxide layer and a second oxide layer of the photonic integrated circuit structure; a reflector on a first side of the photonic integrated circuit structure, the reflector being separated from the grating layer by the first oxide layer, the reflector being used to guide light from the grating layer to a second side of the photonic integrated circuit structure opposite to the first side; a silicon layer on the second side of the photonic integrated circuit structure, the second oxide layer being located between the silicon layer and the grating layer; and a material film between the silicon layer and the second oxide layer for compensating for one or more etalons in the photonic integrated circuit structure, the material film having a refractive index between the refractive index of the silicon layer and the refractive index of the second oxide layer.

[0004] According to an example implementation of this disclosure, a method for manufacturing a photonic integrated circuit structure formed by a first wafer and a second wafer is disclosed. The method includes: oxidizing the first wafer, the first wafer including a grating layer; depositing a material film between the first wafer and the second wafer, the material film having a refractive index between a first refractive index of an oxide material of the first wafer and a second refractive index of a material of the second wafer; bonding the first wafer to the second wafer to form a bonding structure; and separating the first wafer to form a silicon-on-insulator (SOI) wafer of the photonic integrated circuit structure, the material film compensating for one or more etalons caused by light reflected within the photonic integrated circuit structure. Attached Figure Description

[0005] The following description includes a discussion of the accompanying drawings, which are illustrated as examples of implementations of embodiments of the present disclosure. The drawings should be understood by way of example rather than limitation. As used herein, references to one or more “embodiments” should be understood to describe a particular feature, structure, or characteristic included in at least one implementation of the subject matter of the invention. Therefore, phrases such as “in one embodiment” or “in an alternate embodiment” appearing herein describe various embodiments and implementations of the subject matter of the invention and do not necessarily refer to the same embodiment. However, they are not necessarily mutually exclusive. For ease of identification of the discussion of any particular element or action, one or more most significant numerals in the reference numerals refer to the figures (“FIG.”) in which that element or action is first introduced.

[0006] Figure 1 is a diagram showing a side view of an optoelectronic device according to some example embodiments.

[0007] Figure 2 is a diagram illustrating an example photonic integrated circuit structure according to some example embodiments.

[0008] Figure 3 is a diagram illustrating an example photonic integrated circuit structure formed from a wafer according to some example embodiments.

[0009] Figure 4 is a representative diagram illustrating a process architecture according to some example embodiments for fabricating photonic structures with one or more coatings to increase optical bandwidth and reduce physical sensitivity.

[0010] Figure 5 shows a flowchart of a method for fabricating high optical bandwidth photonic structures according to some example embodiments.

[0011] Figure 6 illustrates a flowchart of a method for processing light using a high optical bandwidth PIC (photonic integrated circuit) with etalon compensation to reduce wavelength and manufacturing sensitivity, according to some example embodiments.

[0012] Figure 7 illustrates an example optical transceiver according to some example embodiments.

[0013] The following is a description of certain details and implementations, including a description of the accompanying drawings, which may depict some or all of the embodiments described below, as well as other possible embodiments or implementations of the inventive concepts presented herein. An overview of embodiments of this disclosure is provided below, followed by a more detailed description with reference to the accompanying drawings. Detailed Implementation

[0014] In the following description, several specific details are set forth for purposes of explanation in order to provide an understanding of various embodiments of the subject matter of the invention. However, it will be apparent to those skilled in the art that embodiments of the subject matter of the invention may be practiced without these specific details. Generally, well-known examples of instructions, structures, and techniques are not necessarily shown in detail.

[0015] As discussed, silicon photonics (SiPh) integrated circuits can achieve optical coupling to output light generated by the circuit, detect light received by the circuit, or otherwise process light within the circuit. In some example embodiments, the optical coupling interface is located at the edge of the silicon photonics integrated circuit chip or within the light propagation plane on the silicon photonics integrated circuit chip. In some example embodiments, the optical coupling is positioned approximately or precisely orthogonal to the light propagation plane in the silicon photonics integrated circuit chip. In these methods, light in the PIC can be redirected upwards or downwards using optical components in the PIC, such as mirrors and / or grating couplers. When implementing the optical redirection component, the overall efficiency of the optical coupling interface can depend on the material properties (e.g., thickness, refractive index, shape, etc.) between the optical redirection component present on the SiPh IC and the components (e.g., optical fibers, off-chip lasers, off-chip detectors, etc.) to which the SiPh IC is interfaced. The SiPh IC can be fabricated using a silicon-on-insulator (SOI) substrate, where the high exponential contrast between the buried oxide and the silicon substrate can affect the overall efficiency of the optical coupling interface. For example, specifically, light can be reflected by the silicon oxide / silicon interface, and this reflection can reduce coupling efficiency, increase manufacturing process sensitivity, and limit the bandwidth available in a given chip design (due to reduced coupling efficiency and manufacturing sensitivity). This reduced wavelength performance also limits the number of channels that can be added to the chip (e.g., coarse wavelength division multiplexing chips with multiple consecutive channels spaced 20 to 40 nm apart). While edge-coupled or deflecting components that guide light away from the SOI silicon substrate can mitigate these problems, deflecting light is not practical as a design constraint in many layouts (e.g., edge-coupler designs can deflect light, but edge-coupled designs have space constraints and / or may not be the preferred layout for a given optical structure, such as in flip-chip PICs).

[0016] In some example embodiments, multiple silicon wafers can be processed to form an SOI with one or more anti-reflective coatings to improve efficiency and reduce fabrication sensitivity of the structure. In an example process, the surface of one wafer (wafer A) is thermally oxidized to form a buried oxide. Further, a weakened interface can be created within the top silicon of wafer A via a process such as implantation. Wafer A is then flipped and bonded to another wafer (wafer B). The bonded structure separates at the weakened silicon interface, leaving an SOI wafer comprising a silicon substrate of wafer B, the buried thermal oxide from wafer A, and a thin device silicon layer from wafer A (e.g., for device interface connection such as organic substrate 160 or fiber optic 121). The SOI wafer is typically annealed, and the device silicon layer is polished.

[0017] In some example embodiments, an anti-reflective (AR) coating is added between the buried oxide layer and the silicon substrate of the SOI wafer. In some example embodiments, the AR coating is a thin film deposited on wafer B prior to bonding with wafer A. Alternatively, and according to some example embodiments, the thin film is deposited on wafer A after wafer A has been oxidized, and then bonded to wafer B. Further, in some example embodiments, the thickness of the deposited film is close to or exactly one-quarter wavelength of the light to be transmitted through the film (e.g., light received by the PIC from an external source, generated by the PIC using an internal light source, or processed by the PIC), such that the interference at the coating interface is completely out of phase (e.g., reflection interference from the top and bottom of the coating interface). Further, in order to produce good interference fringes through the interference caused by the AR coating (e.g., through perfect amplitude and wave subtraction at the AR coating interface), the deposited film is a material whose refractive index is close to the geometric mean of the materials on either side of the coating. For example, if the two interface materials are a buried oxide layer and a silicon layer, the AR coating may be a film of silicon nitride material (e.g., Si3N4) whose index is close to the geometric mean of the indices of the buried oxide and silicon materials. In this way, AR coatings can compensate for imperfect buried oxide thickness (e.g., intentional polishing, random manufacturing process variations) and also relax wavelength and manufacturing sensitivity, thereby achieving broadband wavelength performance (e.g., lower loss over a wider band), and thus enabling designs with additional channels.

[0018] Figure 1 shows a side view of an optoelectronic device 100 including one or more optical devices according to some example embodiments. In the illustrated embodiment, the optoelectronic device 100 is shown as including a printed circuit board (PCB) substrate 105, an organic substrate 160, an application-specific integrated circuit (ASIC) 115, and a photonic integrated circuit (PIC) 120.

[0019] In some example embodiments, the PIC 120 includes silicon-on-insulator (SOI) or silicon-based (e.g., silicon nitride (SiN)) devices, or may include devices formed from silicon and non-silicon materials. The non-silicon material (alternatively referred to as "heterogeneous material") may include one of III-V materials, magneto-optical materials, or crystalline substrate materials. III-V semiconductors have elements found in groups III and V of the periodic table (e.g., indium gallium arsenide phosphide (InGaAsP) and indium gallium arsenide nitride (GainAsN)). The carrier dispersion effect of III-V-based materials can be significantly higher than that of silicon-based materials because electrons in III-V semiconductors are much faster than in silicon. Additionally, III-V materials have a direct band gap, which enables efficient creation of light by electrical pumping. Therefore, III-V semiconductor materials allow photonic operations to generate light with higher efficiency than silicon and modulate the refractive index of light. Thus, III-V semiconductor materials allow photonic operations to generate light from electricity and convert light back to electricity with higher efficiency.

[0020] Therefore, the low optical loss and high quality of silicon oxide are combined with the electro-optical efficiency of III-V semiconductors in the heterogeneous optical devices described below; in embodiments of this disclosure, the heterogeneous devices utilize a low-loss heterogeneous optical waveguide transition between the device's heterogeneous waveguide and a silicon-only waveguide.

[0021] Magneto-optical (MO) materials allow heterogeneous PICs to operate based on the MO effect. Such devices can utilize the Faraday effect, where a magnetic field associated with an electrical signal modulates a beam of light, thereby providing high-bandwidth modulation and rotating the electric field of an optical mode to enable optical isolators. The MO material can include, for example, materials such as iron, cobalt, or yttrium iron garnet (YIG). Further, in some example embodiments, a crystalline substrate material provides a heterogeneous PIC with high electromechanical coupling, a linear electro-optic coefficient, low transmission loss, and stable physical and chemical properties. The crystalline substrate material can include, for example, lithium niobate (LiNbO3) or lithium tantalate (LiTaO3).

[0022] In the illustrated example, in a flip-chip configuration where the top side of PIC 120 is connected to an organic substrate and light propagates out (or in) from the bottom side of PIC 120 (e.g., towards a coupler), PIC 120 exchanges light with an external light source 125 via optical fiber 121. According to some example embodiments, optical fiber 121 may be coupled to PIC 120 using prisms, gratings, or lenses. Optical components of PIC 120 (e.g., optical modulators, optical switches) are at least partially controlled by a control circuitry system included in ASIC 115. Both ASIC 115 and PIC 120 are shown disposed on copper pillars 114, which are used to communicatively couple the PIC via organic substrate 160. PCB substrate 105 is coupled to organic substrate 160 via ball grid array (BGA) interconnect 116 and may be used to interconnect organic substrate 160 (and thus ASIC 115 and PIC 120) to other components of optoelectronic device 100 (e.g., interconnect modules, power supplies, etc.), not shown.

[0023] Figure 2 illustrates an example photonic integrated circuit structure 200 (e.g., photonic integrated circuit 120) according to some exemplary embodiments. The etalon is an optical cavity formed by two reflective interfaces (e.g., a Fabry-Perot interferometer), which can depend on the cavity size and the reflectivity of the materials. In Figure 2, light is illustrated as ray arrows (dashed arrows, solid arrows). In the illustrated example, a grating layer 215 is located between a first oxide layer 210 (e.g., a support-side buried oxide layer) and a second oxide layer 220 (e.g., a mirror-side buried oxide layer), and light can propagate through a silicon layer 205 (e.g., the bottom side of the PIC 120 facing an external coupler). Light can be generated, received, or otherwise processed vertically (e.g., relative to the orientation of Figure 2) by the photonic integrated circuit structure 200 in a flip-chip configuration. For example, light can be generated by an integrated light source (e.g., not depicted in Figure 2), propagated toward and emitted from a mirror 225 through a grating layer 215, which reflects the light so that it propagates through a second oxide layer 220, a grating layer 215, a first oxide layer 210, and exits from a silicon layer 205 (e.g., to an external device, such as a fiber optic coupler).

[0024] In the example illustrated in Figure 2, unexpected etalons may appear in structure 200 due to reflections between different surfaces. For example, etalons may arise from reflections from the interface formed by silicon layer 205 and first oxide layer 210, as well as from reflections from mirror 225. As an additional example, etalons may arise from reflections from the interface formed by silicon layer 205 and first oxide layer 210, as well as from another interface formed by first oxide layer 210 and grating layer 215. As yet another example, etalons may arise from reflections from the interface formed by grating layer 215 and second oxide layer 220 and mirror 225. In some example embodiments, the etalons are unintended and may be due to manufacturing variations. For example, first oxide layer 210 may also be etched and then polished (according to a given PIC layout design), and variations in polishing can create variations in the thickness of first oxide layer 210, resulting in one or more of the aforementioned etalons.

[0025] Figure 3 illustrates an example photonic integrated circuit structure 300 (e.g., photonic integrated circuit 120) formed from wafers (e.g., wafer A, wafer B) according to some example embodiments. In Figure 3, light is illustrated as ray arrows (dashed arrows, solid arrows). In some example embodiments, silicon layer 305 and AR coating 313 are formed using wafer B, and first oxide layer 310, grating layer 315, second oxide layer 320, and mirror layer 325 are formed on or using wafer A (e.g., implantation separation to create second oxide layer 320). Light can be generated, received, or otherwise processed by the photonic integrated circuit structure 300 vertically (e.g., relative to the orientation of Figure 3). For example, light can be generated by an integrated light source (e.g., not depicted in FIG. 3) and guided from a grating through the first oxide layer 310, or guided downwards to be reflected on the mirror layer 325 and upwards through the mirror layer 325, grating layer 315, first oxide layer 310, AR coating 313, and silicon layer 305 (e.g., to an external device, such as a fiber optic coupler). In the example illustrated in FIG. 3, the photonic integrated circuit structure 300 includes an AR coating 313, which can be applied to one wafer of the wafer prior to bonding to reduce the fabrication sensitivity of the photonic integrated circuit structure 300 by avoiding one or more etalons in the photonic integrated circuit structure 300 (e.g., by removing the full-length round trip of creating the etalons). Specifically, for example, if the first oxide layer 310 is over-polished during fabrication, the AR coating 313 will prevent one or more etalons from appearing in the photonic integrated circuit structure 300. Additionally, due to the avoidance of sensitivity to potential etalons appearing within the photonic integrated circuit structure 300, the wavelength span of the light to be propagated can be increased (e.g., for additional channels).

[0026] In some example embodiments, grating layer 315 includes a broadband steering mechanism (e.g., a total internal reflection (TIR) ​​grating, a steering mirror) that directs light in grating layer 315 at a 90-degree angle to the interface between silicon layer 305 and first oxide layer 310. In these example embodiments, the addition of AR coating 313 between silicon layer 305 and first oxide layer 310 removes the etalon effect, so the total bandwidth of the device is set by the removal of one or more etalons by AR coating 313 (e.g., because the steering mirror in this embodiment is very broadband and has a wide bandwidth limited by the possible etalons at the interface between silicon layer 305 and first oxide layer 310).

[0027] Figure 4 illustrates a process architecture 400 for fabricating SOIs with AR coatings to reduce wavelength and manufacturing sensitivity, according to some example embodiments. In some example embodiments, wafer A 402 is oxidized to produce oxide wafer A 405. Oxidized wafer A 405 then undergoes interface weakening, for example, using ion implantation to create a weak interface 406 for later separation.

[0028] In the illustrated embodiment of Figure 4, a thin film of material 413 is applied to wafer B 450 for use as the AR coating discussed above. For example, a thin film of silicon nitride (Si3N4) (e.g., 164 nm) can be applied via thin film deposition (e.g., chemical vapor deposition, growth deposition, physical vapor deposition) to create AR coating 313 (Figure 3). The thin film is selected as a material having a certain index (e.g., the geometric mean of the two materials on either side of the coating, the average of the indices of silicon and silicon oxide, etc.). Further, the thin film is deposited at a certain thickness (e.g., a quarter wavelength of light propagating through the coating), for example to ensure that the two reflections of the potential etalon remain completely out of phase, and also to ensure that the waves have equal amplitudes (e.g., to produce good interference fringes through interference), and the material thin film is selected to ensure that it has a refractive index between the two matching refractive indices (silicon and BOX), such that the amplitude matches between the two reflected waves, and the reflection is completely subtracted without the appearance of an etalon. According to some example embodiments, the exponent of the film is chosen as the geometric mean (e.g., or close to the mean) of the two matching refractive indices (silicon and BOX), such that the amplitude matches between the two reflected waves, and the reflection is completely subtracted without the appearance of an etalon. Additionally, in some example embodiments, the film is applied to wafer A instead of wafer B. For example, wafer A may be oxidized, and the film may be applied to the surface of wafer A bonded to wafer B.

[0029] Continuing, wafer A is then flipped and bonded to wafer B to create bonding structure 427. Wafer A is then separated at weak interface 406 to create a new wafer A, which can be used as a donor wafer for additional SOI creation. Further, separation at the thin interface creates silicon (e.g., photonic integrated circuit structure 300, FIG. 3) on insulator structure 444.

[0030] Figure 5 illustrates a flowchart of method 500 according to some example embodiments for fabricating a high optical bandwidth PIC with a standard preemptive AR coating to reduce wavelength and manufacturing sensitivity. In operation 505, one or more wafers are oxidized. For example, wafer A or wafer B (e.g., a silicon wafer) is oxidized to create a buried oxide layer on the wafer.

[0031] In operation 510, the thin film is applied as an AR coating using a film deposition process (e.g., chemical vapor deposition). In some example embodiments, the index of the film material has the geometric mean of the two materials that create the reflective interface of the etalon. For example, the etalon interface may be created by a silicon material (e.g., silicon layer 305) and a silicon oxide material (e.g., first oxide layer 310), and a silicon nitride layer is applied as a thin film to one wafer of the wafer. In some example embodiments, the deposited film has approximately a quarter wavelength of light to be propagated through the PIC.

[0032] In operation 515, the wafers are bonded. For example, wafer A is flipped and bonded to wafer B. In operation 520, the wafer structure is separated. For example, a weak interface may be created in wafer A (e.g., via implantation), and wafer A is split to create a new wafer and the resulting SOI structure, such as photonic integrated circuit structure 300, Figure 3.

[0033] Figure 6 illustrates a flowchart of method 600 according to some example embodiments for processing light using a high optical bandwidth PIC with etalon compensation to reduce wavelength and manufacturing sensitivity. In operation 605, the photonic integrated circuit structure 300 propagates light. For example, light propagates outward from grating layer 315 to mirror layer 325, and also from grating layer 315 to silicon layer 305 (e.g., the bottom side of a flip chip). In operation 610, light is reflected. For example, light is reflected from mirror layer 325 in the direction of silicon layer 305. In operation 615, light is received at an interface 313, such as the interface between silicon layer 305 and first oxide layer 310. In operation 620, as discussed above, light is transmitted through the interface without the inefficiency based on etalon due to AR coating 313.

[0034] Figure 7 illustrates an example multichannel wavelength division multiplexing (WDM) optical transceiver 700 according to some example embodiments. In the illustrated embodiment, the optical transceiver 700 includes an integrated photonic transmitter structure 705 and an integrated photonic receiver structure 710. In some example embodiments, the integrated photonic transmitter structure 705 and the integrated photonic receiver structure 710 are example optical components fabricated as PIC devices, such as the PIC 120 of Figure 1 discussed above. The integrated photonic transmitter structure 705 is an example of a WDM transmitter with four channels, transmitter channels 1 to 4, where each channel handles light of a different wavelength. The integrated photonic receiver structure 710 is an example of a WDM receiver that receives WDM light (e.g., from an optical network or from the integrated photonic transmitter structure 705 in loopback mode). The integrated photonic receiver structure 710 can receive and process light by filtering, amplifying, and converting it into an electrical signal using components such as multiplexers, semiconductor optical amplifiers (SOAs), and one or more detectors such as photodetectors (e.g., photodiodes).

[0035] Optical transceiver 700 is an example structure that can be formed from two wafers (e.g., wafer A and wafer B, FIG. 4) having the AR coating films discussed above. Because the AR coating removes fabrication sensitivities (e.g., unexpected etalons due to over-polishing of buried oxide), different wavelengths and additional channels can be added to optical transceiver 700. For example, an AR coating can be added to the wafer used to form the optical transceiver, and the AR coating has a geometric mean close to that of silicon and buried oxide to remove etalons from each channel in the integrated photonic transmitter structure 705. For example, additional transmitter channels with smaller wavelengths can be added due to the increased bandwidth of the optical transceiver to achieve a larger overall bandwidth.

[0036] In some example embodiments, different films of varying thicknesses can be implemented to compensate for the different operating characteristics of the different channels. For example, the region above transmitter channels 1 and 2 may receive an AR coating with a thickness close to a quarter wavelength of light in transmitter channels 1 and 2 (e.g., a quarter wavelength of the average wavelength of light propagating in channels 1 and 2). Further, the region above transmitter channels 3 and 4 (or additional channels 5 and 6, additional channels 7 and 8, etc.) may receive a slightly thinner AR coating to correspond to the smaller wavelengths of light propagating in these channels (e.g., for an 8-channel WDM).

[0037] In view of the above disclosure, various examples are set forth below. It should be noted that one or more features of the examples adopted in isolation or combination should be considered within the scope of the disclosure of this application.

[0038] Example 1. A photonic integrated circuit structure for transmitting light, comprising: a grating layer for propagating light, the grating layer being located between a first oxide layer and a second oxide layer of the photonic integrated circuit structure; a mirror on a first side of the photonic integrated circuit structure, the mirror being separated from the grating layer by the first oxide layer, the mirror being used to guide light from the grating layer to a second side of the photonic integrated circuit structure opposite to the first side; a silicon layer on the second side of the photonic integrated circuit structure, the second oxide layer being located between the silicon layer and the grating layer; and a material film between the silicon layer and the second oxide layer for compensating for one or more etalons in the photonic integrated circuit structure, the material film having a refractive index between the refractive index of the silicon layer and the refractive index of the second oxide layer.

[0039] Example 2. Based on the photonic integrated circuit structure of Example 1, the refractive index of the material film is the geometric mean of the refractive index of the silicon layer and the refractive index of the second oxide layer.

[0040] Example 3. A photonic integrated circuit structure according to either Example 1 or 2, wherein the thickness of the material film is one-quarter of the wavelength of light in the photonic integrated circuit structure.

[0041] Example 4. A photonic integrated circuit structure according to any one of Examples 1 to 3, wherein a material film prevents the presence of a etalon between: a first interface comprising a silicon layer and a second oxide layer; and a second interface comprising a grating layer and a second oxide layer.

[0042] Example 5. A photonic integrated circuit structure according to any one of Examples 1 to 4, wherein a material film prevents the presence of a etalon between: a reflective interface comprising a silicon layer and a second oxide layer; and a reflector.

[0043] Example 6. A photonic integrated circuit structure according to any one of Examples 1 to 5, wherein the photonic integrated circuit structure is formed from a first silicon wafer and a second silicon wafer.

[0044] Example 7. A photonic integrated circuit structure according to any one of Examples 1 to 6, wherein the oxide materials of the first oxide layer and the second oxide layer are created from the oxidation of a first silicon wafer.

[0045] Example 8. A photonic integrated circuit structure according to any one of Examples 1 to 7, wherein a material film is deposited on the first silicon wafer after oxidation.

[0046] Example 9. A photonic integrated circuit structure according to any one of Examples 1 to 8, wherein a material film is deposited on a second silicon wafer.

[0047] Example 10. A photonic integrated circuit structure according to any one of Examples 1 to 9, wherein the photonic integrated circuit structure is formed by bonding a first silicon wafer to a second silicon wafer.

[0048] Example 11. A photonic integrated circuit structure according to any one of Examples 1 to 10, wherein a first silicon wafer is separated to form a first oxide layer.

[0049] Example 12. A photonic integrated circuit structure according to any one of Examples 1 to 11, wherein the first silicon wafer is separated by ion implantation.

[0050] Example 13. A photonic integrated circuit structure according to any one of Examples 1 to 12, wherein the first oxide layer and the second oxide layer are silicon oxide layers.

[0051] Example 14. A photonic integrated circuit structure according to any one of Examples 1 to 13, wherein the photonic integrated circuit structure includes a plurality of channels, wherein each channel propagates light of one wavelength from a plurality of different wavelengths, and wherein a material film is applied to different regions of the photonic integrated circuit structure corresponding to different channels among the plurality of channels.

[0052] Example 15. A method of manufacturing a photonic integrated circuit structure formed from a first wafer and a second wafer, the method comprising: oxidizing the first wafer, the first wafer including a grating layer; depositing a material film between the first wafer and the second wafer, the material film having a refractive index between a first refractive index of an oxide material of the first wafer and a second refractive index of a material of the second wafer; bonding the first wafer to the second wafer to form a bonded structure; and separating the first wafer to form a silicon-on-insulator (SOI) wafer of the photonic integrated circuit structure, the material film compensating for one or more etalons caused by light reflected within the photonic integrated circuit structure.

[0053] Example 16. The manufacturing method according to Example 15, wherein a material film is applied to the first wafer after the oxidation of the first wafer.

[0054] Example 17. A manufacturing method according to any one of Examples 15 or 16, wherein a material film is applied to a second wafer.

[0055] Example 18. A manufacturing method according to any one of Examples 15 to 17, further comprising: processing a first wafer to induce a change in the thickness of an oxide layer, wherein a material film compensates for the change in the thickness of the oxide layer by inducing phase interference, such that one or more etalons are avoided in a photonic integrated circuit structure.

[0056] Example 19. A manufacturing method according to any one of Examples 15 to 18, wherein a photonic integrated circuit structure is configured to propagate light of a certain wavelength, and a material film is deposited such that the thickness of the material film is one-quarter of the wavelength.

[0057] Example 20. A manufacturing method according to any one of Examples 15 to 19, wherein the photonic integrated circuit structure is a wavelength division multiplexer having multiple channels, and a material film is applied to regions corresponding to different channels, each of the multiple channels being configured to propagate light of a different wavelength.

[0058] In the foregoing detailed description, the methods and apparatus of the present invention have been described with reference to specific exemplary embodiments thereof. However, it will be apparent that various modifications and alterations can be made to the invention without departing from the broader spirit and scope of the subject matter. Therefore, this specification and the accompanying drawings are to be considered illustrative rather than restrictive.

Claims

1. A photonic integrated circuit structure for transmitting light, the photonic integrated circuit structure comprising: A light-propagating grating layer, the grating layer being located between the first oxide layer and the second oxide layer of the photonic integrated circuit structure; A mirror on a first side of the photonic integrated circuit structure, the mirror being separated from the grating layer by a first oxide layer, the mirror being used to guide light from the grating layer to a second side of the photonic integrated circuit structure opposite to the first side; a silicon layer on the second side of the photonic integrated circuit structure, the second oxide layer being between the silicon layer and the grating layer; and a material film between the silicon layer and the second oxide layer, used to prevent one or more etalons from appearing in the photonic integrated circuit structure, the material film having a refractive index between the refractive index of the silicon layer and the refractive index of the second oxide layer; wherein the first side and the second side are planes perpendicular to the stacking direction of the photonic integrated circuit structure; wherein the photonic integrated circuit structure is formed by a first silicon wafer and a second silicon wafer, wherein the first silicon wafer corresponds to the first oxide layer, the grating layer, the second oxide layer and the mirror, and the second silicon wafer corresponds to the silicon layer and the material film.

2. The photonic integrated circuit structure according to claim 1, wherein the refractive index of the material film is the geometric mean of the refractive index of the silicon layer and the refractive index of the second oxide layer.

3. The photonic integrated circuit structure according to claim 1, wherein the thickness of the material film is one-quarter of the wavelength of the light in the photonic integrated circuit structure.

4. The photonic integrated circuit structure according to claim 1, wherein the material film prevents the etalon from appearing between: a first interface comprising the silicon layer and the second oxide layer, and a second interface comprising the grating layer and the second oxide layer.

5. The photonic integrated circuit structure of claim 1, wherein the material film prevents the etalon from appearing between: a reflective interface comprising the silicon layer and the second oxide layer, and the reflector.

6. The photonic integrated circuit structure according to claim 1, wherein the oxide materials of the first oxide layer and the second oxide layer are created from the oxidation of the first silicon wafer.

7. The photonic integrated circuit structure according to claim 6, wherein the material film is deposited on the first silicon wafer after the oxidation of the first silicon wafer.

8. The photonic integrated circuit structure according to claim 6, wherein the material film is deposited on the second silicon wafer.

9. The photonic integrated circuit structure of claim 6, wherein the photonic integrated circuit structure is formed by bonding the first silicon wafer to the second silicon wafer.

10. The photonic integrated circuit structure of claim 9, wherein the first silicon wafer is separated to form the first oxide layer.

11. The photonic integrated circuit structure of claim 10, wherein the first silicon wafer is separated using ion implantation.

12. The photonic integrated circuit structure according to claim 1, wherein the first oxide layer and the second oxide layer are silicon oxide layers.

13. The photonic integrated circuit structure of claim 1, wherein the photonic integrated circuit structure comprises a plurality of channels, wherein each channel propagates light of one wavelength from a plurality of different wavelengths, and wherein the material film is applied to different regions of the photonic integrated circuit structure corresponding to different channels among the plurality of channels.

14. A method for manufacturing a photonic integrated circuit structure formed from a first wafer and a second wafer, the method comprising: The process involves oxidizing the first wafer, which includes a grating layer; depositing a material film between the first wafer and the second wafer, the material film having a refractive index between a first refractive index of the oxide material of the first wafer and a second refractive index of the material of the second wafer; bonding the first wafer to the second wafer to form a bonding structure; and separating the first wafer to form a silicon-on-insulator (SOI) wafer of the photonic integrated circuit structure, the material film preventing the appearance of one or more etalons caused by light reflected within the photonic integrated circuit structure.

15. The manufacturing method of claim 14, wherein the material film is applied to the first wafer after the oxidation of the first wafer.

16. The manufacturing method of claim 14, wherein the material film is applied to the second wafer.

17. The manufacturing method according to claim 14, further comprising: The first wafer is processed to induce a change in the thickness of the oxide layer, wherein the material film compensates for the change in the thickness of the oxide layer by inducing phase interference, such that the one or more etalons are prevented from appearing in the photonic integrated circuit structure.

18. The manufacturing method of claim 14, wherein the photonic integrated circuit structure is configured to propagate light of a certain wavelength, and the material film is deposited such that the thickness of the material film is one-quarter of the wavelength.

19. The manufacturing method of claim 14, wherein the photonic integrated circuit structure is a wavelength division multiplexer having multiple channels, and the material film is applied to regions corresponding to different channels, each of the multiple channels being configured to propagate light of a different wavelength.

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