Interface multiplexing circuit and integrated circuit

Abstract

The application provides an interface multiplexing circuit and an integrated circuit. The interface multiplexing circuit is applied to an integrated circuit, and comprises a general signal input circuit, a communication signal input circuit and a selection switch. The general signal input circuit is used for receiving an input high-voltage digital signal, performing signal processing on the high-voltage digital signal, and converting the high-voltage digital signal into a first low-voltage digital signal. The communication signal input circuit is used for receiving a communication digital signal, performing signal processing on the communication digital signal, and converting the communication digital signal into a second low-voltage digital signal. The selection switch is used for selecting to connect the general signal input circuit or the communication signal input circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of interface circuit of integrated circuit, in particular to an interface multiplexing circuit and integrated circuit. BACKGROUND

[0002] General-purpose input / output (GPIO) is a key circuit of system on chip (SOC), as SOC tends to be low cost but needs to be suitable for rich application scenarios, low cost means that the number of GPIOs needs to be as few as possible to reduce the overall area of SOC, and rich application scenarios need as many GPIOs as possible to meet the needs of various communication interfaces, which limits the application of SOC in low cost and general field.

[0003] A common GPIO circuit schematic diagram is shown in Figure 1 . Referring to Figure 1 , VDD_core is an internal digital low-voltage power supply, I1 is an output buffer, L2H is a low-to-high voltage level shifting circuit, I2 is an output buffer, I3 is an input buffer, and I4 is a high-to-low voltage level shifting circuit.

[0004] When the GPIO is enabled as an input, IE is high, OE is low, and the use of PU and PD depends on the application scenario. When the PAD signal is high at 5V, I3 and I4 convert it to a digital low-voltage signal; IC2 is another chip on the I2C bus, VDD2 is the power supply of the chip, and Rp is the bus pull-up resistor; as VDD2 may be lower than VDD_driver during data transmission, if the GPIO input channel is still used at this time and there is no glitch filtering function, it will cause communication errors and cause I3 to have a large leakage.

[0005] The current solution to the above problem is to convert the I2C signal into a level equal to the SOC power supply through an external level shifting circuit when the GPIO needs to meet the I2C bus communication application, which increases the cost of the board level. Moreover, as the I2C signal noise is large, a filtering unit needs to be added when doing I2C communication, which limits the communication speed of the general-purpose interface. Therefore, the existing method of implementing GPIO and I2C interface multiplexing has the following disadvantages: unable to simultaneously achieve low cost and high-speed communication. SUMMARY

[0006] The embodiment of the present application provides an interface multiplexing circuit, which is applied to an integrated circuit, and comprises a general signal input circuit, a communication signal input circuit and a selection switch. The general signal input circuit is used for receiving an input high-voltage digital signal, performing signal processing on the high-voltage digital signal, and converting the high-voltage digital signal into a first low-voltage digital signal. The communication signal input circuit is used for receiving a communication digital signal, performing signal processing on the communication digital signal, and converting the communication digital signal into a second low-voltage digital signal. The selection switch is used for selecting to connect the general signal input circuit or the communication signal input circuit.

[0007] According to some embodiments, the general signal input circuit comprises a first input buffer and a first output buffer. The first input buffer is used for receiving an input high-voltage digital signal and performing shaping on the high-voltage digital signal. The first output buffer is used for converting the shaped high-voltage digital signal into a first low-voltage digital signal.

[0008] According to some embodiments, a power supply voltage of the first input buffer is a power supply voltage of the integrated circuit.

[0009] According to some embodiments, the communication signal input circuit comprises a second input buffer, a filter and a second output buffer. The second input buffer is used for receiving a communication digital signal of an external chip, performing signal processing on the communication digital signal, and converting the communication digital signal into a second low-voltage digital signal. The filter is used for filtering the second low-voltage digital signal. The second output buffer is used for performing shaping on the filtered second low-voltage digital signal.

[0010] According to some embodiments, a power supply voltage of the second input buffer is an internal digital low-voltage power supply of the integrated circuit.

[0011] According to some embodiments, when the selection switch selects to connect the general signal input circuit, a control end of the first input buffer is at a high level and a control end of the second input buffer is at a low level. When the selection switch selects to connect the communication signal input circuit, the control end of the first input buffer is at the low level and the control end of the second input buffer is at the high level.

[0012] According to some embodiments, the interface multiplexing circuit further comprises a signal output circuit, which is used for outputting the first low-voltage digital signal or the second low-voltage digital signal.

[0013] According to some embodiments, the signal output circuit includes a third input buffer, a level shifting circuit, and a third output buffer. The third input buffer shapes the output first low-voltage digital signal or the second low-voltage digital signal. The level shifting circuit is connected to the output terminal of the third input buffer and converts the shaped first low-voltage digital signal or the second low-voltage digital signal into a high-voltage digital signal. The third output buffer is connected to the output terminal of the level shifting circuit and amplifies the high-voltage digital signal to output the high-voltage digital signal.

[0014] According to some embodiments, when the signal output circuit outputs the first low-voltage digital signal or the second low-voltage digital signal, the control terminal of the third output buffer is at a high level.

[0015] According to some embodiments, the power supply for the general signal input circuit and the communication signal input circuit is DC5V.

[0016] This application also provides an integrated circuit, including the interface multiplexing circuit described above.

[0017] The technical solution provided in this application adopts a time-division multiplexing method for GPIO and I2C interfaces. When performing GPIO communication, the GPIO input channel is selected, and when performing I2C communication, the input channel with glitch filtering function is selected. This can realize an interface circuit that is both low-cost and high-speed, and enriches the application scenarios of GPIO without increasing the number of IOs. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a common GPIO circuit.

[0020] Figure 2 This is a schematic diagram of an interface multiplexing circuit provided in an embodiment of this application.

[0021] Figure 3 This is a schematic diagram of another interface multiplexing circuit provided in an embodiment of this application. Detailed Implementation

[0022] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this application. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0023] It should be understood that the terms "first," "second," etc., in the claims, specification, and drawings of this application are used to distinguish different objects, rather than to describe a specific order. The terms "comprising" and "including" used in the specification and claims of this application indicate the presence of the described features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof.

[0024] Figure 2 This is a schematic diagram of an interface multiplexing circuit provided in an embodiment of this application. The interface multiplexing circuit is applied to an integrated circuit and selects different input channels by means of a selection switch when there are general signal inputs and communication signal inputs.

[0025] like Figure 2 As shown, the interface multiplexing circuit 100 includes a general-purpose signal input circuit 10, a communication signal input circuit 20, and a selection switch K1. The general-purpose signal input circuit and the communication signal input circuit operate on a DC 5V power supply.

[0026] VDD_core is the internal digital low-voltage power supply, DC 1.8V-5V, and VDD_driver is the power supply for the I / O interface, DC 5V. OE is the output enable control signal, and IE is the input enable control signal. PU and PD are the pull-up and pull-down resistor enable control signals, respectively; the use of PU and PD depends on the application scenario.

[0027] The general-purpose signal input circuit 10 is used to receive the input high-voltage digital signal, process the high-voltage digital signal, and convert it into a first low-voltage digital signal. The high-voltage digital signal is a DC 1.8V-5V digital signal, and the first low-voltage digital signal is a digital signal lower than DC 1.8V.

[0028] The general-purpose signal input circuit 10 includes a first input buffer I3 and a first output buffer I4. The power supply voltage of the first input buffer I3 is the power supply voltage VDD_driver of the integrated circuit. The first input buffer I3 is used to receive the input high-voltage digital signal and shape it. The first output buffer I4 converts the shaped high-voltage digital signal into a first low-voltage digital signal.

[0029] The communication signal input circuit 20 receives communication digital signals from the IC2 chip, which is another chip on the I2C bus. VDD2 is the power supply for IC2, and Rp is the bus pull-up resistor. The communication signal input circuit 20 processes the communication digital signals and converts them into second low-voltage digital signals. These second low-voltage digital signals are all below 1.8V.

[0030] The communication signal input circuit 20 includes a second input buffer I5, a filter I7, and a second output buffer I6.

[0031] The second input buffer I5 receives the communication digital signal, processes it, and converts it into a second low-voltage digital signal. The power supply voltage of the second input buffer I5 is the power supply voltage VDD_core of the external chip IC2. Filter I7 filters the second low-voltage digital signal, removing high-frequency glitches from the low-speed I2C signal. The second output buffer I6 shapes the filtered second low-voltage digital signal. Because the communication signal input circuit 20 includes a filter stage, high-frequency glitches are removed. The first input buffer I3 is in the off state. As long as the internal low-voltage digital power supply of VDD_core is designed not to exceed the voltage of VDD2, communication errors will not occur, and leakage in the second input buffer I5 will not be caused.

[0032] Selector switch K1 is used to select whether to connect the general signal input circuit or the communication signal input circuit.

[0033] When selector switch K1 is used to connect the general signal input circuit, the control terminal IE of the first input buffer I3 is high, and the control terminal IE_I2C of the second input buffer I5 is low. When selector switch K1 is used to connect the communication signal input circuit, the control terminal IE of the first input buffer I3 is low, and the control terminal IE_I2C of the second input buffer I5 is high.

[0034] Figure 3 This is a schematic diagram of another interface multiplexing circuit provided in an embodiment of this application. The interface multiplexing circuit is applied to an integrated circuit and selects different input channels by means of a selection switch when there are general signal inputs and communication signal inputs.

[0035] The interface multiplexing circuit 200 includes a general-purpose signal input circuit 10, a communication signal input circuit 20, a signal output circuit 30, and a selection switch K1. The general-purpose signal input circuit and the communication signal input circuit operate on a DC 5V power supply.

[0036] VDD_core is the internal digital low-voltage power supply, DC 1.8V-5V, and VDD_driver is the power supply for the I / O interface, DC 5V. OE is the output enable control signal, and IE is the input enable control signal. PU and PD are the pull-up and pull-down resistor enable control signals, respectively; the use of PU and PD depends on the application scenario.

[0037] The general-purpose signal input circuit 10 is used to receive the input high-voltage digital signal, process the high-voltage digital signal, and convert it into a first low-voltage digital signal. The high-voltage digital signal is a DC 1.8V-5V digital signal, and the first low-voltage digital signal is a digital signal lower than DC 1.8V.

[0038] The general-purpose signal input circuit 10 includes a first input buffer I3 and a first output buffer I4. The first input buffer I3 is used to receive the input high-voltage digital signal and shape it. The first output buffer I4 converts the shaped high-voltage digital signal into a first low-voltage digital signal.

[0039] The communication signal input circuit 20 receives communication digital signals from the IC2 chip, which is another chip on the I2C bus. VDD2 is the power supply for IC2, and Rp is the bus pull-up resistor. The communication signal input circuit 20 processes the communication digital signals and converts them into second low-voltage digital signals. These second low-voltage digital signals are all below 1.8V.

[0040] The communication signal input circuit 20 includes a second input buffer I5, a filter I7, and a second output buffer I6.

[0041] The second input buffer I5 receives the communication digital signal, processes it, and converts it into a second low-voltage digital signal. Filter I7 filters the second low-voltage digital signal, removing high-frequency glitches from the low-speed I2C signal. The second output buffer I6 shapes the filtered second low-voltage digital signal. Because the communication signal input circuit 20 includes a filter stage, removing high-frequency glitches, the first input buffer I3 is in the off state. Since the power supply voltage of the second input buffer I5 is the integrated circuit's internal digital low-voltage power supply VDD_core, as long as the internal digital low-voltage power supply VDD_core is designed not to exceed VDD2 voltage, communication errors will not occur, and leakage in the second input buffer I5 will not be caused.

[0042] Selector switch K1 is used to select whether to connect the general signal input circuit or the communication signal input circuit.

[0043] When selector switch K1 is used to connect the general signal input circuit, the control terminal IE of the first input buffer I3 is high, and the control terminal IE_I2C of the second input buffer I5 is low. When selector switch K1 is used to connect the communication signal input circuit, the control terminal IE of the first input buffer I3 is low, and the control terminal IE_I2C of the second input buffer I5 is high.

[0044] The signal output circuit 30 outputs a first low-voltage digital signal or a second low-voltage digital signal. The signal output circuit 30 includes a third input buffer I1, a level shifting circuit L2H, and a third output buffer I2.

[0045] The third input buffer I1 shapes either the first or second low-voltage digital signal. The level shifting circuit L2H is connected to the output of the third input buffer I1, converting the shaped first or second low-voltage digital signal into a high-voltage digital signal. The third output buffer I2 is connected to the output of the level shifting circuit L2H, amplifying the high-voltage digital signal and outputting it as a high-voltage digital signal. When the signal output circuit outputs either the first or second low-voltage digital signal, the control terminal OE of the third output buffer I2 is high.

[0046] This application also provides an integrated circuit, including the interface multiplexing circuit described above.

[0047] The above embodiments are only for illustrating the technical concept of this application and should not be used to limit the scope of protection of this application. Any modifications made to the technical solution based on the technical concept proposed in this application shall fall within the scope of protection of this application.

Claims

1. An interface multiplexing circuit, applied to an integrated circuit, the interface multiplexing circuit comprising: General purpose signal input circuit, including: The first input buffer is used to receive the input high-voltage digital signal and shape the high-voltage digital signal; The first output buffer converts the shaped high-voltage digital signal into a first low-voltage digital signal. The communication signal input circuit includes: The second input buffer is used to receive communication digital signals from an external chip, process the communication digital signals, and convert them into a second low-voltage digital signal. A filter is used to filter the second low-voltage digital signal; The second output buffer shapes the filtered second low-voltage digital signal. The selector switch is used to select whether to connect the general signal input circuit or the communication signal input circuit.

2. The interface multiplexing circuit as described in claim 1, wherein, The power supply voltage of the first input buffer is the power supply voltage of the integrated circuit.

3. The interface multiplexing circuit as described in claim 1, wherein, The power supply voltage of the second input buffer is the internal digital low-voltage power supply of the integrated circuit.

4. The interface multiplexing circuit as described in claim 1, wherein, When the selection switch is selected to connect the general signal input circuit, the control terminal of the first input buffer is at a high level and the control terminal of the second input buffer is at a low level; when the selection switch is selected to connect the communication signal input circuit, the control terminal of the first input buffer is at a low level and the control terminal of the second input buffer is at a high level.

5. The interface multiplexing circuit as described in claim 1, further comprising: The signal output circuit outputs either the first low-voltage digital signal or the second low-voltage digital signal.

6. The interface multiplexing circuit as described in claim 5, wherein, The signal output circuit includes: The third input buffer shapes the output first low-voltage digital signal or the second low-voltage digital signal. A level shifting circuit, connected to the output of the third input buffer, converts the shaped first low-voltage digital signal or the second low-voltage digital signal into a high-voltage digital signal. The third output buffer is connected to the output terminal of the level transfer circuit to amplify the high-voltage digital signal and output the high-voltage digital signal.

7. The interface multiplexing circuit as described in claim 6, wherein, When the signal output circuit outputs the first low-voltage digital signal or the second low-voltage digital signal, the control terminal of the third output buffer is at a high level.

8. An integrated circuit comprising an interface multiplexing circuit as described in any one of claims 1 to 7.

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