PCI bus and AXI4 bus bridging method

Abstract

The application discloses a PCI bus and AXI4 bus bridging method, 1) converting the PCI bus signal into a localbus bus signal; 2) encoding and decoding the localbus bus signal in step 1), recording the localbus address, and converting the localbus bus access into read access of an axi4_lite interface, write access of the axi4_lite interface, read access of a burst read FIFO, and write access of a burst write FIFO according to the state of LW / R# signals and LAD signals; 3) axi4_lite interface read channel access; 4) axi4_lite interface write channel access; 5) axi4_mm interface read channel access; and 6) axi4_mm interface write channel access. The PCI bus is converted into the AXI4 bus, so that system integration with other IP cores is facilitated; a PCI bridge is adopted, a VIO power supply is used as a bridge PCI signal pin power supply, 3.3V and 5V PCI levels are compatible; burst operation is supported, the communication bandwidth is high, and the application is suitable for high-throughput data communication scenes. The application is suitable for PCI bus, PXI bus and CPCI bus card design based on FPGA.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of computer system, and particularly relates to a PCI bus and AXI4 bus bridging method. BACKGROUND

[0002] The PCI bus has the advantages of high speed, plug and play, high reliability and strong expansibility, and is widely used in personal computers, industrial control computers and servers; the AXI4 bus is the fourth generation of AMBA interface specification, and provides a unified standard interface for plug and play IP cores, and can significantly simplify IP integration. The AXI4 bus has been widely used in high-performance digital systems and designs such as FPGA, and EDA manufacturers generally adopt the open AXI4 standard, so that IP core products of different manufacturers can be conveniently integrated in an SOC.

[0003] A PCI bus controller and a control method thereof (Chinese patent CN105224488B) realize the PCI bus to local bus bridging function based on FPGA, and the disadvantage is that the local bus cannot be conveniently integrated with the IP core based on the AXI4 bus, and the PCI logic realized based on FPGA cannot be compatible with the PCI level when the VIO power supply is 5V; a PCI bus conversion into ISA and APB bus design method (Chinese patent CN104714907B), and the disadvantage is that the APB bus bandwidth is too low, and is not suitable for high-throughput communication scenarios; a PCI bus conversion into local bus communication circuit (Chinese patent CN204066106U), and the disadvantage is that the PCI bus bridge and the FPGA communicate through independent address bus and data bus, and many FPGA pins are occupied. SUMMARY

[0004] In order to overcome the deficiencies of the prior art, the present application provides a PCI bus and AXI4 bus bridging method, 1) converting the PCI bus signal into a localbus bus signal; 2) encoding and decoding the localbus bus signal in step 1), recording the localbus address, and converting the localbus bus access into read access of the axi4_lite interface, write access of the axi4_lite interface, read access of the burst read FIFO, and write access of the burst write FIFO according to the state of the LW / R# signal and the LAD signal; 3) axi4_lite interface read channel access; 4) axi4_lite interface write channel access; 5) axi4_mm interface read channel access; and 6) axi4_mm interface write channel access. The present application converts the PCI bus into the AXI4 bus, which is convenient for system integration with other IP cores; the PCI bridge is used, the VIO power supply is used as the power supply of the PCI signal pin of the bridge, which is compatible with 3.3V and 5V PCI levels; burst operation is supported, the communication bandwidth is high, and it is suitable for high-throughput data communication scenarios. The present application is suitable for PCI bus, PXI bus and CPCI bus card design based on FPGA.

[0005] The technical solution adopted by the present application to solve its technical problems comprises the following steps:

[0006] A PCI bus and AXI4 bus bridging method adopts a PCI bus and AXI4 bus bridging device comprising a PCI bus to localbus bus bridging module and an FPGA module; the FPGA module internally comprises a localbus bus encoding and decoding unit, an axi4_lite interface read channel unit, an axi4_lite interface write channel unit, a burst read FIFO, an axi4_mm interface read channel unit, a burst write FIFO, and an axi4_mm interface write channel unit;

[0007] The PCI bus to localbus bus bridging module is a PCI to localbus bridge; the VIO power supply is used as the power supply of the PCI signal pin of the PCI to localbus bridge; and the localbus bus uses the J mode, and the address signal and the data signal are multiplexed;

[0008] The localbus bus comprises an LW / R# signal, an ADS# signal, a BLAST# signal, a WAIT# signal, a READY# signal, and an LAD signal;

[0009] Step 1: converting the PCI bus signal into a localbus bus signal, using the PCI to localbus bridge, decoding the PCI bus transmission, and re-encoding as localbus bus transmission;

[0010] Step 2: encode and decode the localbus bus signals, record the localbus address, and convert the localbus bus access into an axi4_lite interface read access, an axi4_lite interface write access, a burst read FIFO read access, and a burst write FIFO write access according to the state of the LW / R# signal and the LAD signal;

[0011] Step 3: localbus bus signal encoding and decoding includes the following steps: waiting for the ADS# signal to be valid; if the ADS# signal is valid, recording the address to be accessed, if the LW / R# is low and the LAD corresponding address falls within the corresponding address range of the axi4_lite interface, an axi4_lite interface read channel access is performed; if the LW / R# is high and the LAD corresponding address falls within the corresponding address range of the axi4_lite interface, an axi4_lite interface write channel access is performed; if the LW / R# is low and the LAD corresponding address falls within the corresponding address range of the axi4_mm interface, an axi4_mm read channel access is started, and the burst read FIFO is waited to be non-empty, the burst read FIFO is read, and the data is assigned to the LAD signal; if the LW / R# is high and the LAD corresponding address falls within the corresponding address range of the axi4_mm interface, the LAD signal data is written into the burst write FIFO, and an axi4_mm interface write channel access is started;

[0012] Step 4: axi4_lite interface read channel access: the recorded localbus address is assigned to the axi4_lite interface read channel address, data is read from the axi4_lite address, and the data is assigned to the LAD signal;

[0013] Step 5: axi4_lite interface write channel access: the recorded localbus address is assigned to the axi4_lite interface write channel address, and the data of the LAD signal is written to the axi4_lite address;

[0014] Step 6: axi4_mm interface read channel access: waiting for the idle storage unit of the burst read FIFO to be no less than the amount of axi4_mm interface burst read data once; the recorded localbus address is assigned to the axi4_mm read channel address, the axi4_mm interface read channel burst read operation is started, data is burst read from the axi4_mm interface, the axi4_rdata is written into the burst read FIFO, and the operation is completed until the axi4_mm interface burst read operation is completed;

[0015] Step 7: axi4_mm interface write channel access: waiting for the burst write FIFO data volume to be no less than the axi4_mm interface burst write data volume; assigning the recorded localbus address to the axi4_mm write channel address, starting the axi4_mm interface write channel burst write operation, reading out the data from the burst write FIFO and writing the data into the axi4_wdata in the axi4_mm address space until the axi4_mm interface burst write operation is completed;

[0016] Step 8: the burst read FIFO is used for the axi4_mm interface read channel unit to write data into the FIFO, the localbus bus encoding and decoding unit to read out the data from the FIFO and provide the burst read FIFO state to other modules, including the empty state, the full state, the write end data volume and the read end data volume;

[0017] Step 9: the burst write FIFO is used for the localbus bus encoding and decoding unit to write data into the FIFO, the axi4_mm interface write channel unit to read out the data from the FIFO and provide the burst write FIFO state to other modules, including the empty state, the full state, the write end data volume and the read end data volume.

[0018] Preferably, the VIO power supply is compatible with 3.3V and 5V PCI levels.

[0019] Preferably, the PCI to localbus bridge is a PCI9054 bridge.

[0020] The beneficial effects of the present application are as follows:

[0021] 1. The present application adopts a PCI bridge and an FPGA logic to convert a PCI interface into an axi4_lite interface and an axi4_mm interface, which is convenient for system integration with other IP cores;

[0022] 2. The present application adopts a PCI bridge, uses a VIO power supply as a bridge PCI signal pin power supply, and is compatible with 3.3V and 5V PCI levels;

[0023] 3. The present application supports the conversion of a PCI bus burst operation into an axi4_mm interface burst operation, has high communication bandwidth, and is suitable for high-throughput data communication scenarios;

[0024] 4. The present application adopts a J-mode localbus bus with address signal and data signal pin multiplexing, which saves FPGA pins.

[0025] 5. The PCI bridge that has been tested in the market for a long time is selected to parse PCI bus commands and bus data, which has higher maturity and more sufficient market verification compared with the FPGA-based PCI bus communication logic. BRIEF DESCRIPTION OF DRAWINGS

[0026] Figure 1 The PCI bus and AXI4 bus bridging method flowchart of the present application.

[0027] Figure 2 The PCI bus and AXI4 bus bridging device structure diagram of the present application. DETAILED DESCRIPTION

[0028] The present application is further illustrated below in conjunction with the drawings and examples.

[0029] A PCI bus and AXI4 bus bridging method, the PCI bus and AXI4 bus bridging device used includes a PCI bus to localbus bus bridging module and a FPGA module; the FPGA module internally includes a localbus bus encoding and decoding unit, an axi4_lite interface read channel unit, an axi4_lite interface write channel unit, a burst read FIFO, an axi4_mm interface read channel unit, a burst write FIFO, and an axi4_mm interface write channel unit;

[0030] The PCI bus to localbus bus bridging module is a PCI to localbus bridge; a VIO power supply is used as a PCI to localbus bridge PCI signal pin power supply; the localbus bus uses a J mode, and its address signal and data signal are multiplexed;

[0031] The localbus bus includes a LW / R# signal, an ADS# signal, a BLAST# signal, a WAIT# signal, a READY# signal, and a LAD signal;

[0032] Step 1: convert the PCI bus signal into a localbus bus signal, use a PCI to localbus bridge, decode the PCI bus transmission, and re-encode it as a localbus bus transmission;

[0033] Step 2: encode and decode the localbus bus signal in step 1, record the localbus address, and convert the localbus bus access into an axi4_lite interface read access, an axi4_lite interface write access, a burst read FIFO read access, and a burst write FIFO write access according to the LW / R# signal and the LAD signal state;

[0034] Step 3: localbus bus signal encoding and decoding includes the following steps: waiting for ADS# signal to be valid; if the ADS# signal is valid, recording the address to be accessed, if the LW / R# is low and the LAD corresponding address falls within the corresponding address range of the axi4_lite interface, then performing axi4_lite interface read channel access; if the LW / R# is high and the LAD corresponding address falls within the corresponding address range of the axi4_lite interface, then performing axi4_lite interface write channel access; if the LW / R# is low and the LAD corresponding address falls within the corresponding address range of the axi4_mm interface, then starting axi4_mm read channel access, and waiting for the burst read FIFO to be not empty, reading the burst read FIFO, and assigning the data to the LAD signal; if the LW / R# is high and the LAD corresponding address falls within the corresponding address range of the axi4_mm interface, then writing the LAD signal data into the burst write FIFO, and starting axi4_mm interface write channel access;

[0035] Step 4: axi4_lite interface read channel access: assigning the recorded localbus address to the axi4_lite interface read channel address, reading the data from the axi4_lite address, and assigning the data to the LAD signal;

[0036] Step 5: axi4_lite interface write channel access: assigning the recorded localbus address to the axi4_lite interface write channel address, and writing the data of the LAD signal to the axi4_lite address;

[0037] Step 6: axi4_mm interface read channel access: waiting for the idle storage unit of the burst read FIFO to be not less than the amount of axi4_mm interface burst read data once; assigning the recorded localbus address to the axi4_mm read channel address, starting the axi4_mm interface read channel burst read operation, reading the data from the axi4_mm interface burst, writing the axi4_rdata to the burst read FIFO, and completing the axi4_mm interface burst read operation;

[0038] Step 7: axi4_mm interface write channel access: waiting for the data amount of the burst write FIFO to be not less than the amount of axi4_mm interface burst write data once; assigning the recorded localbus address to the axi4_mm write channel address, starting the axi4_mm interface write channel burst write operation, reading the data from the burst write FIFO and writing the axi4_wdata to the axi4_mm address space, and completing the axi4_mm interface burst write operation;

[0039] Step 8: the burst read FIFO functions are: the axi4_mm interface read channel unit writes data to the FIFO, the localbus bus encoding and decoding unit reads data from the FIFO, and provides the status of the burst read FIFO to other modules, including the empty state, the full state, the data amount at the write end, and the data amount at the read end;

[0040] Step 9: the burst write FIFO functions are: the localbus bus encoding and decoding unit writes data to the FIFO, the axi4_mm interface write channel unit reads data from the FIFO, and provides the status of the burst write FIFO to other modules, including the empty state, the full state, the data amount at the write end, and the data amount at the read end. Embodiments

[0042] The embodiment provides a PCI bus and AXI4 bus bridging method, as shown in the following figure, which comprises the following steps: Figure 1

[0043] S101: convert the PCI bus signal into a localbus bus signal, adopt a PCI9054 bridge, decode the PCI bus transmission, and re-encode the localbus bus transmission;

[0044] S102: encode and decode the localbus bus signal, record the localbus address, and convert the localbus bus access into read access of the axi4_lite interface, write access of the axi4_lite interface, read access of the burst read FIFO, and write access of the burst write FIFO according to the states of the LW / R# signal and the LAD signal;

[0045] S103: axi4_lite interface read channel access, assign the localbus address recorded in step S102 to the axi4_lite interface read channel address, read data from the axi4_lite address, and assign the data to the LAD signal;

[0046] S104: axi4_lite interface write channel access, assign the localbus address recorded in step S102 to the axi4_lite interface write channel address, and write the data of the LAD signal to the axi4_lite address;

[0047] S105: axi4_mm interface read channel access, assign the localbus address recorded in step S102 to the axi4_mm read channel address, read data from the axi4_mm interface burst, and write the axi4_rdata to the burst read FIFO;

[0048] ​S106, access the axi4_mm interface write channel, assign the localbus address recorded in step S102 to the axi4_mm write channel address, and read data from the burst write FIFO and assign it to axi4_wdata;

[0049] In the above PCI bus and AXI4 bus bridging method, step S102, the local bus signal encoding and decoding includes the following steps:

[0050] S201, waiting for ADS# signal to become valid;

[0051] S202, If ADS is valid, record the address to be accessed;

[0052] S203, if LW / R# is low and the address corresponding to LAD falls within the address range of the axi4_lite interface, then access the axi4_lite interface read channel;

[0053] S204, if LW / R# is high and the address corresponding to LAD falls within the address range of the axi4_lite interface, then access the axi4_lite interface write channel;

[0054] S205, if LW / R# is low and the address corresponding to LAD falls within the address range of the axi4_mm interface, then start accessing the axi4_mm read channel, wait for the burst read FIFO to be non-empty, read the burst read FIFO, and assign the data to the LAD signal;

[0055] S206, If LW / R# is high and the address corresponding to LAD falls within the address range of the axi4_mm interface, then write the LAD signal data into the burst write FIFO and start accessing the axi4_mm interface write channel.

[0056] In the above PCI bus and AXI4 bus bridging method, step S203, the axi4_lite interface read channel access includes the following steps:

[0057] S301, Assign the localbus address recorded in step S102 to the axi4_lite interface read channel address, read data from the axi4_lite address, and assign the data to the LAD signal;

[0058] In the above method for bridging the PCI bus and the AXI4 bus, step S204, the axi4_lite interface write channel access includes the following steps:

[0059] S401, Assign the localbus address recorded in step S102 to the write channel address of the axi4_lite interface, and write the LAD signal data to the axi4_lite address;

[0060] In the above PCI bus and AXI4 bus bridging method, step S105, the axi4_mm interface read channel access includes the following steps:

[0061] S501, the amount of data to be read from a burst FIFO free storage unit is not less than the amount of data read from axi4_mm interface in one burst;

[0062] S502, initiates axi4_mm interface read channel burst read operation, writes the read data into burst read FIFO, until the axi4_mm interface burst read operation is completed;

[0063] In the above PCI bus and AXI4 bus bridging method, step S106, the axi4_mm interface write channel access includes the following steps:

[0064] S601, waiting for the burst write FIFO data volume to be no less than the burst write data volume of the axi4_mm interface;

[0065] S602, initiates a burst write operation on the axi4_mm interface write channel, reads data from the burst write FIFO and writes it into the axi4_mm address space until the burst write operation on the axi4_mm interface is completed.

[0066] This embodiment provides a PCI bus and AXI4 bus bridging device, such as Figure 2 As shown, it includes: a PCI bus to localbus bus bridging module 101 and an FPGA module 102; the FPGA module internally includes a localbus bus encoding / decoding unit 103, an axi4_lite interface read channel unit 104, an axi4_lite interface write channel unit 105, a burst read FIFO 106, an axi4_mm interface read channel unit 107, a burst write FIFO 108, and an axi4_mm interface write channel unit 109;

[0067] The PCI bus to localbus bridging module 101 uses the feature-rich and widely used PCI9054 bridge chip; it uses VIO power supply as the power supply for the bridge chip's PCI signal pins, and is compatible with 3.3V and 5V PCI levels; the localbus uses J mode, where address and data signals are multiplexed, saving many IO pins for the FPGA connected to it.

[0068] The FPGA module 102 uses the Xilinx XC7A35T-2FGG484I chip, uses Vivado software to develop FPGA logic, supports BLOCK DESIGN design mode, and is convenient for IP core integration design based on AXI4 bus.

[0069] The localbus bus codec unit 103 includes the following steps: waiting for the ADS# signal to be valid; if the ADS is valid, recording the address to be accessed, if the LW / R# is low and the LAD corresponding address falls within the corresponding address range of the axi4_lite interface, performing axi4_lite interface read channel access; if the LW / R# is high and the LAD corresponding address falls within the corresponding address range of the axi4_lite interface, performing axi4_lite interface write channel access; if the LW / R# is low and the LAD corresponding address falls within the corresponding address range of the axi4_mm interface, starting axi4_mm read channel access, and waiting for the burst read FIFO to be non-empty, reading the burst read FIFO, and assigning the data to the LAD signal; if the LW / R# is high and the LAD corresponding address falls within the corresponding address range of the axi4_mm interface, writing the LAD signal data into the burst write FIFO, and starting axi4_mm interface write channel access;

[0070] The axi4_lite interface read channel unit 104 includes the following steps: assigning the localbus address recorded in step 2) to the axi4_lite interface read channel address, reading data from the axi4_lite address, and assigning the data to the LAD signal;

[0071] The axi4_lite interface write channel unit 105 includes the following steps: assigning the localbus address to the axi4_lite interface write channel address, and writing the data of the LAD signal to the axi4_lite address;

[0072] The burst read FIFO 106 functions as follows: the axi4_mm interface read channel unit writes data into the FIFO, the localbus bus codec unit reads data from the FIFO, and the burst read FIFO state, including the empty state, full state, write end data volume, and read end data volume, is provided to other modules;

[0073] The axi4_mm interface read channel unit 107 includes the following steps: waiting for the idle storage unit of the burst read FIFO to be no less than the axi4_mm interface burst read data volume once; starting the axi4_mm interface read channel burst read operation, writing the read data into the burst read FIFO, and completing the axi4_mm interface burst read operation;

[0074] The burst write FIFO 108 functions as follows: the localbus bus codec unit writes data into the FIFO, the axi4_mm interface write channel unit reads data from the FIFO, and the burst write FIFO state, including the empty state, full state, write end data volume, and read end data volume, is provided to other modules;

[0075] The axi4_mm interface write channel unit 109 includes the following steps: waiting for the burst write FIFO data volume to be no less than the axi4_mm interface burst write data volume; starting the axi4_mm interface write channel burst write operation, reading out data from the burst write FIFO and writing the data into the axi4_mm address space until the current axi4_mm interface burst write operation is completed.

Claims

1. A method for bridging a PCI bus and an AXI4 bus, characterized in that, The PCI bus and AXI4 bus bridging device includes a PCI bus to localbus bus bridging module and an FPGA module; the FPGA module internally includes a localbus bus encoding / decoding unit, an axi4_lite interface read channel unit, an axi4_lite interface write channel unit, a burst read FIFO, an axi4_mm interface read channel unit, a burst write FIFO, and an axi4_mm interface write channel unit. The PCI bus to localbus bridge module is a PCI to localbus bridge chip; VIO power supply is used as the power supply for the PCI signal pins of the PCI to localbus bridge chip; the localbus uses J mode, and its address signals and data signals are multiplexed. The localbus bus includes the LW / R# signal, ADS# signal, BLAST# signal, WAIT# signal, READY# signal, and LAD signal. Step 1: Convert PCI bus signals to localbus bus signals, use a PCI to localbus bridge chip to decode PCI bus transmission, and re-encode it into localbus bus transmission; Step 2: Encode and decode the localbus bus signals in Step 1, record the localbus address, and convert the localbus bus access into read access to the axi4_lite interface, write access to the axi4_lite interface, read access to the burst read FIFO, and write access to the burst write FIFO according to the LW / R# signal and LAD signal status. Step 3: Localbus signal encoding and decoding includes the following steps: Wait for the ADS# signal to be valid; if the ADS# signal is valid, record the address to be accessed; if LW / R# is low and the address corresponding to LAD falls within the address range of the axi4_lite interface, then perform axi4_lite interface read channel access; if LW / R# is high and the address corresponding to LAD falls within the address range of the axi4_lite interface, then perform axi4_lite interface write channel access; if LW / R# is low and the address corresponding to LAD falls within the address range of the axi4_mm interface, then start axi4_mm read channel access, and wait for the burst read FIFO to be non-empty, read the burst read FIFO, and assign the data to the LAD signal; if LW / R# is high and the address corresponding to LAD falls within the address range of the axi4_mm interface, then write the LAD signal data to the burst write FIFO and start axi4_mm interface write channel access. Step 4: axi4_lite interface read channel access: Assign the recorded localbus address to the axi4_lite interface read channel address, read data from the axi4_lite address, and assign the data to the LAD signal; Step 5: axi4_lite interface write channel access: Assign the recorded localbus address to the axi4_lite interface write channel address, and write the LAD signal data to the axi4_lite address; Step 6: Axi4_mm interface read channel access: Wait for the burst read FIFO to have an idle storage unit size of at least one Axi4_mm interface burst read data volume; assign the recorded localbus address to the Axi4_mm read channel address, start the Axi4_mm interface read channel burst read operation, burst read data from the Axi4_mm interface, write axi4_rdata to the burst read FIFO, until the current Axi4_mm interface burst read operation is completed; Step 7: axi4_mm interface write channel access: Wait for the burst write FIFO data volume to be no less than the burst write data volume of the axi4_mm interface; assign the recorded localbus address to the axi4_mm write channel address, start the axi4_mm interface write channel burst write operation, read data from the burst write FIFO and write it into the axi4_mm address space axi4_wdata, until the current axi4_mm interface burst write operation is completed; Step 8: The function of the burst read FIFO is: the axi4_mm interface read channel unit writes data to the FIFO, the localbus bus encoding and decoding unit reads data from the FIFO, and provides other modules with the status of the burst read FIFO, including empty status, full status, amount of data written, and amount of data read. Step 9: The function of the burst write FIFO is: the localbus bus encoding and decoding unit writes data to the FIFO, the axi4_mm interface write channel unit reads data from the FIFO, and provides other modules with the status of the burst write FIFO, including empty status, full status, amount of data written, and amount of data read.

2. The method for bridging a PCI bus and an AXI4 bus according to claim 1, characterized in that, VIO power supply is compatible with 3.3V and 5V PCI levels.

3. The method for bridging a PCI bus and an AXI4 bus according to claim 1, characterized in that, The PCI to localbus bridge chip is the PCI9054 bridge chip.

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