PCIe verification IP automatic integration method and system supporting multiple working modes

Abstract

The application provides a PCIe verification IP automatic integration method supporting multiple working modes, and the method comprises the following steps: providing a configurable configuration file; rendering a template file by using a python-based template engine jinja2 of an automatic verification generation platform; automatically completing the connection relationship between a PIPE level and a SerDes interface level PCIe verification IP and a DUT; automatically generating a PCIe VIP task library; and providing a user with a basic task library for basic transmission path and PCIe protocol verification. The application greatly reduces the platform building time in the front-end verification, so that the verification engineers can pay more attention to the protocol and function verification, meanwhile, the application avoids the time waste caused by some unexpected human errors, greatly improves the simulation speed and the debugging efficiency, and is used for the initial development of the front-end verification. The Serdes level simulation adopts the behavior description level code of the PHY, is closer to the real chip, and is more suitable for the regression test in the later stage of the front-end verification.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, especially to the chip design technical field, and in particular to a PCIe verification IP automatic integration method and system supporting multiple working modes. BACKGROUND

[0002] With the rapid development of big data centers, artificial intelligence, cloud computing and super large scale computing, the demand for high-speed hardware data interaction in servers becomes increasingly important. As a point-to-point high-speed serial bus standard, the PCIe bus plays an important role in this regard and gradually becomes the mainstream solution for server buses, and is widely used in server-related integrated circuit design. In the mainstream solution of server buses, the PHY branching and aggregation functions are often applied to develop diversified working modes according to different application scenarios, which undoubtedly greatly increases the complexity of the PCIe bus system, and naturally undoubtedly greatly increases the complexity of the verification test platform building in the chip front-end verification and the non-reusability of the verification test platform. Therefore, how to improve the efficiency of the verification test platform building at high speed and effectively, and shorten the verification test platform building becomes increasingly important. The present application will mainly provide a configurable PCIe verification IP automatic integration method supporting multiple working modes to efficiently, quickly and accurately complete the automatic integration of the PCIe verification IP, and avoid errors caused by human factors.

[0003] In the traditional PCIe bus system chip front-end verification process, the chip front-end verification engineer manually integrates mature and stable commercial PCIe verification IP in the process of building a verification test platform, which is undoubtedly a time-consuming and labor-intensive work with high repeatability. Moreover, due to the demand for diversified working modes, the reusability of the verification test platform is greatly reduced. The present application will mainly propose a method to complete the PCIe verification IP automatic integration test verification platform, provide a standardized processing procedure to identify different working mode selections, and then complete the correct instantiation and connection of the PCIe verification IP, provide a PIPE level connection mode to greatly accelerate the simulation speed and increase the front-end verification efficiency. SUMMARY

[0004] Therefore, the present application aims to provide a PCIe verification IP automatic integration method and system supporting multiple working modes, so that the entire verification test platform has stronger reusability.

[0005] In the traditional PCIe bus system chip front-end verification process, the chip front-end verification engineer manually integrates mature and stable commercial PCIe verification IP into the verification test platform during the process of building the verification test platform, which is undoubtedly a time-consuming and labor-intensive work with high repeatability, and due to the needs of diversified working modes, the reusability of the verification test platform is greatly reduced. The present application will mainly aim at the above needs to provide a method to complete the PCIe verification IP automatic integration test verification platform, provide a standardized processing flow to identify different working mode selection, and then complete the correct instantiation and connection of the PCIe verification IP, provide the PIPE level connection mode to greatly accelerate the simulation speed and increase the efficiency of the front-end verification. Specifically, the PCIe verification IP automatic integration method supporting multiple working modes includes the following steps: providing a configurable configuration file to determine the custom configuration file; the automatic verification generation platform completes the rendering of the template file based on the python template engine jinja2, fills in the template file as the final output verification test platform file according to the parameters of the configuration file; automatically complete the connection relationship between the PIPE level and SerDes interface level PCIe verification IP and the DUT, the user can switch the SerDes interface level simulation and the PIPE level simulation through the parameters in the Makefile; automatically generate a PCIe VIP task library to provide a basic task library for the user to verify the basic transmission path and the PCIe protocol.

[0006] Based on the above purpose, in one aspect, the present application provides a PCIe verification IP automatic integration method supporting multiple working modes, wherein the method includes the following steps:

[0007] A configurable configuration file is provided to determine the custom configuration file;

[0008] The automatic verification generation platform completes the rendering of the template file based on the python template engine jinja2, fills in the template file as the final output verification test platform file according to the parameters of the configuration file;

[0009] The connection relationship between the PIPE level and SerDes interface level PCIe verification IP and the DUT is automatically completed, and the user can switch the SerDes interface level simulation and the PIPE level simulation through the parameters in the Makefile;

[0010] A PCIe VIP task library is automatically generated to provide a basic task library for the user to verify the basic transmission path and the PCIe protocol.

[0011] In some embodiments of the PCIe verification IP automatic integration method supporting multiple working modes according to the present application, the method for providing a configurable configuration file and determining a customized configuration file specifically includes:

[0012] The user determines the basic parameters of the PCIe verification IP through clear and explicit configuration parameters;

[0013] The automatic integration of the PCIe verification IP on the verification test platform is completed;

[0014] The configuration file of the working mode is generated;

[0015] The user defines the working mode used in simulation according to the configuration file.

[0016] In some embodiments of the PCIe verification IP automatic integration method supporting multiple working modes according to the present application, the customized configuration file is completed by a configuration file definition module, wherein the configuration file definition module includes:

[0017] A project name definition unit specifies the project name through projName, which determines the folder name when the verification test platform is generated;

[0018] An absolute path determination unit specifies the absolute path of the top file of the design under test through dut.

[0019] In some embodiments of the PCIe verification IP automatic integration method supporting multiple working modes according to the present application, the automatic verification generation platform completes the rendering of the template file based on the python-based template engine jinja2, and the method for filling the template file into the final verification test platform file to be output according to the parameters of the configuration file specifically includes:

[0020] The instantiation of the PCIe VIP PIPE is added in the top template file of the verification test platform, and the number of instantiated PIPEs is determined according to the number of channels in the configuration file;

[0021] The uvm_config_db function provided by UVM is used to pass it to the base_test component;

[0022] The configuration file of the working mode selection is generated under the simulation execution path;

[0023] The PCIe VIP configuration template file is created, the split function of the string is used to complete the parsing of the working mode configuration file, and the parsed result is passed to the base_test component through the uvm_config_db function provided by UVM;

[0024] In the Makefile template file, the compilation of the PCIe VIP source code is added, and a mode selection switch of PIPE level simulation and corresponding macro definition are added.

[0025] In some embodiments of the PCIe verification IP automatic integration method supporting multiple working modes according to the present application, the creation of the PCIe VIP configuration template file is completed by implementing a split function of a string, the parsed results are passed to the base_test component through a uvm_config_db function provided by UVM, and the method specifically includes:

[0026] The string array of the PCIe VIP group is initialized according to the user-defined file configuration file, the group_name of the VIP to be integrated of the type EP is stored in the string array of the EP, and the group_name of the VIP to be integrated of the type RC is stored in the string array of the RC;

[0027] The working mode selection configuration file is read line by line;

[0028] It is identified whether the name of the PCIe group of each line is in the string array of the initialized PCIe VIP group of the EP / RC, if it is in the definition, the working mode selection information is separated through a string“x” by implementing a split function of a string, the number m of the VIP in the PCIe VIP group and the channel number n of each VIP are obtained, n is put into the corresponding EP / RC result queue through a repeat function for m times, otherwise, the uvm_error provided by UVM is reported, and subsequent processing is not performed;

[0029] The EP / RC result queue is passed to the base_test component through the config_db function provided by UVM.

[0030] In some embodiments of the PCIe verification IP automatic integration method supporting multiple working modes according to the present application, the template engine jinja2 based on python of the automatic verification generation platform is used to complete the rendering of the template file, the template file is filled according to the parameters of the configuration file, and the method of filling the template file as the final verification test platform file output includes the following steps:

[0031] The instantiation of the PCIe VIP and the PIPE distribution are added in the PCIe base test template file.

[0032] In some embodiments of the PCIe verification IP automatic integration method supporting multiple working modes according to the application, the method of adding the instantiation of the PCIe VIP and the PIPE distribution in the PCIe base test template file comprises the following steps:

[0033] The result queues of the EP and RC are obtained by the config_db function in the UVM.

[0034] According to the size of the EP and RC result queues, the space allocation of the EP BFM dynamic array and the RC BFM dynamic array is completed, and each BFM is instantiated and created.

[0035] The number of channels obtained by the POP operation from the result EP and RC queues is used for the PIPE distribution, and the corresponding number of PIPEs is distributed to the PCIe VIP BFM in sequence.

[0036] The PCIe VIP is configured to start the BFM work.

[0037] In some embodiments of the PCIe verification IP automatic integration method supporting multiple working modes according to the application, the PCIe VIP task library is automatically generated, and a basic task library is provided for a user to verify the basic transmission path and the PCIe protocol, and the method comprises the following steps:

[0038] The PCIe VIP task library template is defined.

[0039] The basic tasks of the PCIe protocol are added.

[0040] The defined task library is included in the template file of the test_pkg, so that all the test cases at present and the test cases derived and inherited later can use the tasks in the task library, and the repeated development of the same function tasks by different verification engineers is avoided.

[0041] Another aspect of the application also provides a PCIe verification IP automatic integration system supporting multiple working modes, which comprises the following steps:

[0042] The configuration file providing module is used for providing a configurable configuration file and determining a custom configuration file.

[0043] The automatic verification generation platform is used for rendering the template file based on the template engine jinja2 of python, and filling the template file into the final verification test platform file to be output according to the parameters of the configuration file.

[0044] a PCIe verification module, configured to automatically complete a connection relationship between a PCIe verification IP and a DUT at a PIPE level and a SerDes interface level, and a user can switch the SerDes interface level simulation and the PIPE level simulation through a parameter in a Makefile;

[0045] a task library generation module, configured to automatically generate a PCIe VIP task library, and provide a basic task library for a user to verify a basic transmission path and a PCIe protocol.

[0046] In some embodiments of the configurable PCIe verification IP automatic integration system supporting multiple working modes according to the application, the configuration file providing module comprises:

[0047] a parameter determination unit, configured to complete determination of basic parameters of the PCIe verification IP through clear and explicit configuration parameters;

[0048] a platform integration unit, configured to complete automatic integration of the PCIe verification IP on a verification test platform;

[0049] a configuration file generation unit, configured to generate a configuration file of the working mode;

[0050] a mode simulation unit, configured to simulate the working mode used in simulation according to the configuration file.

[0051] The present application has at least the following beneficial technical effects: a conventional verification platform automatic generation method only generates a universal verification test platform, and does not automatically integrate a PCIe VIP in the verification platform according to the requirements of a project; the present application aims to provide a verification platform method automatic generation method, so that the PCIe VIP can be automatically integrated in the verification platform through simple and clear parameters, greatly reducing the time for platform building in front-end verification, so that verification engineers can focus more on protocol and function verification, and meanwhile, time waste caused by some unexpected human errors is avoided; a general working mode analysis method is provided, greatly increasing the configurable diversity of the working mode, so that the entire verification test platform has stronger reusability; PIPE level simulation and Serdes level simulation modes are provided, and a user can automatically switch by using a Makefile, the PIPE level simulation adopts a PHY BFM for simulation, greatly improving the simulation speed and the debugging efficiency, and is used for initial development in front-end verification, the Serdes level simulation adopts a behavior description level code of a PHY, is closer to a real chip, and is more suitable for regression testing in a later stage of front-end verification, and the two can better meet different stages of front-end verification; a basic task library is provided, avoiding repeated development of different verification engineers on the same function task, and also providing a basic method for PCIe basic channel verification. BRIEF DESCRIPTION OF DRAWINGS

[0052] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description only some embodiments of the present application, and for those skilled in the art, other embodiments can be obtained without creative labor on the basis of these drawings.

[0053] In the drawings:

[0054] Figure 1 The implementation flowchart of the PCIe verification IP automatic integration method of the present application is shown.

[0055] Figure 2 The implementation flowchart of the method for determining the self-defined configuration file is shown.

[0056] Figure 3 The user self-defined configuration file according to the present application is shown.

[0057] Figure 4 The implementation flowchart of the method for filling the template file into the final verification test platform file output according to the parameters of the configuration file is shown.

[0058] Figure 5 Fig. 1 shows a configuration file format diagram according to the working mode in the present application;

[0059] Figure 6 Fig. 2 shows a creation of a PCIe VIP configuration template file in the present application, and a parsing implementation flowchart of the working mode configuration file is completed by implementing a split function of a string;

[0060] Figure 7 Fig. 3 shows a method implementation flowchart of adding a PCIe VIP instantiation and a PIPE distribution in a PCIe base test template file;

[0061] Figure 8 Fig. 4 shows a method diagram of arbitrarily switching SerDes interface level simulation and PIPE level simulation through a parameter in a Makefile;

[0062] Figure 9 Fig. 5 shows a connection relationship diagram in a verification platform top-level file according to the present application;

[0063] Figure 10 Fig. 6 shows a connection relationship diagram in a verification platform top-level file according to the present application;

[0064] Figure 11 Fig. 7 shows a method implementation flowchart of automatically generating a PCIe VIP task library according to the present application, and providing a user with a basic task library for verifying a basic transmission path and a PCIe protocol;

[0065] Figure 12 Fig. 8 shows a diagram of a framework of an embodiment of a PCIe verification IP automatic integration system according to the present application which can be configured to support multiple working modes;

[0066] Figure 13 Fig. 9 shows a diagram of a configuration file providing module according to the present application. DETAILED DESCRIPTION

[0067] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application is further described in detail below with reference to specific embodiments and the accompanying drawings.

[0068] It should be noted that all the expressions of "first" and "second" in the embodiments of the present application are used to distinguish two non-same entities or non-same parameters with the same name, and the "first" and "second" are only for the convenience of description, and should not be understood as the limitation of the embodiments of the present application. In addition, the terms "include" and "have" and any variations thereof are intended to cover non-exclusive inclusion, for example, the process, method, system, product or device inherently includes other steps or units.

[0069] In the traditional PCIe bus system chip front-end verification process, the chip front-end verification engineer manually integrates mature and stable commercial PCIe verification IP in the process of building a verification test platform, which is undoubtedly a time-consuming and labor-intensive work with high repeatability, and due to the demand of diversified working modes, the reusability of the verification test platform is greatly reduced. The present application will mainly aim at the above demand to provide a method to complete the automatic integration of PCIe verification IP test verification platform, provide a standardized processing flow to identify different working mode selection, and then complete the correct instantiation and connection of PCIe verification IP, provide PIPE level connection mode to greatly accelerate the simulation speed and increase the efficiency of front-end verification. Specifically, the configurable PCIe verification IP automatic integration method supporting multiple working modes comprises the following steps: providing a configurable configuration file to determine a custom configuration file; the automatic verification generation platform completes the rendering of the template file based on the python template engine jinja2, fills the template file into the final output verification test platform file according to the parameters of the configuration file; automatically complete the connection relationship between the PIPE level and SerDes interface level PCIe verification IP and the DUT, and the user can switch the SerDes interface level simulation and the PIPE level simulation at will through the parameters in the Makefile; automatically generate a PCIe VIP task library to provide a basic task library for the user to verify the basic transmission path and PCIe protocol.

[0070] The embodiments of the present application provide a configurable PCIe verification IP automatic integration supporting multiple working modes, as shown in the following table: Figure 1 The configurable PCIe verification IP automatic integration method supporting multiple working modes specifically comprises the following steps:

[0071] Step S10, providing a configurable configuration file to determine a custom configuration file;

[0072] Step S20, the automatic verification generation platform completes the rendering of the template file based on the python template engine jinja2, fills the template file into the final output verification test platform file according to the parameters of the configuration file;

[0073] Step S30, automatically complete the connection relationship between the PCIe verification IP and the DUT in the PIPE level and the SerDes interface level, and the user can switch the SerDes interface level simulation and the PIPE level simulation arbitrarily through the parameters in the Makefile.

[0074] Step S40, automatically generate the PCIe VIP task library, and provide a basic task library for the user to verify the basic transmission path and the PCIe protocol.

[0075] In the embodiment, the application aims to provide a verification platform method automatic generation method, so that the PCIe VIP can be automatically integrated in the verification platform through simple and clear parameters, the time for building the platform in the front-end verification is greatly reduced, the verification engineer can pay more attention to the protocol and function verification, meanwhile, the time waste caused by some unexpected human errors is avoided, a general working mode analysis method is provided, the configurable diversity of the working mode is greatly increased, the whole verification test platform has stronger reusability, PIPE level simulation and SerDes level simulation two modes are provided, the user can automatically switch through the Makefile, the PIPE level simulation adopts the PHY BFM for simulation, the simulation speed and the debugging efficiency are greatly improved, and the PIPE level simulation is used for the initial development in the front-end verification, the SerDes level simulation adopts the behavior description level code of the PHY, is closer to the real chip, and is more suitable for the regression test in the later stage of the front-end verification, the two modes can better meet different stages of the front-end verification, a basic task library is provided, the repeated development of the same function task by different verification engineers is avoided, and the basic method for the PCIe basic path verification is provided.

[0076] The embodiment of the application provides a configurable configuration file, and a method for determining a custom configuration file. Figure 2 As shown in the figure, a configurable configuration file is provided, and a method for determining a custom configuration file is provided.

[0077] Step S101, the user determines the basic parameters of the PCIe verification IP through clear and explicit configuration parameters.

[0078] Step S102, the automatic integration of the PCIe verification IP in the verification test platform is completed.

[0079] Step S103, a configuration file of the working mode is generated.

[0080] Step S104, the user defines the working mode used in the simulation according to the configuration file.

[0081] In the embodiment, the custom configuration file is completed by a configuration file definition module, wherein the configuration file definition module comprises:

[0082] A project name definition unit specifies a project name by projName, which determines the folder name when the verification test platform is generated.

[0083] An absolute path determination unit specifies the absolute path of the top file of the design under test by dut.

[0084] Meanwhile, in the present application, as shown in the user custom configuration file schematic diagram, Figure 3 The projName is used to specify the project name, which determines the folder name when the verification test platform is generated; the dut is used to specify the absolute path of the top file of the design under test; the dutName is used to specify the top module name in the top file, and the parameter and the absolute path of the top file cooperatively complete the automatic connection function of the verification test platform and the DUT; the topName is used to specify the prefix name of the verification test platform file; the backup is a backup option, when it is specified as yes, the original project environment is automatically backed up, otherwise the original project environment is overwritten; the pcie_vip is used to complete the parameter determination of the PCIe VIP in the verification test platform, wherein the group_name represents the name of the integrated PCIe VIP group, which is used to generate the configuration file of the working mode selection; the type of VIP to be integrated is used to specify the type of the PCIe VIP, and the PCIe VIP types supported in the present application include RC and EP; the PIPE depth is used to specify the data bit width of each channel of the PIPE; the number of channels is used to specify the total number of channels of the PCIe VIP group; the PIPE level is used to specify the relative level of the PIPE in the verification test platform; and the PIPE file path is used to specify the absolute path of the file of the DUT corresponding to the PCIe PIPE, and the parameter cooperatively completes the automatic connection function of the PIPE level DUT and the PCIe VIP with the PIPE level parameter.

[0085] The embodiment of the present application provides a method for rendering a template file by a python-based template engine jinja2 of an automatic verification generation platform, and filling the template file into a verification test platform file to be finally output according to parameters of a configuration file. Figure 4 As shown in the method for rendering a template file by a python-based template engine jinja2 of an automatic verification generation platform, and filling the template file into a verification test platform file to be finally output according to parameters of a configuration file, the method specifically comprises the following steps:

[0086] Step S201, add the instantiation of the PCIe VIP PIPE in the verification test platform top-level template file, and determine the number of instantiated PIPEs according to the number of channels in the configuration file;

[0087] Step S202, pass it to the base_test component through the uvm_config_db function provided by UVM;

[0088] Step S203, generate the configuration file of the working mode selection under the simulation execution path.

[0089] In this step, as shown in Figure 5 , a configuration file format diagram of the working mode is shown, wherein the left side of “:” is the group_name in the configuration file, which is used for the user to direct the configuration of the corresponding PCIe VIP group, and the right side of “:” represents the working mode selection of the PHY, which can be customized by the user according to the project requirements, wherein the left side of “x” represents the number of VIPs in the corresponding PCIe VIP group, and the right side of “x” represents the number of channels of each VIP in each PCIe VIP group. For example, group1:8x2 represents that 8 PCIe VIPs with 2 channels need to be instantiated in the “group1” PCIe VIP group.

[0090] Step S204, creation of the PCIe VIP configuration template file, the split function of the string is implemented to complete the parsing of the working mode configuration file, and the parsed result is passed to the base_test component through the uvm_config_db function provided by UVM;

[0091] Step S205, add the compilation of the PCIe VIP source code in the Makefile template file, and add the mode selection switch and the corresponding macro definition of the PIPE-level simulation.

[0092] Exemplarily, the compilation of the PCIe VIP source code is added in the Makefile template file, the mode selection switch and the corresponding macro definition of the PIPE-level simulation are added, and the specific process is as follows;

[0093] MODE?=

[0094] ifeq(PIPE, $(strip($MODE)))

[0095] MODE_OPTS:=+define+PIPE_MODE

[0096] endif.

[0097] Step S206, adding instantiation of the PCIe VIP and PIPE distribution in the PCIe base test template file.

[0098] The embodiment of the application provides creation of a PCIe VIP configuration template file, and a method for parsing a configuration file of a working mode by implementing a split function of a string and transmitting a result of the parsing to a base_test component by using a uvm_config_db function provided by UVM, as shown in the following table. Figure 6 The creation of the PCIe VIP configuration template file, the method for parsing the configuration file of the working mode by implementing the split function of the string and transmitting the result of the parsing to the base_test component by using the uvm_config_db function provided by UVM, specifically includes the following steps.

[0099] Step S301, creating a string array of an initialization PCIe VIP group of EP and RC according to a user-defined file configuration file, storing all group_name of the VIP type EP to be integrated in the user configuration file in the string array of the EP, and storing all group_name of the VIP type RC to be integrated in the user configuration file in the string array of the RC;

[0100] Step S302, reading the configuration file of the working mode selection line by line.

[0101] Step S303, identifying whether the name of the PCIe group of each line is in the string array of the initialization PCIe VIP group of the EP and RC, if yes, separating the working mode selection information by using the split function of the string through a string "x" to obtain the number m of the VIP in the PCIe VIP group and the channel number n of each VIP, and putting n into a corresponding EP / RC result queue by repeating m times through a repeat function, otherwise, reporting by using a uvm_error provided by UVM and not performing subsequent processing.

[0102] Step S304, transmitting the EP / RC result queue to the base_test component by using a config_db function provided by UVM.

[0103] The embodiment of the application provides the method for adding instantiation of the PCIe VIP and PIPE distribution in the PCIe base test template file, as shown in the following table. Figure 7 The method for adding instantiation of the PCIe VIP and PIPE distribution in the PCIe base test template file specifically includes the following steps.

[0104] Step S2061, the result queues of EP and RC passed by the PCIe VIP configuration are obtained through the config_db function in UVM;

[0105] Step S2062, according to the size of the EP and RC result queues, the space allocation of the EP BFM dynamic array and the RC BFM dynamic array is completed, and each BFM is instantiated and created;

[0106] Step S2063, the channel number obtained by the POP operation from the result EP and RC queues is used for PIPE allocation, and the corresponding number of PIPEs is allocated to the PCIe VIP BFM in sequence;

[0107] Step S2064, the PCIe VIP is configured to start the BFM work.

[0108] The embodiment of the application provides a method for automatically completing the connection relationship between the PCIe verification IP and the DUT at the PIPE level and the SerDes interface level, and a user can perform arbitrary switching of SerDes interface level simulation and PIPE level simulation through parameters in a Makefile, as shown in the following table: Figure 8 The method for automatically completing the connection relationship between the PCIe verification IP and the DUT at the PIPE level and the SerDes interface level, and the user can perform arbitrary switching of SerDes interface level simulation and PIPE level simulation through parameters in a Makefile, and the method specifically comprises the following steps:

[0109] Step S401, in a test platform top-level file, the PIPE level connection relationship and the Serdes connection relationship are distinguished through a macro definition corresponding to a PIPE mode switch in a Makefile file.

[0110] Step S402, according to a PIPE file path configured by a user, interface information of a top-level module of a PIPE file is found through a regular matching expression.

[0111] Step S403, according to the matched interface information, a PIPE signal meeting a certain naming rule is identified, and automatic connection with a PCIe VIP is completed, as shown in the following table: Figure 5 The macro PIPE_PATH defined herein is generated by a PIPE level configured by the user, and PIPE_WIDTH is a PIPE data bit width defined by the user.

[0112] In the embodiment, as shown in the following table: Figure 9As shown, the connection diagram in the top-level file of the verification platform is illustrated. In the top-level file of the test platform, the PIPE-level connection relationship and the Serdes connection relationship are distinguished by the macro definition corresponding to the PIPE mode switch in the Makefile file.

[0113] like Figure 10 The diagram shows the connection relationship of PIPEs in the test platform. Based on the matched interface information, PIPE signals conforming to certain naming rules are identified, and automatic connection with the PCIe VIP is completed. Specifically... Figure 5 As shown. The macro PIPE_PATH is generated by the PIPE hierarchy configured by the user, and PIPE_WIDTH is the user-defined PIPE data width.

[0114] This invention provides an automatically generated PCIe VIP task library, offering users a basic task library for verifying basic transmission paths and the PCIe protocol, such as... Figure 11 As shown, the automatically generated PCIe VIP task library provides users with a basic task library for verifying basic transmission paths and the PCIe protocol, specifically including:

[0115] Step S501: Define the PCIe VIP task library template;

[0116] Step S502: Add the basic tasks of the PCIe protocol;

[0117] Step S503: Include the defined task library into the template file of test_pkg, so that all current test cases and subsequent derived test cases can use the tasks in the task library, avoiding the duplication of development of the same functional tasks by different verification engineers.

[0118] This invention provides a configurable PCIe authentication IP automatic integration system that supports multiple operating modes, such as... Figure 12 As shown, the configurable PCIe authentication IP automatic integration system supporting multiple working modes specifically includes:

[0119] The configuration file provider module 100 is used to provide configurable configuration files and determine custom configuration files;

[0120] An automated verification generation platform 200 is used to render template files based on the Python template engine Jinja2. The template files are filled with parameters from the configuration file to form the final output verification test platform file.

[0121] The PCIe verification module 300 is used for automatically completing the connection relationship between the PCIe verification IP and the DUT at the PIPE level and the SerDes interface level, and the user can switch the SerDes interface level simulation and the PIPE level simulation through the parameters in the Makefile.

[0122] The task library generation module 400 is used for automatically generating the PCIe VIP task library, and provides a basic task library for the user to verify the basic transmission path and the PCIe protocol.

[0123] In the embodiment, the application aims to provide a verification platform method automatic generation system, so that the PCIe VIP can be automatically integrated in the verification platform through simple and clear parameters, the time for building the platform in the front-end verification is greatly reduced, the verification engineer can pay more attention to the protocol and function verification, meanwhile, the time waste caused by some unexpected human errors is avoided, a general working mode analysis method is provided, the configurable diversity of the working mode is greatly increased, the whole verification test platform has stronger reusability, PIPE level simulation and SerDes level simulation two modes are provided, the user can automatically switch through the Makefile, the PIPE level simulation adopts the PHY BFM for simulation, the simulation speed and the debugging efficiency are greatly improved, and the PIPE level simulation is used for the initial development in the front-end verification, the SerDes level simulation adopts the behavior description level code of the PHY, is closer to the real chip, and is more suitable for the regression test in the later stage of the front-end verification, the two modes can better meet different stages of the front-end verification, a basic task library is provided, the repeated development of the same function task by different verification engineers is avoided, and the basic system of the PCIe basic path verification is provided.

[0124] The application embodiment provides a configuration file providing module, as shown in the following table. Figure 13 The configuration file providing module 100 specifically comprises the following.

[0125] The parameter determination unit 110 is used for determining the basic parameters of the PCIe verification IP through clear and explicit configuration parameters.

[0126] The platform integration unit 120 is used for automatically integrating the PCIe verification IP in the verification test platform.

[0127] The configuration file generation unit 130 is used for generating the configuration file of the working mode.

[0128] The mode simulation unit 140 is used for defining the working mode used in the simulation according to the configuration file.

[0129] The embodiment of the present application also provides a computer device, comprising a display screen, a memory, a processor and a computer program, wherein the memory stores the computer program, and the computer program is executed by the processor to enable the processor to execute the steps of the PCIe verification IP automatic integration method supporting multiple working modes, and the PCIe verification IP automatic integration method supporting multiple working modes comprises the following steps of:

[0130] The configurable configuration file is provided, and the customized configuration file is determined.

[0131] The template file is rendered by the python-based template engine jinja2 of the automatic verification generation platform, and the template file is filled as a verification test platform file finally output according to parameters of the configuration file.

[0132] The connection relationship between the PCIe verification IP and the DUT at the PIPE level and the SerDes interface level is automatically completed, and the user can switch the SerDes interface simulation and the PIPE level simulation through parameters in a Makefile.

[0133] The PCIe VIP task library is automatically generated, and a basic task library is provided for the user to verify a basic transmission path and a PCIe protocol.

[0134] It can be understood that, in the preferred embodiment provided by the present application, the computer device can also be a notebook computer, a personal digital assistant (PDA), a mobile phone or other devices that can communicate.

[0135] The embodiment of the present application also provides a readable storage medium, wherein the readable storage medium stores a computer program, and the computer program is executed by a processor to enable the processor to execute the steps of the PCIe verification IP automatic integration method supporting multiple working modes, and the PCIe verification IP automatic integration method supporting multiple working modes comprises the following steps of:

[0136] The configurable configuration file is provided, and the customized configuration file is determined.

[0137] The template file is rendered by the python-based template engine jinja2 of the automatic verification generation platform, and the template file is filled as a verification test platform file finally output according to parameters of the configuration file.

[0138] The connection between the PCIe verification IP and the DUT at the PIPE level and the SerDes interface level is automatically completed, and the user can switch the SerDes interface level simulation and the PIPE level simulation through the parameters in the Makefile;

[0139] The PCIe VIP task library is automatically generated, and a basic task library is provided for the user to verify the basic transmission path and the PCIe protocol.

[0140] For example, the computer program can be divided into one or more modules, one or more modules are stored in the memory and executed by the processor to complete the present application. One or more modules can be a series of computer program instruction segments capable of completing a specific function, which are used to describe the execution process of the computer program in the terminal device. For example, the above-mentioned computer program can be divided into the units or modules of the configurable PCIe verification IP automatic integration system supporting multiple working modes provided by the above-mentioned various system embodiments.

[0141] Those skilled in the art can understand that the above description of the terminal device is only an example and does not constitute a limitation on the terminal device, which can include more or less components than the above description, or combine certain components or different components, for example, can include input and output devices, network access devices, buses, etc.

[0142] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSP), application specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The above processor is the control center of the terminal device, which connects all parts of the terminal device through various interfaces and lines.

[0143] The memory can be used to store computer programs and / or modules, and the processor realizes various functions of the terminal device by running or executing the computer programs and / or modules stored in the memory and calling data stored in the memory. The memory can mainly include a program storage area and a data storage area, wherein the program storage area can store an operating system, at least one application program (such as an information collection template display function, a product information publishing function, etc.) required by a function, etc.; and the data storage area can store data (such as product information collection templates corresponding to different product categories, product information to be published by different product providers, etc.) created according to the use of the PCIe verification IP automatic integration state display system supporting multiple working modes. In addition, the memory can include a high-speed random access memory, and can also include a non-volatile memory, for example, a hard disk, a memory, a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, at least one disk storage device, a flash memory device, or other volatile solid-state storage devices.

[0144] In comparison, the conventional verification platform automatic generation method only generates a universal verification test platform, and does not automatically integrate the PCIe VIP in the verification platform according to the requirements of a project; the present application aims to provide a verification platform method automatic generation method, so that the PCIe VIP can be automatically integrated in the verification platform through simple and clear parameters, greatly reducing the time for building a platform in front-end verification, enabling verification engineers to focus more on protocol and function verification, while avoiding time waste caused by unexpected human errors; a general working mode analysis method is provided, greatly increasing the configurable diversity of the working mode, making the entire verification test platform more reusable; PIPE-level simulation and Serdes-level simulation modes are provided, and users can automatically switch between the two modes using Makefile; the PIPE-level simulation uses PHY BFM for simulation, greatly improving the simulation speed and debugging efficiency, and is used for initial development in front-end verification; the Serdes-level simulation uses the behavioral description level code of the PHY, is closer to the real chip, and is more suitable for regression testing in the later stage of front-end verification; the combination of the two can better meet the different stages of front-end verification; a basic task library is provided, avoiding repeated development of the same function task by different verification engineers, and providing a basic method for PCIe basic channel verification.

[0145] The application adopts a string Split mode to standardize the configuration file of the processing mode, greatly increases the configurable diversity of the processing mode, and makes the whole verification test platform more reusable. The application adopts a PCIe PIPE and Serdes combined mode to automatically generate a verification test platform, and adapts to different stages of front-end verification. The application automatically integrates PCIe VIP, provides a set of basic task library, avoids repeated development of different verification engineers on the same function task, and also provides a basic method for PCIe basic path verification.

[0146] The above is the exemplary embodiment disclosed by the application, but it should be noted that various changes and modifications can be made without departing from the scope of the embodiments disclosed by the application defined by the claims. The functions, steps and / or actions of the method claims described herein need not be performed in any particular order. Furthermore, although the elements of the embodiments disclosed by the application can be described or claimed in individual form or in a singular way, they can also be understood as a plurality unless explicitly limited as singular.

[0147] It should be understood that, as used herein, the singular forms "a", "an" and "the" are intended to include plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", as used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. The above-mentioned embodiment serial numbers of the embodiments disclosed by the application are only for description, and do not represent the advantages or disadvantages of the embodiments.

[0148] Those skilled in the art should understand that the above discussion of any embodiment is only exemplary and is not intended to imply that the scope of the embodiments disclosed by the application (including claims) is limited to these examples; the technical features of the above embodiments or different embodiments can also be combined, and there are many other changes of the above aspects of the embodiments disclosed by the application. In order to be brief, they are not provided in detail. Therefore, any omissions, modifications, equivalent replacements, improvements, etc. made in the spirit and principles of the embodiments disclosed by the application shall be included in the scope of protection of the embodiments disclosed by the application.

Claims

1. A configurable method for automatic integration of PCIe verification IPs supporting multiple working modes, characterized in that: The configurable PCIe authentication IP automatic integration method that supports multiple working modes includes the following steps: Provides configurable configuration files to define custom configuration files, which include: users determining the basic parameters of the PCIe verification IP through configuration parameters; completing the automated integration of the PCIe verification IP into the verification test platform; generating a configuration file for the working mode; and users defining the working mode used in the simulation based on this configuration file. The automated verification generation platform uses the Python template engine Jinja2 to render template files and fills them with parameters from the configuration file to create the final output verification test platform file. Automatically completes the connection relationship between the PCIe verification IP and DUT at both the PIPE level and the SerDes interface level. Users can switch between SerDes interface level simulation and PIPE level simulation at will through parameters in the Makefile. Automatically generate a PCIe VIP task library, providing users with a basic task library for basic transmission path and PCIe protocol verification.

2. The configurable PCIe authentication IP automatic integration method supporting multiple working modes according to claim 1, characterized in that, The custom configuration file is defined through a configuration file definition module, which includes: The project name definition unit, specified by projName, will determine the folder name when the verification test platform is generated; The absolute path determination unit specifies the absolute path of the top-level file of the design under test through the dut.

3. The configurable PCIe authentication IP automatic integration method supporting multiple working modes according to any one of claims 1 to 2, characterized in that, The automated verification generation platform uses the Python template engine Jinja2 to render template files. It employs a method to fill in the template file with parameters from the configuration file to create the final output verification test platform file. Specifically, this includes: Add the instantiation of PCIe VIP PIPE to the top-level template file of the verification test platform, and determine the number of PIPEs to be instantiated based on the number of channels in the configuration file; It is passed to the base_test component through the uvm_config_db function provided by UVM; Generate a configuration file for selecting the working mode under the simulation execution path; The PCIe VIP configuration template file is created by parsing the configuration file of the working mode through the string split function, and the parsed result is passed to the base_test component through the uvm_config_db function provided by UVM. Add compilation of the PCIe VIP source code to the Makefile template file, add a PIPE-level simulation mode selection switch and corresponding macro definitions.

4. The configurable PCIe authentication IP automatic integration method supporting multiple working modes according to claim 3, characterized in that, The creation of the PCIe VIP configuration template file involves parsing the configuration file for the working mode using the string split function, and then passing the parsed result to the base_test component via the uvm_config_db function provided by UVM. Specifically, this includes: Create string arrays of initial PCIe VIP groups for EP and RC based on user-defined configuration files. The string array for EP stores the group_name of all VIPs of type EP to be integrated in the user configuration file, and the string array for RC stores the group_name of all VIPs of type RC to be integrated in the user configuration file. Read the configuration file for the selected working mode line by line; If the name of the PCIe group in each row is in the string array of the PCIe VIP group initialized in EP / RC, then the working mode selection information is separated by the string "x" using the implemented string split function to obtain the number of VIPs m and the number of channels n for each VIP. The repeat function is used to repeat m times and put n into the corresponding EP / RC result queue. Otherwise, a report is made using the uvm_error method provided by UVM, and no further processing is performed. The EP / RC result queue is passed to the base_test component via the config_db function provided by UVM.

5. The configurable PCIe authentication IP automatic integration method supporting multiple working modes according to claim 4, characterized in that, The automated verification generation platform uses the Python template engine Jinja2 to render template files. It further includes a method for filling in the template file with parameters from the configuration file to create the final output verification test platform file. Add the instantiation of the PCIe VIP and the distribution of PIPE to the PCIe base test template file.

6. The configurable PCIe authentication IP automatic integration method supporting multiple working modes according to claim 5, characterized in that, The method for adding PCIe VIP instantiation and PIPE distribution to the PCIe base test template file includes: The result queue of EP and RC passed from the PCIe VIP configuration is obtained through the config_db function in UVM; Based on the size of the EP and RC result queues, complete the space allocation for the EP BFM dynamic array and the RC BFM dynamic array, and instantiate each BFM. By performing a POP operation from the resulting EP and RC queues, the number of channels obtained is used for PIPE allocation, and the corresponding number of PIPEs are allocated to the PCIe VIP BFM in sequence. Configure the PCIe VIP to start BFM.

7. The configurable PCIe authentication IP automatic integration method supporting multiple working modes according to claim 6, characterized in that, The automatically generated PCIe VIP task library provides users with a basic task library for verifying basic transmission paths and the PCIe protocol, specifically including: Define a PCIe VIP task library template; The basic task of joining the PCIe protocol; The defined task library is included in the template file of test_pkg, so that all current test cases and subsequent derived test cases can use the tasks in the task library, avoiding the duplication of development of the same functional tasks by different verification engineers.

8. A configurable PCIe authentication IP automatic integration system supporting multiple working modes, characterized in that, The configurable PCIe authentication IP automatic integration system that supports multiple working modes specifically includes: The configuration file provider module is used to provide configurable configuration files and determine custom configuration files; An automated verification generation platform, which uses the Python template engine Jinja2 to render template files and fills in the template files with parameters from the configuration file to form the final output verification test platform file; The PCIe verification module is used to automatically complete the connection relationship between the PCIe verification IP and the DUT at both the PIPE level and the SerDes interface level. Users can switch between SerDes interface-level simulation and PIPE-level simulation at will through the parameters in the Makefile. The task library generation module is used to automatically generate a PCIe VIP task library, providing users with a basic task library for basic transmission paths and PCIe protocol verification. The configuration file providing module includes: The parameter determination unit allows users to determine the basic parameters of the PCIe verification IP through clear and explicit configuration parameters; The platform integration unit is used to automate the integration of PCIe verification IPs into the verification test platform. The configuration file generation unit is used to generate configuration files for the working mode; The mode simulation unit allows users to define the working mode used in the simulation based on this configuration file.

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