Covergroup generation method, device, equipment and medium in integrated circuit verification environment

Abstract

The present disclosure provides a method, apparatus, device and medium for generating a cover group in an integrated circuit verification environment, and relates to the field of computer technology, and in particular to the field of chip testing. The specific implementation scheme is as follows: parsing the instruction set file that matches the integrated circuit verification environment to be tested, and obtaining the instruction description information of each instruction in the instruction set file; wherein the instruction set file includes the definition of each data bit in each instruction, and the instruction description information includes at least one of the instruction type, static data in the instruction, at least one dynamic data in the instruction and the instruction function description information; based on the instruction description information of each instruction, generating a single instruction cover group that matches each instruction respectively. The technical solution disclosed in the present disclosure can automatically generate a cover group in an integrated circuit verification environment, thereby improving the accuracy and generation efficiency of the cover group.

Description

Technical Field

[0001] The present disclosure relates to computer technology, in particular to chip testing technology, and specifically to a method, apparatus, device, and medium for generating a cover group in an integrated circuit verification environment. Background Art

[0002] Because processor instruction sets contain a large number of instructions and their definitions are similar, integrated circuit verification requires recording and managing the instructions in the instruction set in a table format and collecting functional coverage for the instructions in the instruction set. This can be achieved, for example, by establishing cover groups using System Verilog (SV) syntax.

[0003] The existing technology usually requires manual filling in one or more of the following information in a table based on the coverage point requirements within the coverage group: the name of the coverage point or combined coverage point, the name of the variable to be collected, the name of the collection to be combined, the collection conditions, and the information used to generate the warehouse, in order to generate the coverage group.

[0004] However, with such a large number of instruction sets, manually writing covergroups is tedious, time-consuming, and prone to omissions. Therefore, how to automatically generate covergroups in an integrated circuit verification environment and improve their accuracy and efficiency is an urgent problem to be solved. Summary of the Invention

[0005] The present disclosure provides a method, apparatus, device, and medium for generating a cover group in an integrated circuit verification environment.

[0006] According to one aspect of the present disclosure, a method for generating a covergroup in an integrated circuit verification environment is provided, comprising:

[0007] Parsing an instruction set file that matches the verification environment of the integrated circuit to be tested, and obtaining instruction description information of each instruction in the instruction set file;

[0008] The instruction set file includes a definition of each data bit in each instruction, and the instruction description information includes at least one of the instruction type, static data in the instruction, at least one dynamic data in the instruction, and instruction function description information;

[0009] According to the instruction description information of each instruction, a single instruction cover group matching each instruction is generated.

[0010] According to another aspect of the present disclosure, there is provided an electronic device, comprising:

[0011] at least one processor; and

[0012] a memory communicatively connected to the at least one processor; wherein,

[0013] The memory stores instructions that can be executed by the at least one processor. The instructions are executed by the at least one processor to enable the at least one processor to perform the method described in any embodiment of the present disclosure.

[0014] According to another aspect of the present disclosure, a non-transitory computer-readable storage medium storing computer instructions is provided, wherein the computer instructions are used to enable a computer to execute the method described in any embodiment of the present disclosure.

[0015] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present disclosure, nor are they intended to limit the scope of the present disclosure. Other features of the present disclosure will become readily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are provided to facilitate a better understanding of the present invention and do not constitute a limitation of the present disclosure.

[0017] Figure 1 is a flowchart of a method for generating a cover group in an integrated circuit verification environment according to an embodiment of the present disclosure;

[0018] Figure 2 is a flowchart of another method for generating a cover group in an integrated circuit verification environment according to an embodiment of the present disclosure;

[0019] Figure 3 is a flowchart of another method for generating a cover group in an integrated circuit verification environment according to an embodiment of the present disclosure;

[0020] Figure 4 A schematic structural diagram of a cover group generation device in an integrated circuit verification environment according to an embodiment of the present disclosure;

[0021] Figure 5 The present invention is a block diagram of an electronic device for implementing the method for generating a cover group in an integrated circuit verification environment according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0022] The following description of exemplary embodiments of the present disclosure is made in conjunction with the accompanying drawings, including various details of the embodiments of the present disclosure to facilitate understanding. These details should be considered as merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications may be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Similarly, for the sake of clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0023] Figure 1This is a flowchart of a method for generating covergroups in an integrated circuit verification environment, according to an embodiment of the present disclosure. This embodiment of the present disclosure is applicable to the automatic generation of covergroups in an integrated circuit verification environment, improving the accuracy and efficiency of covergroup generation. This method can be performed by a covergroup generation device in an integrated circuit verification environment. This device can be implemented in hardware and / or software and can generally be integrated into an electronic device.

[0024] like Figure 1 As shown, a method for generating a cover group in an integrated circuit verification environment provided by an embodiment of the present disclosure includes the following specific steps:

[0025] S110: Parse the instruction set file that matches the verification environment of the integrated circuit to be tested, and obtain instruction description information of each instruction in the instruction set file.

[0026] The instruction set file includes the definition of each data bit in each instruction, and the instruction description information includes at least one item of the instruction type, static data in the instruction, at least one dynamic data in the instruction, and instruction function description information.

[0027] The instruction set file may refer to a table file containing the data bits of each instruction in the integrated circuit under test. Typically, an instruction set file may contain instruction description information for multiple instructions. The instruction description information may refer to information describing the instruction, and may include, for example, at least one of the following: the instruction type, static data in the instruction, at least one dynamic data in the instruction, and instruction function description information.

[0028] The instruction type may refer to the execution function of the instruction, and for example, may be addition, subtraction, multiplication, or division. The instruction type corresponding to an instruction can usually be known based on the instruction name. For example, if the instruction name is "demoadd," it can be known that the instruction type corresponding to the instruction is the addition operation "add."

[0029] Static data refers to data used primarily for control or reference purposes during operation. It remains constant over long periods of time and generally does not change with operation. In the context of verifying an integrated circuit under test, static data often serves as an identifier.

[0030] Dynamic data refers to data that changes during operation and data that needs to be input or output during operation. In the verification environment of the integrated circuit under test, dynamic data can usually be used for transmission or calculation.

[0031] Generally speaking, each instruction can be composed of fixed-length data bits (for example, 16 bits or 32 bits, etc.). By specifying the definition of each data bit in each instruction in the instruction set file, it can be clearly determined which data bits in each instruction correspond to static data and which data bits correspond to dynamic data.

[0032] For example, if the instruction set file defines that data bits [0:6] of instruction A correspond to a register RT, then data bits [0:6] of instruction A correspond to dynamic data, which is the data value currently stored in register RT. If data bits [32-27] of instruction B correspond to a set data 1, then data bits [32-27] of instruction B correspond to the static data 000001.

[0033] The instruction function description information may refer to information that describes in detail the execution environment of the instruction, or information that describes in detail the format of dynamic data in the instruction.

[0034] It is worth noting that the instruction set file in the embodiment of the present disclosure is provided and maintained by the designers, and is unique during the development process of the integrated circuit. There is no need for additional cross-team maintenance of the consistency of the instruction set file, which improves the efficiency of the verification work and avoids the risks of omissions and dislocations caused by manual consistency checks.

[0035] S120 . Generate a single instruction cover group matching each instruction according to the instruction description information of each instruction.

[0036] A covergroup can refer to a class that contains multiple sampled data. A covergroup can include the type of sampled data, the range of sampled data, and the conditions that the sampled data meets. A single-instruction covergroup can refer to a class that aggregates the sampled data from a single instruction.

[0037] After obtaining the static data, dynamic data and instruction function description information of each instruction, the coverage points in each single instruction coverage group, as well as the coverage conditions and coverage layers corresponding to each coverage point, can be automatically set based on the above information to achieve the effect of automatically constructing the coverage group.

[0038] Therefore, after generating a corresponding single instruction coverage group for each instruction, data scanning can be performed according to the single instruction coverage group to generate a corresponding SV coverage file, thereby realizing the calculation of the SV coverage of the instruction set in the integrated circuit.

[0039] The technical solution of the embodiment of the present disclosure parses the instruction set file that matches the verification environment of the integrated circuit to be tested to obtain the instruction description information of each instruction in the instruction set file; and generates a single instruction cover group that matches each instruction based on the instruction description information of each instruction. The cover group in the integrated circuit verification environment can be automatically generated, thereby improving the accuracy and generation efficiency of the cover group.

[0040] Figure 2This is a flowchart of another method for generating a cover group in an integrated circuit verification environment according to an embodiment of the present disclosure. The embodiment of the present disclosure is refined based on the above-mentioned embodiment. In this embodiment, the operation of generating a single instruction cover group that matches each instruction is specifically implemented as follows: obtaining the target instruction currently being processed, and creating a target single instruction cover group corresponding to the target instruction according to the instruction type of the target instruction; creating a first type of cover point corresponding to each dynamic data in the target instruction in the target single instruction cover group; setting the coverage condition of each first type of cover point according to the static data in the target instruction; and setting the coverage bin of each first type of cover point according to the instruction type or instruction function description information of the target instruction.

[0041] like Figure 2 As shown, a method for generating a cover group in an integrated circuit verification environment provided by an embodiment of the present disclosure includes the following specific steps:

[0042] S210: If the file format of the instruction set file is a table, read cells in the instruction set file in units of rows.

[0043] Among them, a cell may refer to the intersection of a row and a column in an instruction set file, which is the smallest unit constituting the instruction set file and is used to record instruction description information of each instruction.

[0044] The instruction description information may include at least one of the instruction type, static data in the instruction, at least one dynamic data in the instruction, and instruction function description information.

[0045] It is worth noting that reading cells can usually be implemented using an open source library. For example, in the embodiment of the present disclosure, the openpyxl open source library can be used to read the table.

[0046] Based on the above embodiment, when reading cells in the instruction set file line by line, the text in the cell can also be matched through the open source regular expression library (regular expression, re), according to the particularity of the instruction format, such as English string + space + English string + English comma, to avoid non-instruction description line information, thereby improving the accuracy of the coverage group.

[0047] S220. When an empty type cell is read, determine whether the empty type cell belongs to a merged cell; if so, execute S230; if not, execute S250.

[0048] The empty type cell may refer to a cell that does not store data or does not undergo type conversion. The merged cell may refer to a cell formed by merging two or more cells in the same row or column.

[0049] It is worth noting that for merged cells, the script will record the boundaries of the merged cells, so that it can promptly determine whether the empty type cell belongs to the merged cell.

[0050] S230 , obtaining the left border cell corresponding to the merged cell, and reading the data content in the left border cell, and executing S240 .

[0051] The left border cell may refer to the leftmost cell when a merged cell is formed. Usually, after cells are merged, the merged result is stored in the left border cell.

[0052] S240 , performing attribute name splicing along the attribute names of the left border cells toward the attribute names of the empty type cells, and using the read data content as the attribute value of the attribute name splicing result.

[0053] The attribute name can refer to the representative name of each cell. Usually, a row of cells or a column of cells can share the same attribute name. The attribute name concatenation result can refer to the attribute name corresponding to the merged cells.

[0054] Specifically, after reading the data content in the left border cell, the empty type cell adjacent to the left border cell in the merged cell is obtained according to the attribute name naming direction of the empty type cell. The attribute name of the left border cell is then spliced ​​with the attribute name of the empty type cell until all the empty type cells that make up the merged cell are spliced. The splicing result is recorded as the attribute name splicing result, and the data content in the left border cell is used as the attribute value of the attribute name splicing result. In this way, the accuracy of the data read in the merged cell can be guaranteed.

[0055] For example, as shown in Table 1, there are merged cells. Since cell [6:2] is merged with cell [1:0], when cell [1:0] is read, it can be identified as an empty type cell and belongs to a merged cell. Then, the left border cell [6:2] corresponding to the merged cell is obtained, and the data content 0 in the left border cell [6:2] is read. Furthermore, the attribute name is spliced ​​along the attribute name [6:2] of the left border cell toward the attribute name [1:0] of the empty type cell to obtain the attribute name splicing result Data0, and the data content 0 in the left border cell [6:2] is used as the attribute value of the attribute name splicing result Data0. In this way, the attribute value of the attribute name splicing result is obtained.

[0056] Table 1 Merge cells

[0057]

[0058] S250 , obtaining a target instruction currently being processed, and creating a target single instruction cover group corresponding to the target instruction according to the instruction type of the target instruction.

[0059] The target instruction may refer to an instruction that currently needs to be covered, and the target single instruction covergroup may refer to a covergroup corresponding to the target instruction.

[0060] Specifically, if the type of the target instruction is "demoswap", the target single instruction cover group can be constructed using the following sentence pattern: covergroup_demoswap.

[0061] S260 , creating first-type cover points corresponding to each dynamic data in the target instruction in the target single instruction cover group.

[0062] A first-class coverpoint can refer to a point used to sample the data value or data change of each dynamic data in the target instruction. Typically, one dynamic data item corresponds to one first-class coverpoint. Furthermore, a target single-instruction covergroup can contain one or more first-class coverpoints.

[0063] In an optional embodiment, after creating first-type cover points corresponding to each dynamic data in the target instruction in the target single instruction cover group, it may also include: if it is determined that register type data exists in each dynamic data in the target instruction, creating second-type cover points corresponding to each register type data; setting the coverage condition of each first-type cover point according to the static data in the target instruction; obtaining the register type corresponding to each register type data; and setting the coverage bin of each second-type cover point according to the bin building rules corresponding to each register type in the default bin building rule set.

[0064] Register type data may refer to data that needs to be stored and read from a register. A second type of coverpoint may refer to a point used to sample dynamic data stored in a register. A coverage condition may refer to the rule conditions used to select a coverpoint. A coverage bin may refer to the data range used to determine a coverpoint. A bin building rule may refer to the rules used to construct a coverage bin.

[0065] Among them, the default bin building rule set can refer to a bin building rule that adopts a full collection type, that is, a coverage bin is established one by one for the dynamic data bits from the minimum value 0 to the maximum value to achieve all possible coverage collection. For example, if the maximum value of the dynamic data is 31, a coverage bin can be established by bins b_rs[] = {[0:31]}. It is worth noting that the bit width of each dynamic data bit in the target instruction is fixed, so the dynamic data maximum value of the data bit can be determined.

[0066] Among them, the coverage bin of the second-type cover point can refer to the data range or data type for judging the second-type cover points in the register. For example, if the register contains data of int8, int32 and float32 types, the coverage bin of the second-type cover point can be set to int8, and only the second-type cover points with data type int8 will be judged.

[0067] Therefore, when determining that register type data exists in each dynamic data in the target instruction, by setting the second type of cover points and the cover bins of the second type of cover points, the accuracy of the cover group can be guaranteed to a great extent, and the impact of dynamic data outside the cover bins of the second type of cover points on the final coverage rate can be reduced.

[0068] S270 : Set a coverage condition for each first-type cover point according to the static data in the target instruction.

[0069] Specifically, for the static data in the target instruction, the data bits of each static data may be recorded as distinguishing marks; and then, the coverage condition of each first-category coverage point may be set according to each distinguishing mark.

[0070] For example, the conditional judgment expression iff may be used to judge the data bits of the static data to achieve the coverage condition of the first type of cover point.

[0071] Therefore, when the static data identification bit matches successfully, it proves that the first type of coverage point meets the coverage conditions, ensuring the accuracy of the sampling data.

[0072] S280: Set a coverage bin for each first-category coverage point according to the instruction type or instruction function description information of the target instruction.

[0073] The coverage bin of the first type of coverage points may refer to a data range for judging the first type of coverage points corresponding to the dynamic data.

[0074] In an optional embodiment, a coverage bin for each first-category coverage point is set according to the instruction type or instruction function description information of the target instruction, including: obtaining the target first-category coverage point currently being processed; and obtaining the target dynamic data corresponding to the target first-category coverage point; detecting whether there is a target data type corresponding to the target dynamic data in the instruction function description information of the target instruction; if so, setting the coverage bin for the target first-category coverage point according to the bin building rules corresponding to the target data type; if not, setting the coverage bin for the target first-category coverage point according to the bin building rules corresponding to the instruction type of the target instruction in the default bin building rule set.

[0075] The target data type may refer to the data type of the target dynamic data, and may be, for example, a signed number, an unsigned number, or a one-hot value, etc. The target first-class cover point may refer to the first-class cover point corresponding to the target dynamic data.

[0076] Specifically, when the target data type corresponding to the target dynamic data in the instruction function description information is an unsigned number, the bin building rule can use the unsigned number boundary value collection, that is, the dynamic data bit width is large, the amount of data to be collected is large, and there is no need to pay attention to the data type of all numerical traversal requirements, only the boundary values ​​need to be built. For example, the coverage bin of each first-class coverage point can be set by bins b_imm[] = {0, 1, 254, 255}. When the target data type corresponding to the target dynamic data in the instruction function description information is a signed number, the bin building rule can use the signed number boundary value collection, that is, but the positive boundary values, negative boundary values, 0, and ±1 will be collected. For example, the coverage bin of each first-class coverage point can be set by bins b_imm[] = {0, 1, 126, 127, 128, 254, 255}. When the target data type corresponding to the target dynamic data in the instruction function description is a unique hot value, the bin building rule can use unique hot value coverpoint collection. That is, each target dynamic data only has one 1. For example, the cover bins of each first-class cover point can be set as bins b_md = {1, 2, 4, 8}. This allows matching the corresponding bin building rule for each type of dynamic data, ensuring the accuracy of the cover group.

[0077] The technical solution of the embodiment of the present disclosure is to read cells in units of rows from an instruction set file in a table format, and when reading an empty type cell, determine whether the empty type cell belongs to a merged cell; if so, obtain the left boundary cell corresponding to the merged cell, and read the data content in the left boundary cell; perform attribute name splicing along the attribute name of the left boundary cell toward the attribute name of the empty type cell, and use the read data content as the attribute value of the attribute name splicing result; then, obtain the target instruction currently being processed, and create a target single instruction cover group corresponding to the target instruction according to the instruction type of the target instruction, and create first-class cover points corresponding to each dynamic data in the target instruction in the target single instruction cover group; set the coverage condition of each first-class cover point according to the static data in the target instruction; finally, set the coverage bin of each first-class cover point according to the instruction type or instruction function description information of the target instruction, so as to automatically generate the cover group in the integrated circuit verification environment, thereby improving the accuracy and generation efficiency of the cover group.

[0078] On the basis of the above embodiments, after setting the coverage bin of each first-category coverage point according to the instruction type or instruction function description information of the target instruction, it may also include: creating a cross coverage point corresponding to all the first-category coverage points in the target single instruction coverage group.

[0079] Among them, the cross cover point can refer to the cover point formed by cross-combining the various cover points in the same cover group. Exemplarily, it can be achieved through cross. Specifically, if all the first-class cover points in the target single instruction cover group are imm, md, mrs, rs and vrd, then cmd_cross:crossimm,md,mrs,rs,vrd can be used to create a cross cover point corresponding to all the first-class cover points. In this way, the complete coverage of the target instruction can be fully represented.

[0080] Optionally, in the target single instruction cover group, cross-cover points corresponding to all the first-category cover points are created, including: in the target single instruction cover group, cross-cover points corresponding to all the first-category cover points are created using macro definitions; wherein the macro definitions include macro switch parameters, and the macro switch parameters are used to set whether to cover or not cover the cross-cover points.

[0081] The macro definition can encompass crossimm operations and determine whether to enable crossimm operations during simulation. For example, the macro definition can be implemented using `ifdef FCOV_STAGE_1_demo_cmd_:crossimm,md,mrs,rs,vrd;`endif . A value of 1 indicates enabling crossimm operations, while a value of 0 indicates disabling crossimm operations.

[0082] In this way, the impact of a large coverage bin on the speed of integrated circuit verification during cross-combination operations can be avoided.

[0083] Figure 3 This is a flowchart of another method for generating a cover group in an integrated circuit verification environment provided according to an embodiment of the present disclosure; the embodiment of the present disclosure is supplemented on the basis of the above-mentioned disclosed embodiment. In this embodiment, the specific additions are: creating a combined cover group; combining all instructions in the instruction set file in pairs to obtain multiple instruction groups; and creating a combined cover point corresponding to each instruction group in the combined cover group based on the instruction description information of the two instructions in each instruction group.

[0084] like Figure 3 As shown, a method for generating a cover group in an integrated circuit verification environment provided by an embodiment of the present disclosure includes the following specific steps:

[0085] S310: If the file format of the instruction set file is a table, read cells in the instruction set file in units of rows.

[0086] S320. When an empty type cell is read, determine whether the empty type cell belongs to a merged cell; if so, execute S330; if not, execute S350.

[0087] S330 , obtaining the left border cell corresponding to the merged cell, and reading the data content in the left border cell, and executing S340 .

[0088] S340: Attribute names are spliced ​​along the attribute names of the left border cells toward the attribute names of the empty type cells, and the read data content is used as the attribute value of the attribute name splicing result.

[0089] S350 . Generate a single instruction cover group that matches each instruction according to the instruction description information of each instruction.

[0090] S360. Create a combined coverage group.

[0091] The combined cover group may refer to a cover group obtained by combining all instructions in the instruction set file in pairs.

[0092] In an optional embodiment, after creating the combined cover group, it may also include: generating at least one of an unreasonable bin and an ignored bin according to a preset invalid instruction combination entry; and adding at least one of the unreasonable bin and the ignored bin to the combined cover group.

[0093] Among them, unreasonable bins can refer to data judgment rules established to avoid unreasonable instruction combinations. For example, once such instruction combinations are sampled in the simulation, the simulation software will issue an error message reminder according to the simulation parameter requirements. Exemplarily, an unreasonable bin can be established through illegal_bins. For example, if the combination of last_cmd and this_cmd is an unreasonable instruction combination, an unreasonable bin of the form illegal_bins_demo_2_exit_=binsof(last_cmd._demo_)&&binsof(this_cmd._exit_) can be generated. Ignore bins can refer to instruction combinations that do not need to be verified. Exemplarily, ignore bins can be established through ignore_bins. The invalid instruction combination entry includes one or more invalid instruction combinations, and each invalid instruction combination includes two unreasonable instruction combinations. Among them, the invalid instruction combination entry can be collected by the tester, or obtained by the simulation software through actual measured data statistics, and this embodiment does not limit this.

[0094] Therefore, by adding at least one of the unreasonable bins and the ignored bins to the combined cover group, unreasonable instruction combinations or negligible instruction combinations can be effectively avoided, thereby ensuring the accuracy of the cover group.

[0095] S370: Combine all instructions in the instruction set file in pairs to obtain multiple instruction groups.

[0096] Specifically, all instructions in the instruction set are obtained, and all instructions are combined in pairs to obtain an instruction group consisting of two different instructions.

[0097] S380: Create, in the combined cover group, combined cover points corresponding to each of the instruction groups according to the instruction description information of the two instructions in each of the instruction groups.

[0098] The combined coverpoints may refer to the coverpoints corresponding to each instruction group.

[0099] In an optional embodiment, based on the instruction description information of the two instructions in each instruction group, a combined cover point corresponding to each instruction group is created in the combined cover group, including: obtaining the first instruction and the second instruction in the target instruction group currently being processed; creating a first combined cover point and a second combined cover point corresponding to the first instruction and the second instruction respectively in the combined cover group; generating a first wildcard representation corresponding to the first instruction based on the static data and at least one dynamic data in the first instruction, and setting a first cover bin corresponding to the first combined cover point based on the first wildcard representation; generating a second wildcard representation corresponding to the second instruction based on the static data and at least one dynamic data in the second instruction, and setting a second cover bin corresponding to the second combined cover point based on the second wildcard representation.

[0100] Among them, the target instruction group may refer to the instruction group that currently needs to be verified. The first instruction and the second instruction may refer to a combination instruction generated according to the sequence of the two instructions in the target instruction group. For example, if the target instruction group contains two instructions, demoadd and demosub, the first instruction may be a combination instruction with demoadd first and demosub second; similarly, the second instruction may be a combination instruction with demosub first and demoadd second. The first combination coverpoint and the second combination coverpoint may refer to the coverpoints corresponding to the first instruction and the second instruction, respectively.

[0101] The first wildcard and the second wildcard may generally refer to symbols used in the first instruction and the second instruction for fuzzy searching data, and may generally be represented by an asterisk or a question mark. In the embodiment of the present disclosure, a question mark may be selected as the first wildcard and the second wildcard. Generally, the positions of the first wildcard and the second wildcard may be the same.

[0102] The first covering bin and the second covering bin may refer to covering bins with wildcard definitions established for dynamic data using wildcards.

[0103] Specifically, taking the target instruction group including the two instructions demoadd and demosub as an example, the first cover bin corresponding to the first combined cover point can be set according to the first instruction (demoadd comes first, demosub comes second): demo_command:coverpointthis_cmd{wildcardbins_demoadd_={32'b0000111?????????000????0000011};wildcardbins_demosub_={32'b0000111????????001?????} 0000011}; / / …};Similarly, the second cover bin corresponding to the second combined cover point can be set according to the second instruction (demosub first, demoadd later): demo_command:coverpointlast_cmd{wildcard bins_demosub_={32'b0000111?????????001?????0000011};wildcard bins_demoadd_={32'b0000111?????????000????0000011}; / / …}. In this way, the creation of the combined cover point can be effectively implemented.

[0104] In another optional embodiment, after setting the second coverage bin corresponding to the second combined cover point according to the second wildcard representation, the method further includes: creating a cross coverage point corresponding to both the first combined cover point and the second combined cover point in the combined cover group.

[0105] Specifically, the cross cover point can be established by cross-combining the first combined cover point and the second combined cover point. For example, the cross cover point corresponding to the first combined cover point and the second combined cover point can be created by cmd_cross:cross this_cmd,last_cmd. This ensures the accuracy of the combined cover group.

[0106] The technical solution of the embodiment of the present disclosure is to read cells in units of rows from an instruction set file in a table format, and when reading an empty type cell, determine whether the empty type cell belongs to a merged cell; if so, obtain the left boundary cell corresponding to the merged cell, and read the data content in the left boundary cell; splice the attribute names along the attribute name of the left boundary cell toward the attribute name of the empty type cell, and use the read data content as the attribute value of the attribute name splicing result; then, based on the instruction description information of each instruction, generate a single instruction cover group that matches each instruction respectively, and create a combined cover group; combine all instructions in the instruction set file in pairs to obtain multiple instruction groups; finally, based on the instruction description information of the two instructions in each instruction group, create a combined cover point corresponding to each instruction group in the combined cover group, so that single instruction cover groups and combined cover groups in the integrated circuit verification environment can be automatically generated, thereby improving the accuracy and generation efficiency of the cover group.

[0107] As an implementation of the above-mentioned covergroup generation method in each integrated circuit verification environment, the present disclosure also provides an optional embodiment of an execution device for implementing the above-mentioned covergroup generation method in each integrated circuit verification environment.

[0108] Figure 4 FIG. 1 is a schematic structural diagram of a cover group generating device in an integrated circuit verification environment according to an embodiment of the present disclosure; FIG. Figure 4 As shown, the cover group generating device in the integrated circuit verification environment includes: a data parsing module 410 and a single instruction cover group generating module 420;

[0109] The data parsing module 410 is configured to parse an instruction set file that matches the verification environment of the integrated circuit under test, and obtain instruction description information for each instruction in the instruction set file; wherein the instruction set file includes a definition of each data bit in each instruction, and the instruction description information includes at least one of an instruction type, static data in the instruction, at least one dynamic data in the instruction, and instruction function description information;

[0110] The single instruction cover group generating module 420 is configured to generate a single instruction cover group matching each instruction according to the instruction description information of each instruction.

[0111] The technical solution of the embodiment of the present disclosure parses the instruction set file that matches the verification environment of the integrated circuit to be tested to obtain the instruction description information of each instruction in the instruction set file; and generates a single instruction cover group that matches each instruction based on the instruction description information of each instruction. The cover group in the integrated circuit verification environment can be automatically generated, thereby improving the accuracy and generation efficiency of the cover group.

[0112] Optionally, the single instruction cover group generation module 420 may include:

[0113] a single instruction cover group creation unit, configured to obtain a target instruction currently being processed and, based on an instruction type of the target instruction, create a target single instruction cover group corresponding to the target instruction;

[0114] A first-type coverpoint creation unit, configured to create, in the target single instruction covergroup, first-type coverpoints corresponding to each dynamic data in the target instruction;

[0115] a coverage condition setting unit, configured to set a coverage condition for each of the first-category cover points according to static data in the target instruction;

[0116] The first coverage bin setting unit is configured to set a coverage bin for each of the first-category coverage points according to the instruction type or instruction function description information of the target instruction.

[0117] Optionally, the first covering bin setting unit may be specifically used to:

[0118] Acquire a target first-category cover point currently being processed; and acquire target dynamic data corresponding to the target first-category cover point;

[0119] detecting whether there is a target data type corresponding to the target dynamic data in the instruction function description information of the target instruction;

[0120] If yes, then setting the coverage bin of the target first-category coverage point according to the bin building rule corresponding to the target data type;

[0121] If not, the covering warehouse of the target first-category covering point is set according to the covering warehouse rule corresponding to the instruction type of the target instruction in the default covering warehouse rule set.

[0122] Optionally, the covergroup generating apparatus in the integrated circuit verification environment may further include:

[0123] The second coverage bin setting module is used to create first-type coverage points corresponding to each dynamic data in the target instruction in the target single instruction coverage group, and then, if it is determined that register type data exists in each dynamic data in the target instruction, create second-type coverage points corresponding to each register type data; set the coverage condition of each first-type coverage point according to the static data in the target instruction; obtain the register type corresponding to each register type data; and set the coverage bin of each second-type coverage point according to the position building rules corresponding to each register type in the default position building rule set.

[0124] Optionally, the covergroup generating apparatus in the integrated circuit verification environment may further include:

[0125] A cross cover point creation module is configured to create a cross cover point corresponding to all the first type cover points in the target single instruction cover group after setting a cover bin for each first type cover point according to the instruction type or instruction function description information of the target instruction.

[0126] Optional, cross-coverage creation module, specifically used for:

[0127] In the target single instruction covergroup, creating cross coverpoints corresponding to all the first-category coverpoints by using macro definitions;

[0128] The macro definition includes a macro switch parameter, and the macro switch parameter is used to set whether to cover or not cover the cross-coverage point.

[0129] Optionally, the covergroup generating apparatus in the integrated circuit verification environment may further include:

[0130] A combination cover group creation module is used to create a combination cover group; all instructions in the instruction set file are combined in pairs to obtain multiple instruction groups; according to the instruction description information of the two instructions in each instruction group, a combination cover point corresponding to each instruction group is created in the combination cover group.

[0131] Optionally, a combined covergroup creation module can be used to:

[0132] Obtain the first and second instructions in the target instruction group currently being processed;

[0133] In the combined cover group, creating a first combined cover point and a second combined cover point corresponding to the first instruction and the second instruction respectively;

[0134] generating a first wildcard representation corresponding to the first instruction according to static data and at least one dynamic data in the first instruction, and setting a first coverage bin corresponding to the first combined coverage point according to the first wildcard representation;

[0135] A second wildcard representation corresponding to the second instruction is generated according to the static data and at least one dynamic data in the second instruction, and a second coverage bin corresponding to the second combined coverage point is set according to the second wildcard representation.

[0136] Optionally, the covergroup generating apparatus in the integrated circuit verification environment may further include:

[0137] A cross cover point creating module is configured to create a cross cover point corresponding to both the first combined cover point and the second combined cover point in the combined cover group after setting a second cover bin corresponding to the second combined cover point according to the second wildcard representation.

[0138] Optionally, the covergroup generating apparatus in the integrated circuit verification environment may further include:

[0139] The post-processing module is used to generate at least one of an unreasonable bin and an ignored bin according to the preset invalid instruction combination entries after the combination cover group is created; and add at least one of the unreasonable bin and the ignored bin to the combination cover group.

[0140] Optionally, the data parsing module 410 may be used to:

[0141] If the file format of the instruction set file is a table, reading cells in the instruction set file in units of lines;

[0142] When reading an empty type cell, determine whether the empty type cell belongs to a merged cell;

[0143] If so, obtain the left border cell corresponding to the merged cell, and read the data content in the left border cell;

[0144] Attribute names are spliced ​​along the attribute names of the left border cells toward the attribute names of the empty type cells, and the read data content is used as the attribute value of the attribute name splicing result.

[0145] The above-mentioned product can execute the method provided by any embodiment of the present disclosure, and has the corresponding functional modules and beneficial effects of the execution method.

[0146] In the technical solutions disclosed herein, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved comply with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0147] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0148] Figure 5A schematic block diagram of an example electronic device 500 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are provided as examples only and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0149] like Figure 5 As shown, the device 500 includes a computing unit 501, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 502 or a computer program loaded from a storage unit 508 into a random access memory (RAM) 503. Various programs and data required for the operation of the device 500 can also be stored in the RAM 503. The computing unit 501, the ROM 502, and the RAM 503 are connected to each other via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0150] Various components in device 500 are connected to I / O interface 505, including: an input unit 506, such as a keyboard, mouse, etc.; an output unit 507, such as various types of displays, speakers, etc.; a storage unit 508, such as a magnetic disk, optical disk, etc.; and a communication unit 509, such as a network card, modem, wireless communication transceiver, etc. The communication unit 509 allows device 500 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0151] The computing unit 501 can be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 501 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units that run machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 501 performs the various methods and processes described above, such as the cover group generation method in the integrated circuit verification environment. For example, in some embodiments, the cover group generation method in the integrated circuit verification environment can be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 508. In some embodiments, part or all of the computer program can be loaded and / or installed on the device 500 via the ROM 502 and / or the communication unit 509. When the computer program is loaded into the RAM 503 and executed by the computing unit 501, one or more steps of the cover group generation method in the integrated circuit verification environment described above can be performed. Alternatively, in other embodiments, the computing unit 501 may be configured in any other appropriate manner (for example, by means of firmware) to execute the covergroup generation method in the integrated circuit verification environment.

[0152] Various embodiments of the systems and techniques described above can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), system-on-chip systems (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include being implemented in one or more computer programs that are executable and / or interpreted on a programmable system that includes at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0153] The program code for implementing the method of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device so that when the program code is executed by the processor or controller, the functions / operations specified in the flow chart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, as a stand-alone software package, partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0154] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in conjunction with an instruction execution system, device or equipment. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium can include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0155] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0156] The systems and techniques described herein can be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include a local area network (LAN), a wide area network (WAN), and the Internet.

[0157] A computer system may include a client and a server. The client and server are typically remote from each other and typically interact via a communication network. This client-server relationship arises through computer programs running on the respective computers, creating a client-server relationship. The server may be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service ecosystem that addresses the management difficulties and limited scalability of traditional physical hosting and VPS services. The server may also be a server in a distributed system or a server integrated with blockchain.

[0158] Artificial intelligence (AI) is the study of how computers can simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, specialized AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily encompass computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graphs.

[0159] Cloud computing refers to a technology system that provides network access to elastically scalable shared pools of physical or virtual resources. These resources can include servers, operating systems, networks, software, applications, and storage devices, and can be deployed and managed on-demand in a self-service manner. Cloud computing technology provides efficient and powerful data processing capabilities for the application of technologies such as artificial intelligence and blockchain, as well as for model training.

[0160] It should be understood that the various forms of processes shown above can be used to reorder, add, or delete steps. For example, the steps described in this disclosure can be performed in parallel, sequentially, or in a different order, as long as the desired results of the technical solutions provided by this disclosure can be achieved. This is not limited herein.

[0161] The above specific embodiments do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art will appreciate that various modifications, combinations, sub-combinations, and substitutions may be made based on design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure shall be included within the scope of protection of this disclosure.

Claims

1. A method for generating a cover group in an integrated circuit verification environment, comprising: Parsing an instruction set file that matches the verification environment of the integrated circuit to be tested, and obtaining instruction description information of each instruction in the instruction set file; The instruction set file includes a definition of each data bit in each instruction, and the instruction description information includes at least one of the instruction type, static data in the instruction, at least one dynamic data in the instruction, and instruction function description information; Acquire a target instruction currently being processed, and create a target single instruction cover group corresponding to the target instruction according to the instruction type of the target instruction; Creating first-type coverpoints corresponding to each dynamic data in the target instruction in the target single instruction cover group; Setting a coverage condition for each of the first-category cover points according to static data in the target instruction; Setting a coverage bin for each first-category coverage point according to the instruction type or instruction function description information of the target instruction; Among them, setting the coverage bin of each first-category coverage point according to the instruction type or instruction function description information of the target instruction includes: obtaining the target first-category coverage point currently being processed; and obtaining the target dynamic data corresponding to the target first-category coverage point; detecting whether there is a target data type corresponding to the target dynamic data in the instruction function description information of the target instruction; if so, setting the coverage bin of the target first-category coverage point according to the bin building rules corresponding to the target data type; if not, setting the coverage bin of the target first-category coverage point according to the bin building rules corresponding to the instruction type of the target instruction in the default bin building rule set.

2. The method according to claim 1, further comprising, after creating in the target single instruction covergroup a first type of coverpoint corresponding to each dynamic data in the target instruction, If it is determined that register type data exists in each dynamic data in the target instruction, creating a second type of coverpoint corresponding to each register type data; Setting a coverage condition for each of the first-category cover points according to static data in the target instruction; Obtaining the register type corresponding to each of the register type data; The covering bin of each second-type covering point is set according to the building rules corresponding to each register type in the default building rule set.

3. The method according to claim 1 , further comprising: after setting the coverage bin of each first-category coverage point according to the instruction type or instruction function description information of the target instruction; In the target single instruction covergroup, a cross cover point corresponding to all the first-type cover points is created.

4. The method according to claim 3, wherein: Creating cross-coverpoints corresponding to all the first-type coverpoints in the target single-instruction covergroup includes: In the target single instruction covergroup, creating cross coverpoints corresponding to all the first-category coverpoints by using macro definitions; The macro definition includes a macro switch parameter, and the macro switch parameter is used to set whether to cover or not cover the cross-coverage point.

5. The method according to any one of claims 1 to 4, further comprising: Create combined coverage groups; Combining all instructions in the instruction set file in pairs to obtain multiple instruction groups; According to the instruction description information of the two instructions in each of the instruction groups, a combined cover point corresponding to each of the instruction groups is created in the combined cover group.

6. The method according to claim 5, wherein: The step of creating, in the combined cover group, combined cover points corresponding to each instruction group according to the instruction description information of the two instructions in each instruction group, includes: Obtain the first and second instructions in the target instruction group currently being processed; In the combined cover group, creating a first combined cover point and a second combined cover point corresponding to the first instruction and the second instruction respectively; generating a first wildcard representation corresponding to the first instruction according to static data and at least one dynamic data in the first instruction, and setting a first coverage bin corresponding to the first combined coverage point according to the first wildcard representation; A second wildcard representation corresponding to the second instruction is generated according to the static data and at least one dynamic data in the second instruction, and a second coverage bin corresponding to the second combined coverage point is set according to the second wildcard representation.

7. The method according to claim 6, wherein: After setting a second coverage bin corresponding to the second combined coverage point according to the second wildcard representation, the method further includes: In the combined cover group, a cross cover point corresponding to both the first combined cover point and the second combined cover point is created.

8. The method according to claim 5, further comprising, after creating the combined cover group: Combining entries according to preset invalid instructions to generate at least one of an unreasonable bin and an ignored bin; At least one of the unreasonable bin and the ignored bin is added to the combined coverage group.

9. The method according to any one of claims 1 to 4, wherein: The step of parsing the instruction set file matching the integrated circuit verification environment to be tested and obtaining instruction description information of each instruction in the instruction set file includes: If the file format of the instruction set file is a table, reading cells in the instruction set file in units of lines; When reading an empty type cell, determine whether the empty type cell belongs to a merged cell; If so, obtain the left border cell corresponding to the merged cell, and read the data content in the left border cell; Attribute names are spliced ​​along the attribute names of the left border cells toward the attribute names of the empty type cells, and the read data content is used as the attribute value of the attribute name splicing result.

10. A cover group generation device in an integrated circuit verification environment, comprising: a data parsing module, configured to parse an instruction set file that matches the verification environment of the integrated circuit under test, and obtain instruction description information for each instruction in the instruction set file; wherein the instruction set file includes a definition of each data bit in each instruction, and the instruction description information includes at least one of the following: instruction type, static data in the instruction, at least one dynamic data in the instruction, and instruction function description information; a single instruction cover group creation unit, configured to obtain a target instruction currently being processed and, based on an instruction type of the target instruction, create a target single instruction cover group corresponding to the target instruction; A first-type coverpoint creation unit, configured to create, in the target single instruction covergroup, first-type coverpoints corresponding to each dynamic data in the target instruction; a coverage condition setting unit, configured to set a coverage condition for each of the first-category cover points according to static data in the target instruction; a first coverage bin setting unit, configured to set a coverage bin for each of the first-category coverage points according to an instruction type or instruction function description information of the target instruction; Among them, the first coverage bin setting unit is specifically used to: obtain the target first-category coverage point currently being processed; and obtain the target dynamic data corresponding to the target first-category coverage point; detect whether there is a target data type corresponding to the target dynamic data in the instruction function description information of the target instruction; if so, set the coverage bin of the target first-category coverage point according to the bin building rules corresponding to the target data type; if not, set the coverage bin of the target first-category coverage point according to the bin building rules corresponding to the instruction type of the target instruction in the default bin building rule set.

11. The apparatus according to claim 10, further comprising: a second coverage bin setting module, configured to, after creating first-type coverpoints corresponding to each dynamic data in the target instruction in the target single instruction cover group, create second-type coverpoints corresponding to each register type data if it is determined that register type data exists in each dynamic data in the target instruction; Setting a coverage condition for each of the first-category cover points according to static data in the target instruction; Obtaining the register type corresponding to each of the register type data; The covering bin of each second-type covering point is set according to the building rules corresponding to each register type in the default building rule set.

12. The apparatus according to claim 10, further comprising: A cross cover point creation module is configured to create a cross cover point corresponding to all the first type cover points in the target single instruction cover group after setting a cover bin for each first type cover point according to the instruction type or instruction function description information of the target instruction.

13. The apparatus according to claim 12, wherein the cross coverage point creation module is specifically configured to: In the target single instruction covergroup, creating cross coverpoints corresponding to all the first-category coverpoints by using macro definitions; in, The macro definition includes a macro switch parameter, and the macro switch parameter is used to set whether to cover or not cover the cross coverage point.

14. An electronic device comprising: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 9.

15. A non-transitory computer-readable storage medium storing computer instructions, wherein: The computer instructions are used to enable a computer to execute the method according to any one of claims 1 to 9.

16. A computer program product comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the steps of the method according to any one of claims 1 to 9.

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