Display panel and display device

Abstract

The present application discloses a display panel and a display device. The display panel includes a plurality of data lines and a first multiplexer. The plurality of data lines are arranged at intervals along a first direction; the first multiplexer includes at least one first control unit and at least one first channel trace, and the extending direction of the first channel trace is the same as that of the data lines; each first channel trace is connected to at least two data lines; each first control unit includes a plurality of first switching elements; among at least two data lines sharing the same first channel trace, at least one data line is connected to the first channel trace through M parallel-connected first switching elements, M≥2; wherein, the display panel has a display area, and the first control unit is arranged in the display area. By integrating the first multiplexer into the display area in the present application, the border size of the display panel can be reduced.

Description

Technical Field

[0001] The present application relates to the field of display technologies, and particularly to a display panel and a display device. Background Art

[0002] Narrow bezel display screens have advantages such as being concise, beautiful, and having a high screen-to-body ratio, and are gradually becoming a major development trend of high-end display screens. At present, the development of narrow bezel technology has approached a bottleneck, and it has become particularly difficult to further reduce the bezel of the display panel and improve the product specifications.

[0003] In the prior art, the bezel area of the display panel needs to be provided with a gate driving circuit, a driving chip, a flexible printed circuit board, a Demux (demultiplexer) circuit, power traces, touch circuit traces, etc., making it difficult to further reduce the bezel of the display panel and being unfavorable for achieving narrow bezels. Summary of the Invention

[0004] The present application provides a display panel and a display device to solve the technical problem in the prior art that it is difficult to reduce the bezel of the display panel and it is unfavorable for achieving narrow bezels.

[0005] The present application provides a display panel, which includes:

[0006] Multiple data lines, the multiple data lines are arranged at intervals along a first direction;

[0007] A first demultiplexer, the first demultiplexer includes at least one first control unit and at least one first channel trace, the extending direction of the first channel trace is the same as the extending direction of the data line; each first channel trace is connected to at least two data lines; each first control unit includes multiple first switching elements; among at least two data lines sharing the same first channel trace, at least one data line is connected to the first channel trace through M parallel first switching elements, M≥2;

[0008] Wherein, the display panel has a display area, the first control unit is arranged in the display area. Optionally, in some embodiments of the present application, the first demultiplexer further includes at least two control lines, the at least two control lines are arranged at intervals along the extending direction of the data line, the at least two control lines transmit different control signals, and the control ends of the M first switching elements connected to the same data line are all connected to the same control line.

[0009] Optionally, in some embodiments of the present application, the first demultiplexer further includes multiple control lines, the multiple control lines are arranged at intervals along the extending direction of the data line;

[0010] Among them, the M control lines transmit the same control signal; the M first switching elements connected to the same data line are respectively connected to the M control lines that transmit the same control signal.

[0011] Optionally, in some embodiments of the present application, the display panel further includes a plurality of sub-pixels arranged in an array, and the plurality of first switching elements are disposed in different sub-pixels, and one control line is provided in each row of sub-pixels.

[0012] Optionally, in some embodiments of the present application, the data voltage polarities of the data lines connected to the same first channel trace are the same.

[0013] Optionally, in some embodiments of the present application, the display panel further includes at least one pixel region. Along the first direction, the pixel region includes 2N columns of sub-pixels, and two first channel traces are provided in the pixel region, and one data line is correspondingly provided for each column of sub-pixels, where N is an integer greater than or equal to 2;

[0014] Among them, the data voltage polarities of two adjacent first channel traces are opposite. In the pixel region, along the first direction, the first first channel trace is respectively connected to the odd-numbered data lines; the second first channel trace is respectively connected to the even-numbered data lines.

[0015] Optionally, in some embodiments of the present application, the display panel further includes multiple columns of sub-pixels, the data voltage polarities of two adjacent columns of sub-pixels are opposite, and the data voltage polarities of two adjacent first channel traces are opposite;

[0016] Among them, at least one auxiliary channel trace is provided between two adjacent first channel traces, and the first switching elements connected to the auxiliary channel trace are disposed in the sub-pixels adjacent to the auxiliary channel trace.

[0017] Optionally, in some embodiments of the present application, the display panel further includes at least one pixel region, each pixel region includes six columns of sub-pixels, four first channel traces are provided in each pixel region, and one data line is correspondingly provided for each column of sub-pixels;

[0018] Among them, in each pixel region, along the first direction, the first first channel trace is respectively connected to the first data line and the third data line; the second first channel trace is connected to the second data line, the third first channel trace is respectively connected to the fourth data line and the sixth data line, the fourth first channel trace is connected to the fifth data line, and the second first channel trace and the fourth first channel trace are both auxiliary channel traces.

[0019] Optionally, in some embodiments of the present application, the first channel trace described in the first item is connected in parallel with the fourth channel trace described in the first item, and the second channel trace described in the first item is connected in parallel with the third channel trace described in the first item.

[0020] Optionally, in some embodiments of the present application, the display panel further includes at least one pixel region. Along the first direction, the pixel region includes N columns of the sub-pixels, and each pixel region is provided with one of the first channel traces, where N is an integer greater than or equal to 2;

[0021] Wherein, in each pixel region, the first channel trace is respectively connected to the data lines corresponding to each column of the sub-pixels.

[0022] Optionally, in some embodiments of the present application, the display panel further includes a plurality of pixel regions, and each pixel region includes at least two adjacent columns of sub-pixels. Among the plurality of sub-pixels connected to the same first channel trace, some of the sub-pixels are located in one pixel region, and the other part of the sub-pixels are located in another pixel region.

[0023] Optionally, in some embodiments of the present application, the display panel further includes a plurality of touch traces; the plurality of touch traces are arranged at intervals along the first direction;

[0024] Wherein, the display panel further includes a second demultiplexer, the second demultiplexer includes a plurality of second control units and a plurality of second channel traces, and the plurality of second channel traces are arranged at intervals along the first direction; each second channel trace is connected to at least two of the touch traces; each second control unit includes a plurality of second switch elements; among at least two touch traces sharing the same second channel trace, at least one of the touch traces is connected to the second channel trace through the corresponding at least one second switch element; the second control unit is disposed in the display area.

[0025] Optionally, in some embodiments of the present application, along the extension direction of the data line, the display area includes a first display area and a second display area, the first demultiplexer is disposed in the second display area, the second demultiplexer is disposed in the first display area and the second display area, and in the second display area, the first switch element is disposed in one of the odd-numbered row sub-pixels and the even-numbered row sub-pixels, and the second switch element is disposed in the other of the odd-numbered row sub-pixels and the even-numbered row sub-pixels.

[0026] Optionally, in some embodiments of the present application, the display panel further includes a plurality of columns of sub-pixels, and each column of sub-pixels is correspondingly provided with one data line;

[0027] Along the first direction, the first channel trace, the touch trace, and the second channel trace are respectively disposed adjacent to different data lines.

[0028] Optionally, in some embodiments of the present application, the display panel further includes a plurality of touch electrodes arranged in an array, each touch electrode is connected to at least one touch trace and / or two second channel traces are provided corresponding to each touch electrode.

[0029] Optionally, in some embodiments of the present application, in the first display area, two second channel traces are provided corresponding to each touch electrode, and in the second display area, four second channel traces are provided corresponding to each touch electrode.

[0030] Optionally, in some embodiments of the present application, the display panel further includes a plurality of touch electrodes arranged in an array, each touch electrode is connected to at least one touch trace, and the touch electrode is multiplexed as a common electrode;

[0031] Wherein, the display panel further includes a plurality of third channel traces; the plurality of third channel traces are arranged at intervals along the first direction, and each third channel trace is connected to a corresponding touch trace.

[0032] Optionally, in some embodiments of the present application, the display panel further includes a third multiplexer, the third multiplexer includes a plurality of third control units; each third channel trace is connected to at least two touch traces; each third control unit includes a plurality of third switching elements; among at least two touch traces sharing the same third channel trace, at least one touch trace is connected to the third channel trace through a corresponding at least one third switching element.

[0033] Optionally, in some embodiments of the present application, along the extension direction of the data line, each touch electrode includes a connected first part and a second part, the second multiplexer is disposed corresponding to the second part, and the third multiplexer is disposed corresponding to the first part.

[0034] Correspondingly, the present application further provides a display device, which includes a display panel and a driving chip, the display panel is the display panel described in any one of the above, and the driving chip is connected to the first channel trace.

[0035] The present application provides a display panel and a display device. On the one hand, by providing a first multiplexer in the display panel in the embodiments of the present application, a smaller number of first-channel traces can be used to provide corresponding data signals to a larger number of data lines, thereby reducing the number of driving chips and lowering the production cost. On the second hand, by arranging the first multiplexer in the display area in the embodiments of the present application, the border size of the display panel can be reduced, which is conducive to realizing narrow borders. On the third hand, since there are multiple sub-pixels in the display area, when the first switching element T1 is integrated in the display area, in order not to affect the aperture ratio of the sub-pixels, the size of the first switching element is very small. It can be understood that the resistance of the first switching element is related to the device size. The smaller the size of the first switching element, the larger the resistance, which easily leads to poor data signal transmission. In the embodiments of the present application, at least one data line is connected to the first-channel trace through M parallel first switching elements, which can improve the signal transmission yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the following drawings are only some embodiments of the present application. For those skilled in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0037] Figure 1 is the first structural schematic diagram of the display panel provided by the present application;

[0038] Figure 2 is the first planar schematic diagram of the display panel provided by the present application;

[0039] Figure 3 is the second structural schematic diagram of the display panel provided by the present application;

[0040] Figure 4 is the second planar schematic diagram of the display panel provided by the present application;

[0041] Figure 5 is the third structural schematic diagram of the display panel provided by the present application;

[0042] Figure 6 is the third planar schematic diagram of the display panel provided by the present application;

[0043] Figure 7 is the structural schematic diagram of the touch electrode, the second multiplexer, and the third multiplexer provided by the present application;

[0044] Figure 8 is the fourth planar schematic diagram of the display panel provided by the present application;

[0045] Figure 9It is the fifth planar schematic diagram of the display panel provided by the present application;

[0046] Figure 10 It is a schematic structural diagram of a display device provided by the present application. Detailed implementation manners

[0047] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative efforts belong to the scope of protection of the present application.

[0048] In the description of the present application, it should be understood that the terms "first" and "second" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" etc. may explicitly or implicitly include one or more of the described features, and thus cannot be understood as a limitation to the present application. In addition, it should be noted that unless otherwise clearly defined and limited, the terms "connected" and "coupled" should be understood in a broad sense. For example, it may be a mechanical connection or an electrical connection; it may be directly connected or indirectly connected through an intermediate medium, and it may be the internal connection of two components. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0049] The present application provides a display panel and a display device, which will be described in detail below. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application.

[0050] Please refer to Figure 1 , Figure 1 It is the first schematic structural diagram of the display panel provided by the present application. In the embodiment of the present application, the display panel 100 includes a plurality of data lines D and a first multiplexer 10.

[0051] Among them, the plurality of data lines D are arranged at intervals along the first direction X. The first multiplexer 10 includes at least one first control unit 11 and at least one first channel trace S. The extending direction of the first channel trace S is the same as that of the data line D. Each first channel trace S is connected to at least two data lines D. Each first control unit 11 includes a plurality of first switching elements T1. Among at least two data lines D sharing the same first channel trace S, at least one data line D is connected to the first channel trace S through M parallel first switching elements T1, and M is an integer greater than or equal to 2. The display panel 100 has a display area AA. The first control unit 11 is disposed in the display area AA.

[0052] In an embodiment of the present application, the display panel 100 further includes a plurality of scan lines G (such as G1 / G2 / G3 / G4 / G5 / G6, etc.). The plurality of scan lines G are arranged at intervals along the extending direction of the data lines D. The plurality of scan lines G and the plurality of data lines D intersect to define a plurality of sub-pixels 20. The plurality of sub-pixels 20 are arranged in an array. Each sub-pixel 20 is connected to a corresponding data line D and a corresponding scan line G. Since the same first channel trace S is connected to a plurality of data lines D, the sub-pixels 20 in the corresponding row can be controlled to be turned on through the plurality of scan lines G, avoiding data signal transmission errors.

[0053] Among them, the sub-pixels 20 presented in the display screen may be red sub-pixels, green sub-pixels, blue sub-pixels, white sub-pixels, yellow sub-pixels, etc., and the present application does not make specific limitations thereto. The display panel 100 provided by the present application may adopt a standard RGB pixel arrangement architecture, an RGB PenTile pixel arrangement architecture, an RGB Delta pixel arrangement architecture, an RGBW pixel arrangement architecture, etc. When the display panel 100 adopts a standard RGB pixel arrangement architecture, among the sub-pixels 20 in the same row, the red sub-pixels, green sub-pixels, and blue sub-pixels may be repeatedly arranged in any one of the arrangement combinations such as RGB, RBG, BGR, BRG, GRB, GBR, etc. The colors of the sub-pixels 20 in each column are the same. Of course, the present application is not limited thereto, and specific settings can be made according to the display requirements of the display panel 100.

[0054] In an embodiment of the present application, on the one hand, by providing the first multiplexer 10 in the display panel 100, a smaller number of first channel traces S can be used to provide corresponding data signals to a larger number of data lines D, thereby reducing the number of driving chips and lowering the production cost. On the other hand, the Demux circuit is usually arranged in the border area, and its height can reach hundreds or even thousands of micrometers, becoming a major difficulty in realizing a narrow border of the display screen. In the embodiment of the present application, by arranging the first multiplexer 10 in the display area AA, the border size of the display panel 100 can be reduced, which is conducive to realizing a narrow border. On the third hand, since there are a plurality of sub-pixels 20 in the display area AA, when the first switching element T1 is integrated in the display area AA, in order not to affect the aperture ratio of the sub-pixels 20, the size of the first switching element T1 is very small. It can be understood that the resistance of the first switching element T1 is related to the device size, and the size of the first switching element T1 is very small, which easily leads to poor data signal transmission. In the embodiment of the present application, at least one data line D is connected to the first channel trace S through M parallel first switching elements T1, which can improve the transmission yield of the data signal.

[0055] In the embodiment of the present application, the first multiplexer 10 further includes at least two control lines Mux. The at least two control lines Mux are arranged at intervals along the extension direction of the data line D. Each control line Mux is used to transmit a corresponding control signal. The control end of each first switching element T1 is connected to the corresponding control line Mux. The control line Mux is used to control the first switching element T1 to be turned on or off.

[0056] Among them, the control line Mux can be arranged on the same layer as the scan line G. On the one hand, it is beneficial to reduce the film layer structure of the display panel 100 and realize the thinning of the display panel 100; on the other hand, in the process of manufacturing the scan line G, the control line Mux can be formed synchronously, thereby saving the manufacturing process and improving production efficiency. Of course, the control line Mux can also be formed by different conductive layers from the scan line G.

[0057] Among them, the input pole of the first switching element T1 is connected to the corresponding first channel trace S. The output pole of the first switching element T1 is connected to the corresponding data line D. Among them, the first switching element T1 can be a thin film transistor. The control end of the first switching element T1 is the gate of the thin film transistor. The input pole of the first switching element T1 is one of the source and drain of the thin film transistor. The output pole of the first switching element T1 is the other of the source and drain of the thin film transistor. The control line Mux controls the first switching element T1 connected thereto to be turned on or off, so that the first channel trace S can transmit data signals to the corresponding data lines D respectively.

[0058] Correspondingly, when the first switching element T1 is a thin film transistor, the larger the channel width-to-length ratio W / L of the thin film transistor, the smaller the resistance under the same conditions. However, when the size of the first switching element T1 is small, it is difficult for the channel width-to-length ratio W / L of the first switching element T1 to meet the preset requirements, resulting in poor transmission of data signals. Therefore, in the embodiment of the present application, at least one data line D is connected to the first channel trace S through at least two parallel first switching elements T1, and the resistance of the multiple parallel first switching elements T1 is reduced, which can improve the transmission yield of data signals.

[0059] In the embodiment of the present application, the number of control lines Mux is related to the number of data lines D connected to each first channel trace S1. Each first channel trace S1 can be connected to 2 data lines D; each first channel trace S1 can also be connected to 3 data lines D; each first channel trace S1 can also be connected to 4 data lines D, which will not be elaborated one by one in this application.

[0060] It should be noted that in the following embodiments of the present application, each first channel trace S1 is connected to 3 data lines D as an example for illustration. Correspondingly, the control line Mux includes a first control line Mux1, a second control line Mux2, and a third control line Mux3. However, it should not be construed as a limitation to the present application.

[0061] In some embodiments of the present application, M control lines Mux transmit the same control signal. M first switching elements T1 connected to the same data line D are respectively connected to M control lines Mux that transmit the same control signal in a one-to-one correspondence. That is, at least one of the first control line Mux1, the second control line Mux2, and the third control line Mux3 can be set to M lines.

[0062] Specifically, please continue to refer to Figure 1 , in the embodiments of the present application, the first control line Mux1, the second control line Mux2, and the third control line Mux3 are respectively set to two. The two first control lines Mux1 can be connected in parallel to access the same control signal; the two first control lines Mux1 can also be respectively connected to the same control signal. The two second control lines Mux2 can be connected in parallel to access the same control signal; the two second control lines Mux2 can also be respectively connected to the same control signal. The two third control lines Mux3 can be connected in parallel to access the same control signal; the two third control lines Mux3 can also be respectively connected to the same control signal.

[0063] Among them, two first switching elements T1 connected to the first data line D1 or the fourth data line D4 are respectively connected to the two first control lines Mux1 in a one-to-one correspondence. Two first switching elements T1 connected to the second data line D2 or the fifth data line D5 are respectively connected to the two second control lines Mux2 in a one-to-one correspondence. Two first switching elements T1 connected to the third data line D3 or the sixth data line D6 are respectively connected to the two third control lines Mux3 in a one-to-one correspondence.

[0064] Among them, along the extending direction of the data line D, multiple control lines Mux can be repeatedly arranged in units of the first control line Mux1, the second control line Mux2, and the third control line Mux3.

[0065] Thus, the embodiments of the present application can achieve the parallel connection of multiple first switching elements T1 connected to the same data line D, improve the conductivity of the multiple first switching elements T1, and avoid poor data signal transmission.

[0066] It should be noted that in some embodiments of the present application, the number of first switching elements T1 connected to the same data line D can also be 3, 4, or more. Correspondingly, 3, 4, or more first control lines Mux1 (second control line Mux2 or third control line Mux3) can be set, which will not be elaborated here.

[0067] Of course, in some embodiments of the present application, the first demultiplexer 10 may further include at least two control lines Mux, and different control signals are transmitted on the at least two control lines Mux. The control ends of the multiple first switching elements T1 connected to the same data line D are connected to the same control line Mux.

[0068] The embodiments of the present application can reduce the number of control lines Mux. Some of the first switching elements T1 can be connected to the corresponding control lines Mux by changing the wiring, which will not be elaborated here.

[0069] Furthermore, in some embodiments of the present application, multiple first switching elements T1 are arranged in different sub-pixels 20. At most one control line Mux is provided in each row of sub-pixels 20.

[0070] It can be understood that the display panel 100 has certain specification requirements for the pixel aperture ratio. In the embodiments of the present application, multiple first switching elements T1 are respectively arranged in different sub-pixels 20, and only one control line Mux is arranged in the corresponding row of sub-pixels 20, which can reduce the influence on the pixel aperture ratio and improve the display uniformity of the display panel 100.

[0071] In the embodiments of the present application, the data voltage polarities of the data lines D connected to the same first channel trace S are the same. Of course, in some embodiments, if the polarity of the data voltage is adjusted and transformed in the driving chip, the data voltage polarities of the data lines D connected to the same first channel trace S can also be different.

[0072] In the embodiments of the present application, different driving methods, such as dot inversion, column inversion, frame inversion, row inversion, etc., can be achieved by adjusting the connection manner of each data line D to the first channel trace S, or adjusting the connection manner of each sub-pixel 20 to the data line D.

[0073] Please continue to refer to Figure 1 In the embodiments of the present application, the display panel 100 further includes at least one pixel region 201. Along the first direction X, the pixel region 201 includes 2N columns of sub-pixels 20. Each pixel region 201 is provided with two first channel traces S. Each column of sub-pixels 20 is correspondingly provided with one data line D. Wherein N is an integer greater than or equal to 2.

[0074] Among them, the data voltage polarities of two adjacent first channel traces S are opposite. In each pixel region 201, along the first direction X, the first first channel trace S1 is respectively connected to the odd-numbered data lines D. The second first channel trace S2 is respectively connected to the even-numbered data lines D.

[0075] Through the above connection method, the polarities of the sub-pixels 20 in each column can be the same, and the polarities of two adjacent sub-pixels 20 in each row of sub-pixels 20 are opposite. That is, the embodiment of the present application can implement a column inversion driving method to improve display problems such as picture crosstalk.

[0076] Further, the embodiment of the present application takes N as 3, and the pixel region 201 includes 6 columns of sub-pixels 20 as an example for illustration. That is, each first channel trace S transmits corresponding data signals to 3 data lines D respectively.

[0077] Specifically, in each pixel region 201, along the first direction X, the first first channel trace S1 is disposed adjacent to the first data line D1. For example, the first first channel trace S1 is disposed on the left side of the first data line D1; the second first channel trace S2 is disposed adjacent to the fourth data line D4. For example, the second first channel trace S2 is disposed on the left side of the fourth data line D4. The first first channel trace S1 is connected to the first data line D1, the fifth data line D5, and the third data line D3 respectively. The second first channel trace S2 is connected to the fourth data line D4, the second data line D2, and the sixth data line D6 respectively.

[0078] Among them, the first first channel trace S1 transmits a data signal with a positive polarity; the second first channel trace S2 transmits a data signal with a negative polarity. Therefore, along the first direction X, the first column of sub-pixels 20, the third column of sub-pixels 20, and the fifth column of sub-pixels 20 are all of positive polarity; the second column of sub-pixels 20, the fourth column of sub-pixels 20, and the sixth column of sub-pixels 20 are all of negative polarity.

[0079] In the embodiment of the present application, each pixel region 201 may include at least two adjacent columns of sub-pixels 20. For example, each pixel region 201 may include three columns of RGB sub-pixels 20. Among the multiple sub-pixels 20 connected to the same first channel trace S, some sub-pixels 20 are located in one pixel region 201, and some other sub-pixels 20 are located in another pixel region 201. By designing in-plane wire connection, the data voltage polarities required by the sub-pixels 20 located in different pixel regions 201 can be achieved.

[0080] Further, please refer to Figure 1 and Figure 2 , Figure 2 is the first planar schematic diagram of the display panel provided by the present application. As Figure 2As shown, since the first first-channel trace S1 is disposed on the left side of the first data line D1, in order to avoid short circuits between different signal lines, multiple wire-changing designs are required to achieve the connection between the first first-channel trace S1 and the fifth data line D5. Similarly, since the second first-channel trace S2 is disposed on the left side of the fourth data line D4, multiple wire-changing designs are required to achieve the connection between the second first-channel trace S2 and the second data line D2. The multiple wire-changing designs result in a certain loss of pixel aperture ratio.

[0081] For this, please refer to Figure 3 and Figure 4 , Figure 3 which is the second structural schematic diagram of the display panel provided by the present application; Figure 4 which is the second planar schematic diagram of the display panel provided by the present application. Different from the display panel 100 shown in Figure 1 and Figure 2 , in the embodiment of the present application, at least one auxiliary-channel trace is provided between two adjacent first-channel traces S, and the first switching element T1 connected to the auxiliary-channel trace is disposed in the sub-pixel 20 adjacent to the auxiliary-channel trace.

[0082] Wherein, along the first direction X, among two adjacent first-channel traces S and one auxiliary-channel trace, the data voltage polarity of the previous first-channel trace S is opposite to that of the auxiliary-channel trace, and the data voltage polarity of the subsequent first-channel trace S is the same as that of the auxiliary-channel trace.

[0083] In the embodiment of the present application, an auxiliary-channel trace is added between two adjacent first-channel traces S. By controlling the voltage polarity of the auxiliary-channel trace, column inversion can be achieved. At the same time, the first switching element T1 connected to the auxiliary-channel trace is disposed in the sub-pixel 20 adjacent to the auxiliary-channel trace, and the connection between the auxiliary-channel trace and the corresponding sub-pixel 20 and the data line D can be achieved without wire changing.

[0084] Further, in a specific embodiment, each pixel region 201 includes six columns of sub-pixels 20. Four first-channel traces S are provided in each pixel region 201. One data line D is correspondingly provided for each column of sub-pixels 20.

[0085] Wherein, in each pixel region 201, along the first direction X, the first first-channel trace S1 is respectively connected to the first data line D1 and the third data line D3. The second first-channel trace S2 is connected to the second data line D2. The third first-channel trace S3 is respectively connected to the fourth data line D4 and the sixth data line D6. The fourth first-channel trace S4 is connected to the fifth data line D5.

[0086] Among them, the second first-channel trace S2 and the fourth first-channel trace S4 are both auxiliary channel traces. The data voltage polarities of the first first-channel trace S1 and the fourth first-channel trace S4 are the same. The data voltage polarities of the second first-channel trace S2 and the third first-channel trace S3 are the same. The data voltage polarities of the first first-channel trace S1 and the second first-channel trace S2 are opposite.

[0087] Thus, while implementing the column inversion driving method, the wire swapping within the display area AA can be reduced, thereby increasing the pixel aperture ratio and improving the display effect of the screen.

[0088] Furthermore, in the embodiments of the present application, the first first-channel trace S1 and the fourth first-channel trace S4 are connected in parallel; the second first-channel trace S2 and the third first-channel trace S3 are connected in parallel.

[0089] It can be understood that since the data voltage polarities of the first first-channel trace S1 and the fourth first-channel trace S4 are the same, and the three data lines D respectively connected to the first first-channel trace S1 and the fourth first-channel trace S4 respectively transmit data signals through different first switching elements T1, the first first-channel trace S1 and the fourth first-channel trace S4 can be designed to be connected in parallel, further reducing the number of first-channel traces S, and thus reducing the number of driving chips. Similarly, by designing the second first-channel trace S2 and the third first-channel trace S3 to be connected in parallel, the number of driving chips can also be reduced, lowering the production cost.

[0090] In some embodiments of the present application, please refer to Figure 5 , Figure 5 which is the third planar schematic diagram of the display panel provided by the present application. Different from the display panel 100 shown in Figure 1 and Figure 2 , in the embodiments of the present application, along the first direction X, the pixel region 201 includes N columns of sub-pixels 20. Each pixel region 201 is provided with a first-channel trace S. N is an integer greater than or equal to 2. Among them, in each pixel region 201, the first-channel trace S is respectively connected to the data lines D corresponding to each column of sub-pixels 20.

[0091] As shown in Figure 5 , the embodiments of the present application take N = 3 as an example for illustration, but it should not be construed as a limitation to the present application. Specifically, along the first direction X, the first first-channel trace S1 is respectively connected to the first data line D1, the second data line D2, and the third data line D3. The second first-channel trace S2 is respectively connected to the fourth data line D4, the fifth data line D5, and the sixth data line D6.

[0092] In the embodiments of the present application, multiple first-channel traces S can transmit data signals with the same polarity. Meanwhile, the wire-changing design in the display area AA is very few, further improving the pixel aperture ratio.

[0093] In some embodiments of the present application, please refer to Figure 6 and Figure 7 , Figure 6 which is the third plane schematic diagram of the display panel provided by the present application; Figure 7 which is the schematic structural diagram of the touch electrode, the second multiplexer, and the third multiplexer provided by the present application. Different from the display panel 100 shown in Figure 1 and Figure 2 , in the embodiments of the present application, the display panel 100 further includes multiple touch traces RX. The multiple touch traces RX are arranged at intervals along the first direction X.

[0094] Among them, the display panel 100 further includes a second multiplexer 40. The second multiplexer 40 includes multiple second control units 41 and multiple second-channel traces TPS. The second-channel traces TPS are arranged at intervals along the first direction X. Each second-channel trace TPS is connected to at least two touch traces RX. Each second control unit 41 includes multiple second switching elements T2. Among the multiple touch traces RX sharing the same second-channel trace TPS, at least one touch trace RX is connected to a second-channel trace TPS through the corresponding at least one second switching element T2.

[0095] By arranging the second multiplexer 40 in the display area AA in the present application, the border size of the display panel 100 can be further reduced, which is beneficial to realizing narrow borders.

[0096] It should be noted that, in order to improve the display uniformity of the display panel 100, the first-channel traces S and the second-channel traces TPS can be arranged in different column sub-pixels 20.

[0097] In the embodiments of the present application, the display panel 100 further includes multiple touch electrodes 30. Each touch electrode 30 can be designed corresponding to multiple sub-pixels 20. For example, each touch electrode 30 can be arranged corresponding to 40 rows and 40 columns of sub-pixels 20, and the present application does not make specific limitations on this. Figure 6 Only a partial structure of the touch electrode 30 is shown, but it should not be construed as a limitation to the present application.

[0098] Among them, each touch electrode 30 is connected to at least one touch trace RX. It can be understood that, since the area of the touch electrode 30 is relatively large, in order to improve the distribution uniformity of the touch signal, multiple touch traces RX can be arranged to be connected to the same touch electrode 30 to transmit the touch signal to different positions of the touch electrode 30.

[0099] Among them, at least one second channel trace TPS is provided corresponding to each touch electrode 30. Similarly, since the area of the touch electrode 30 is relatively large, by providing multiple second channel traces TPS, touch signals can be provided for multiple touch traces RX. When multiple second channel traces TPS are provided corresponding to each column of touch electrodes 30, the multiple second channel traces TPS can be connected in parallel to further reduce the number of channels of the driving chip.

[0100] As Figure 6 shown, in the embodiment of the present application, an example is given in which each touch electrode 30 is connected to 3 touch traces RX. Among them, along the first direction X, the second touch trace RX2 is connected to the first second channel trace TPS1 through the second switching element T2; the second touch trace RX2 is connected to the second second channel trace TPS2 through the second switching element T2.

[0101] Among them, the second demultiplexer 40 further includes multiple control signal lines TPMux. The multiple control signal lines TPMux are arranged at intervals along the extension direction of the data line D. Similarly, in the embodiment of the present application, at least one touch trace RX can be provided to be connected to a second channel trace TPS through multiple parallel second switching elements T2 to improve the transmission yield of the touch signal. For example, as Figure 6 shown, the first control signal line TPMux1 is set to two, and each touch trace RX is connected to the same second channel trace TPS through two second switching elements T2. The two second switching elements T2 are respectively connected to the two first control signal lines TPMux1 correspondingly, so as to realize the parallel connection of the two second switching elements T2.

[0102] As Figure 7 shown, the second demultiplexer 40 includes two control signal lines TPMux for accessing different control signals. Along the extension direction of the data line D, among two adjacent touch electrodes 30, the first control signal line TPMux1 is used to control the first second channel trace TPS1 and the second second channel trace TPS2 to transmit the touch signal to the upper touch electrode 30. The second control signal line TPMux2 is used to control the first second channel trace TPS1 and the second second channel trace TPS2 to transmit the touch signal to the lower touch electrode 30. That is, the same second channel trace TPS is connected to at least two touch traces RX, and then at least the upper and lower two touch electrodes 30 are controlled, so that the touch electrodes 30 in odd rows and even rows do not work simultaneously.

[0103] In order to improve the display uniformity of the display panel 100, the first channel trace S, the touch trace RX, and the second channel trace TPS can be respectively arranged adjacent to different data lines D.

[0104] In an embodiment of the present application, the display panel 100 further includes a plurality of third channel traces VS. The plurality of third channel traces VS are arranged at intervals along the first direction X. Each third channel trace VS is connected to a corresponding touch electrode 30. Figure 6 Only 1 third channel trace VS is shown, but it should not be construed as a limitation of the present application.

[0105] It should be noted that, in order to improve the display uniformity of the display panel 100, the first channel trace S, the second channel trace TPS, and the third channel trace VS can be respectively disposed adjacent to different data lines D.

[0106] In some embodiments of the present application, the touch electrode 30 can be reused as a common electrode. During the display stage, each third channel trace VS transmits a common voltage to the corresponding touch electrode 30. During the touch stage, each third channel trace VS transmits a touch signal to the corresponding touch electrode 30. Since the area of the touch electrode 30 is relatively large, using the third channel trace VS to transmit the touch signal to the corresponding touch electrode 30 can enhance the strength of the touch signal and improve the distribution uniformity of the touch signal.

[0107] In some embodiments of the present application, the display panel 100 further includes a third multiplexer 50. The third multiplexer 50 includes a plurality of third control units 51. Each third channel trace VS is connected to at least two touch traces RX. Each third control unit 51 includes a plurality of third switching elements T3. Among the multiple touch traces RX sharing the same third channel trace VS, at least one touch trace RX is connected to a third channel trace VS through the corresponding at least one third switching element T3.

[0108] By disposing the third multiplexer 50 within the display area AA in the present application, the border size of the display panel 100 can be further reduced, which is conducive to achieving a narrow border. Similarly, in the embodiment of the present application, at least one touch trace RX can be set to be connected to the third channel trace VS through a plurality of parallel third switching elements T3, which can improve the transmission yield of the touch signal.

[0109] It should be noted that the structures and connection manners of the second switching element T2 and the third switching element T3 can refer to the first switching element T1 in the above embodiments, and will not be elaborated herein.

[0110] Among them, the third multiplexer 50 further includes a plurality of control traces VMux. The plurality of control traces VMux are arranged at intervals along the extension direction of the data line D. Figure 6 Only one control trace VMux is shown, but it should not be construed as a limitation of the present application.

[0111] Similarly, in the embodiments of the present application, at least one touch trace RX can be set to be connected to the third channel trace VS through multiple parallel third switching elements T3 to improve the transmission yield of touch signals. For example, as Figure 6 shown, the first control trace VMux1 is set to two, and each touch trace RX is connected to the same third channel trace VS through two third switching elements T3. The two third switching elements T3 are respectively connected to the two first control traces VMux1 correspondingly, so as to realize the parallel connection of the two third switching elements T3.

[0112] Specifically, as Figure 6 and Figure 7 shown, the third multiplexer 50 includes two control traces VMux for accessing different control signals. Along the extension direction of the data line D, among two adjacent touch electrodes 30, the first control trace VMux1 is used to control the third channel trace VS to transmit the touch signal to the upper touch electrode 30. The second control trace VMux2 is used to control the third channel trace VS to transmit the touch signal to the lower touch electrode 30.

[0113] Furthermore, in some embodiments of the present application, as Figure 7 shown, along the extension direction of the data line D, each touch electrode 30 includes a connected first portion 31 and second portion 32. The second multiplexer 40 is correspondingly arranged for the second portion 32, and the third multiplexer 50 is correspondingly arranged for the first portion 31.

[0114] It can be understood that the embodiments of the present application arrange the second multiplexer 40 and the third multiplexer 50 in different regions, which can ensure the display uniformity of the display panel 100.

[0115] In some embodiments of the present application, please refer to Figure 1 、 Figure 6 and Figure 8 simultaneously. Along the extension direction of the data line D, the display area AA includes a first display area AA1 and a second display area AA2. The first multiplexer 10 is arranged in the second display area AA2. The second multiplexer 40 is arranged in the first display area AA1 and the second display area AA2. In the second display area AA2, the first switching element T1 is arranged in one of the odd-row sub-pixels and the even-row sub-pixels. The second switching element T2 is arranged in the other of the odd-row sub-pixels and the even-row sub-pixels.

[0116] Furthermore, the third multiplexer 50 can be arranged in the first display area AA1 and the second display area AA2. The first switching element T1 and the third switching element T3 are also arranged in different row sub-pixels 20.

[0117] For example, taking the display panel 100 with a resolution of 1920×720 as an example, in the 240 rows below the display panel 100 (occupying the height of 6 touch electrodes 30), the first multiplexer 10, the second multiplexer 40, and the third multiplexer 50 are distributed in different areas of the display panel 100. In the 480 rows above the display panel 100 (occupying the height of 12 touch electrodes 30), only the second multiplexer 40 and the third multiplexer 50 are provided. Of course, the present application is not limited to this.

[0118] Thus, the first multiplexer 10, the second multiplexer 40, and the third multiplexer 50 can be evenly arranged in the display area AA, improving the display uniformity of the display panel 100.

[0119] In addition, in some embodiments of the present application, in the first display area AA1, as Figure 9 shown, two second channel traces TPS are provided corresponding to each touch electrode 30; in the second display area AA2, as Figure 6 shown, four second channel traces TPS are provided corresponding to each touch electrode 30.

[0120] Furthermore, in the first display area AA1, one third channel trace VS is provided corresponding to each touch electrode 30, and in the second display area AA2, two third channel traces VS are provided corresponding to each touch electrode 30.

[0121] It can be understood that the first multiplexer 10, the second multiplexer 40, and the third multiplexer 50 are all provided in the second display area AA2, and the first multiplexer 10 occupies a part of the wiring space. Thus, in the second display area AA2, the second switching element T2 and the third switch T3 can only be arranged in one of the odd-row sub-pixels and the even-row sub-pixels to be staggeredly arranged with the first switching element T1. Therefore, in order to improve the transmission yield of the touch signal, in the embodiments of the present application, four second channel traces TPS and two third channel traces VS are provided corresponding to each touch electrode 30 in the second display area AA2.

[0122] Correspondingly, the present application also provides a display device. The display device includes a display panel. The display panel is the display panel 100 described in any of the above embodiments, which will not be elaborated here.

[0123] In addition, the display device can be a smart phone, a tablet computer, an e-book reader, a smart watch, a camera, a game console, etc., and the present application does not limit this.

[0124] Specifically, please refer to Figure 10 , Figure 10It is a schematic structural diagram of a display device provided by the present application. In an embodiment of the present application, the display device 1000 includes a display panel 100 and a driving chip 200. The driving chip 200 is connected to a plurality of first channel traces S.

[0125] Among them, the driving chip 200 may be a source driving chip. The driving chip 200 is used to provide data signals to a plurality of first channel traces S, and further drive each sub-pixel to display a picture.

[0126] In an embodiment of the present application, the second channel trace TPS and the third channel trace VS may also be connected to the driving chip 200. The driving chip 200 is also used to provide a touch signal and a common voltage, which improves the integration of the driving chip 200 and reduces the number of driving chips 200.

[0127] The display device 1000 in an embodiment of the present application includes a display panel 100. The display panel 100 includes a plurality of data lines and a first demultiplexer. The plurality of data lines are arranged at intervals along a first direction; the first demultiplexer includes at least one first control unit and at least one first channel trace. The extending direction of the first channel trace is the same as the extending direction of the data lines; each first channel trace is connected to at least two data lines; each first control unit includes a plurality of first switching elements; among at least two data lines sharing the same first channel trace, at least one data line is connected to the first channel trace through M parallel-connected first switching elements, M≥2; wherein, the display panel has a display area, and the first control unit is arranged in the display area. Integrating the first demultiplexer in the display area in an embodiment of the present application can reduce the border size of the display panel 100, which is beneficial to realizing the narrow border of the display device 1000.

[0128] The above has introduced in detail the display panel and the display device provided by the embodiments of the present application. Specific examples are used in this article to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A display panel, characterized in that, Comprising: A plurality of data lines, the plurality of data lines being arranged at intervals in a first direction; A first multiplexer, the first multiplexer including at least one first control unit and at least one first channel trace, the extending direction of the first channel trace being the same as the extending direction of the data lines; each first channel trace is connected to at least two of the data lines; each first control unit includes a plurality of first switch elements; among at least two of the data lines sharing the same first channel trace, at least one of the data lines is connected to the first channel trace through M parallel-connected first switch elements, M≥2; Wherein, the display panel has a display area, and the first control unit is arranged in the display area; The data voltage polarities of the data lines connected to the same first channel trace are the same; The display panel further includes at least one pixel area, along the first direction, the pixel area includes 2N columns of sub-pixels, and two first channel traces are provided in the pixel area, and each column of sub-pixels is correspondingly provided with one data line, where N is an integer greater than or equal to 2; Wherein, the data voltage polarities of two adjacent first channel traces are opposite, and in the pixel area, along the first direction, the first first channel trace is respectively connected to the odd-numbered data lines; the second first channel trace is respectively connected to the even-numbered data lines.

2. The display panel according to claim 1, wherein The first multiplexer further includes at least two control lines, the at least two control lines being arranged at intervals along the extending direction of the data lines, the at least two control lines transmitting different control signals, and the M first switch elements connected to the same data line are all connected to the same control line.

3. The display panel according to claim 1, characterized in that, The first multiplexer further includes at least two control lines, the at least two control lines being arranged at intervals along the extending direction of the data lines; Wherein, M of the control lines transmit the same control signal; the M first switch elements connected to the same data line are respectively connected to the M control lines transmitting the same control signal in a one-to-one correspondence.

4. The display panel according to claim 2 or 3, characterized in that, The display panel further includes a plurality of sub-pixels arranged in an array, the plurality of first switch elements are arranged in different sub-pixels, and at most one control line is provided in each row of sub-pixels.

5. The display panel according to claim 1, wherein The display panel further includes multiple columns of sub-pixels, the data voltage polarities of two adjacent columns of sub-pixels are opposite, and the data voltage polarities of two adjacent first channel traces are opposite; Wherein, at least one auxiliary channel trace is provided between two adjacent first channel traces, and the first switch elements connected to the auxiliary channel trace are arranged in the sub-pixels adjacent to the auxiliary channel trace.

6. The display panel according to claim 5, characterized in that, The display panel further includes at least one pixel area, each pixel area includes six columns of sub-pixels, and four first channel traces are provided in each pixel area, and each column of sub-pixels is correspondingly provided with one data line; Among them, in each of the pixel regions, along the first direction, the first first-channel trace is respectively connected to the first data line and the third data line; the second first-channel trace is connected to the second data line; the third first-channel trace is respectively connected to the fourth data line and the sixth data line; the fourth first-channel trace is connected to the fifth data line; the second first-channel trace and the fourth first-channel trace are both auxiliary channel traces.

7. The display panel according to claim 6, wherein The first first-channel trace is connected in parallel with the fourth first-channel trace, and the second first-channel trace is connected in parallel with the third first-channel trace.

8. The display panel according to claim 1, wherein The display panel further includes a plurality of pixel regions, each pixel region includes at least two adjacent columns of sub-pixels, among the plurality of sub-pixels connected to the same first-channel trace, some of the sub-pixels are located in one pixel region, and the other part of the sub-pixels are located in another pixel region.

9. The display panel according to claim 1, wherein The display panel further includes a plurality of touch traces; the plurality of touch traces are arranged at intervals along the first direction; Among them, the display panel further includes a second multiplexer, the second multiplexer includes a plurality of second control units and a plurality of second-channel traces, the plurality of second-channel traces are arranged at intervals along the first direction; each second-channel trace is connected to at least two of the touch traces; each second control unit includes a plurality of second switching elements; among at least two touch traces sharing the same second-channel trace, at least one touch trace is connected to the second-channel trace through the corresponding at least one second switching element; the second control unit is disposed in the display area.

10. The display panel according to claim 9, wherein Along the extension direction of the data line, the display area includes a first display area and a second display area, the first multiplexer is disposed in the second display area, the second multiplexer is disposed in the first display area and the second display area, in the second display area, the first switching element is disposed in one of the odd-numbered row sub-pixels and the even-numbered row sub-pixels, and the second switching element is disposed in the other of the odd-numbered row sub-pixels and the even-numbered row sub-pixels.

11. The display panel according to claim 10, wherein The display panel further includes a plurality of columns of sub-pixels, and each column of sub-pixels is correspondingly provided with a data line; Along the first direction, the first-channel trace, the touch trace, and the second-channel trace are respectively disposed adjacent to different data lines.

12. The display panel according to claim 10, wherein The display panel further includes a plurality of touch electrodes arranged in an array, each touch electrode is connected to at least one touch trace and / or at least one second-channel trace is correspondingly provided for each touch electrode.

13. The display panel according to claim 12, wherein In the first display area, two second-channel traces are correspondingly provided for each touch electrode, and in the second display area, four second-channel traces are correspondingly provided for each touch electrode.

14. The display panel according to claim 9, wherein The display panel further includes a plurality of touch electrodes arranged in an array, each touch electrode is connected to at least one touch trace, and the touch electrode is multiplexed as a common electrode; Wherein, the display panel further includes a plurality of third-channel traces; the plurality of third-channel traces are arranged at intervals along the first direction, and each third-channel trace is connected to a corresponding touch trace.

15. The display panel according to claim 14, wherein The display panel further includes a third multiplexer, the third multiplexer includes a plurality of third control units; each third-channel trace is connected to at least two touch traces; each third control unit includes a plurality of third switching elements; among at least two touch traces sharing the same third-channel trace, at least one touch trace is connected to the third-channel trace through a corresponding at least one third switching element; the third control unit is disposed in the display area.

16. The display panel according to claim 15, wherein, Along the extension direction of the data line, each touch electrode includes a connected first part and a second part, the second multiplexer is disposed corresponding to the second part, and the third multiplexer is disposed corresponding to the first part.

17. A display device, characterized in that, It includes a display panel and a driving chip, the display panel is the display panel according to any one of claims 1-16, and the driving chip is connected to the first-channel trace.

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