Display device and operating method thereof

Abstract

The present invention discloses a display device and an operating method thereof. The display device may include a pixel, an emission control driver, and a timing controller. The emission control driver may supply an emission control signal set, the emission control signal set being used to control the emission period of the pixel. The timing controller may receive a received bit stream including a first bit set and a second bit set, and may use bits in the first bit set without using any bits in the second bit set to determine a first duty cycle of the emission control signal set. The first bit set may include at least two bits. The second bit set may include at least one bit. The emission control signal set may control the pixel to operate according to a first duty cycle for each frame of a first frame group.

Description

[0001] This application is a divisional application of the invention with the application date of October 18, 2018, application number 201811213751.6 and name “Display device and operation method thereof”.

[0002] CROSS-REFERENCE TO RELATED APPLICATIONS

[0003] This application claims the benefit of Korean Patent Application No. 10-2017-0135135, filed on October 18, 2017, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] The technical field relates to a display device and an operating method of the display device. Background Art

[0005] Display devices such as organic light emitting display devices can display images using organic light emitting diodes that generate light through the combination of electrons and holes. Organic light emitting display devices can have a high response speed and can operate with low power consumption.

[0006] The organic light emitting display device may display a target image by providing a data voltage in each pixel so that a corresponding organic light emitting diode emits light according to the data voltage. Summary of the Invention

[0007] Embodiments may relate to a display device capable of expressing a dimming level similar to a target dimming level with minimum switching power consumption of a dimming controller.Embodiments may relate to a driving method (ie, an operating method) of a display device.

[0008] Embodiments may relate to a display device having a satisfactory number of representable dimming levels and including a low-resolution display panel.Embodiments may relate to a driving method of a display device.

[0009] According to an embodiment, a display device may include the following elements: a pixel unit including a plurality of pixels; an emission control driver configured to supply an emission control signal for determining an emission period of the plurality of pixels; and a timing controller configured to determine a duty cycle of the emission control signal using a duty cycle bit stream configured with m bits, wherein the timing controller determines a duty cycle bit stream including mk most significant bits (MSBs) and k least significant bits (LSBs) having a fixed value during n frames, wherein k is a natural number of 1 or greater, and n and m are natural numbers of 2 or greater.

[0010] n can be 2 k .

[0011] Frames of a first group of n frames may be transmission-controlled to correspond to a duty cycle bit stream as a first duty cycle bit stream, and frames of a second group of n frames may be transmission-controlled to correspond to a duty cycle bit stream as a second duty cycle bit stream, and the first duty cycle bit stream and the second duty cycle bit stream are different.

[0012] The second duty cycle bit stream may have a value obtained by adding 2 to the value of the first duty cycle bit stream. k The value obtained.

[0013] The frames of the first group and the frames of the second group may be alternately arranged in time division.

[0014] During n frames, the mk MSBs of the average value of the duty cycle bit stream may correspond to the mk MSBs of the first duty cycle bit stream.

[0015] According to an embodiment, a display device may include the following elements: a pixel unit including a plurality of pixels; an emission control driver configured to supply an emission control signal for determining an emission period of the plurality of pixels; and a timing controller configured to determine a duty cycle of the emission control signal using a duty cycle bit stream configured with m+k bits, wherein the timing controller determines a duty cycle bit stream including k highest extended bits replacing k LSBs, mk MSBs, and k LSBs having fixed values ​​during n frames, wherein k is a natural number of 1 or greater, and n and m are natural numbers of 2 or greater.

[0016] n can be 2 k .

[0017] Frames of a first group of n frames may be transmission-controlled to correspond to a duty cycle bit stream as a first duty cycle bit stream, and frames of a second group of n frames may be transmission-controlled to correspond to a duty cycle bit stream as a second duty cycle bit stream, and the first duty cycle bit stream and the second duty cycle bit stream are different.

[0018] The second duty cycle bit stream may have a value obtained by adding 2 to the value of the first duty cycle bit stream. k The value obtained.

[0019] The frames of the first group and the frames of the second group may be alternately arranged in time division.

[0020] During n frames, other bits except the k LSBs of the average value of the duty cycle bit stream may correspond to the most extended bit and the MSB of the first duty cycle bit stream.

[0021] According to an embodiment, a method for driving / operating a display device may include the following steps: supplying a control signal corresponding to a first duty cycle bit stream to an emission control driver through a timing controller; supplying an emission control signal having a duty cycle corresponding to the first duty cycle bit stream to a pixel unit through the emission control driver; supplying a control signal corresponding to a second duty cycle bit stream to the emission control driver through the timing controller, wherein the second duty cycle bit stream has a value obtained by increasing the value of the first duty cycle bit stream by 2. k and supplying an emission control signal having a duty cycle corresponding to the second duty cycle bit stream to the pixel unit through the emission control driver.

[0022] The sum of the number of frames corresponding to the first group in which the first duty cycle bit stream is controlled for transmission and the number of frames corresponding to the second group in which the second duty cycle bit stream is controlled for transmission may be n. k may be a natural number of 1 or greater, and n may be a natural number of 2 or greater.

[0023] n can be 2 k .

[0024] The frames of the first group and the frames of the second group may be alternately arranged in time division.

[0025] The k LSBs of the first duty cycle bit stream may be zero, and the k LSBs of the second duty cycle bit stream may be zero. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a diagram (eg, a block diagram) illustrating a display device according to an embodiment.

[0027] Figure 2 is a diagram (eg, a block diagram) illustrating a timing controller according to an embodiment.

[0028] Figure 3 is a diagram (eg, a circuit diagram) illustrating a pixel according to an embodiment.

[0029] Figure 4 is a diagram illustrating a method according to an embodiment Figure 3 Timing diagram of the pixel operation in .

[0030] Figure 5 is a diagram (eg, a block diagram) illustrating an emission control driver according to an embodiment.

[0031] Figure 6 is a diagram illustrating a method according to an embodiment Figure 5 A diagram (eg, a circuit diagram) of one stage of an emission control driver in FIG.

[0032] Figure 7 is a diagram illustrating a method according to an embodiment Figure 6 Diagram of the driver stage of the first driver in the stage.

[0033] Figure 8 is a diagram illustrating a method according to an embodiment Figure 6 Figure 1 shows a diagram of the driver stage of the third driver in the stage.

[0034] Figure 9 is a diagram illustrating the embodiment including Figure 5 Figure 2 shows a timing controller for the emission control driver.

[0035] Figure 10 is a diagram illustrating emission control according to an embodiment.

[0036] Figure 11 is a diagram illustrating emission control according to an embodiment. DETAILED DESCRIPTION

[0037] The exemplary embodiments are described in detail with reference to the accompanying drawings. The implementable embodiments may be implemented in various forms and are not limited to the exemplary embodiments.

[0038] Although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms can be used to distinguish one element from another. Therefore, the first element can be referred to as the second element without departing from the teachings of one or more embodiments. Describing an element as a "first" element does not require or imply the presence of a second element or other elements. Terms "first", "second", etc. may also be used herein to distinguish between elements of different categories or sets. For the sake of brevity, the terms "first", "second", etc. may represent "first type (or first set)", "second type (or second set)", etc., respectively.

[0039] The same or similar constituent elements will be denoted by the same reference numerals.

[0040] The term "coupled" may mean "electrically connected" or "not electrically connected through an intervening transistor."

[0041] Figure 1 is a diagram illustrating a display device according to an embodiment.

[0042] refer to Figure 1 , the display device 9 includes a timing controller 10 , a scan driver 20 , an emission control driver 30 , a data driver 40 and a pixel unit 50 .

[0043] The timing controller 10 converts the control signal and the image signals R, G, and B supplied from the outside to suit the specifications of the display device 9, and supplies the control signal CONT1 to the scan driver 20, supplies the control signal CONT3 to the emission control driver 30, and supplies the control signal CONT2 and the image signals R', G', and B' to the data driver 40. The control signals received by the timing controller 10 may include a horizontal synchronization signal Hsync and a vertical synchronization signal Vsync.

[0044] The scan driver 20 generates scan signals to be supplied to the plurality of scan lines S1, S2, ..., and Sn by receiving a control signal CONT1. In an embodiment, the scan driver 20 may sequentially supply the scan signals to the plurality of scan lines S1, S2, ..., and Sn. For example, the control signal CONT1 may include a gate start pulse and a plurality of gate clock signals, and the scan driver 20 may be configured in the form of a shift register to generate the scan signals in a manner that sequentially transmits the gate start pulse to the next stage circuit under the control of the gate clock signal.

[0045] The data driver 40 generates data voltages to be supplied to the plurality of data lines D1, D2, ..., and Dm by receiving the control signal CONT2 and the image signals R', G', and B'. The data voltages generated in units of pixel rows can be simultaneously applied to the plurality of data lines D1, D2, ..., and Dm according to the output control signal included in the control signal CONT2.

[0046] The pixel unit 50 may include a plurality of pixel circuits PX11, PX12, ..., PX1m, PX21, PX22, ..., PX2m, ..., PXn1, PXn2, ..., and PXnm. Each pixel may have a substantially identical pixel circuit structure. Each pixel circuit may be coupled to a corresponding data line and a corresponding scan line and receive a data voltage input in response to a scan signal. The emission control driver 30 may supply emission control signals for determining emission periods of the plurality of pixel circuits PX11, PX12, ..., PX1m, PX21, PX22, ..., PX2m, ..., PXn1, PXn2, ..., and PXnm to the emission control lines E1, E2, ..., and En. For example, each pixel circuit may include an emission control transistor, and the flow of current through the organic light emitting diode may be determined by turning the emission control transistor on / off, thereby controlling the emission of the organic light emitting diode.

[0047] Figure 2 is a diagram illustrating a timing controller according to an embodiment.

[0048] refer to Figure 2 , the timing controller 10 may include a dimming controller 110 and a signal converter 120 .

[0049] The dimming controller 110 can use the duty cycle bit stream duty[7:0] to determine the duty cycle of the emission control signal. Figure 2 In the following figures, for ease of description, it is assumed that the duty cycle bit stream duty[7:0] has 8 bits. In an embodiment, the duty cycle bit stream can be configured with m bits, thus being represented as duty[(m–1):0]. Here, m can be a natural number of 2 or greater.

[0050] The dimming controller 110 may include a transistor coupled to each bit signal line to represent the binary level of each bit, i.e., 0 or 1. For example, when the transistor is to be turned on, the binary level 1 can be represented by a specific voltage applied to the corresponding bit signal line. When the transistor is to be turned off, the binary level 0 can be represented by another voltage of the corresponding bit signal line. Existing open drain and open collector structures can be applied as the coupling structure of the transistor and the bit signal line. A pull-up resistor or a pull-down resistor can be coupled to this structure. Those skilled in the art can redesign various coupling relationships between the transistor and the bit signal line of the dimming controller 110.

[0051] In an embodiment, the dimming controller 110 may consume switching control power of all eight transistors to represent the duty cycle bit stream duty[7:0].

[0052] According to an embodiment, the k least significant bits (LSBs) in the duty cycle bit stream duty[7:0] may be maintained at a single / constant level / value during n frames. The k LSBs being fixed to a single / constant level / value may mean that the k LSBs are maintained at a binary level of 0, causing the transistors corresponding to the k LSBs in the dimming controller 110 to be continuously turned off (i.e., kept off) during n frames. In an embodiment, k may be a natural number of 1 or greater, and n may be a natural number of 2 or greater. In an embodiment, n may be 2 k .

[0053] For example, in Figure 2 In an embodiment, k may be 2 and n may be 4. In an embodiment, b1 and b0 corresponding to the LSB may be binary level 0 during four frames.

[0054] That is, the timing controller 10 may determine a duty cycle bit stream including (mk) most significant bits (MSBs) and k LSBs having fixed values ​​during n frames.

[0055] Therefore, switching control is not performed separately on the transistors corresponding to the LSBs, so that the power consumption of the dimming controller 110 can be reduced. Although switching control is not performed separately on the transistors corresponding to the LSBs, the MSB is partially changed so that emission control can be performed to indicate a dimming level equal to or similar to the target dimming level.

[0056] The signal converter 120 converts the received duty cycle bit stream duty[7:0] to suit the specification of the emission control driver 30 and supplies the converted duty cycle bit stream as part of the control signal CONT3 to the emission control driver 30. For example, the signal converter 120 may be a serializer.

[0057] The emission control driver 30 may generate an emission control signal having a duty cycle corresponding to the duty cycle bit stream duty[7:0] based on the received control signal CONT3 and supply (an instance / copy of) the generated emission control signal to the emission control lines E1, E2, . . . and En.

[0058] In an embodiment, for n frames, the timing controller 10 may determine a duty cycle bit stream including k most extended bits replacing k LSBs, (mk) MSBs, and k LSBs having fixed values. In this embodiment, the duty cycle bit stream may be configured as (m+k) bits.

[0059] For example, the timing controller 10 may use bit signal lines corresponding to k LSBs in the duty cycle bit stream duty[7:0] to represent k highest extended bits, and the k LSBs may be assumed to be 0 during n frames.

[0060] refer to Figure 2 , the first MSB of the duty cycle bit stream duty[7:0] is b7, but the LSBs b1 and b0 can be used as if they were b9 and b8, which are the most extended bits. In an embodiment, the LSBs b1 and b0 can be assumed to be 0. In an embodiment, all eight transistors of the dimming controller 110 are used, so that the number of dimming levels that can be represented can be increased without reducing the switching control power. In particular, this is effective with respect to low-resolution display panels.

[0061] In an embodiment, for n frames, the k LSBs may be assumed to be 0.

[0062] Figure 3 is a diagram illustrating a pixel according to an embodiment. Figure 4 is a diagram illustrating a method according to an embodiment Figure 3 Timing diagram of the pixel.

[0063] refer to Figure 3, the pixel PXij may include a plurality of transistors T1 , T2 and T3 , a storage capacitor Cst and an organic light emitting diode OLED.

[0064] In an embodiment, the circuitry of the pixel PXij is configured with P-type transistors. In an embodiment, the circuitry may include N-type transistors.

[0065] One end of the transistor T2 may be coupled to the data line Dj, and a gate terminal of the transistor T2 may be coupled to the scan line Si. The transistor T2 may be referred to as a scan transistor.

[0066] A gate terminal of the transistor T1 may be coupled to the other end of the transistor T2 , and one end of the transistor T1 may be coupled to a voltage source ELVDD. The transistor T1 may be referred to as a driving transistor.

[0067] The storage capacitor Cst may connect the gate terminal of the transistor T1 with one end.

[0068] One end of transistor T3 may be coupled to the other end of transistor T1, a gate terminal of transistor T3 may be coupled to emission control line Ei, and the other end of transistor T3 may be coupled to the anode of organic light emitting diode OLED. Transistor T3 may be referred to as an emission control transistor.

[0069] The cathode of the organic light emitting diode OLED may be coupled to a voltage source ELVSS.

[0070] refer to Figure 4 , when a scan signal having a low level is supplied through the scan line Si, the transistor T2 is turned on, and the data voltage DATA applied to the data line Dj is applied to the gate terminal of the transistor T1 through the turned-on transistor T2.

[0071] The storage capacitor Cst stores a voltage corresponding to a difference between the data voltage DATA and the voltage source ELVDD. Since the transistor T3 is in an off state, no current flows through the organic light emitting diode OLED even when the transistor T1 is turned on.

[0072] When a low-level emission control signal is supplied via the emission control line Ei, a driving current flows from the voltage source ELVDD through the transistors T1 and T3 to the organic light emitting diode OLED. Consequently, the organic light emitting diode OLED emits light with a brightness proportional to the magnitude of the driving current. In an embodiment, the magnitude of the driving current is proportional to the voltage maintained by the storage capacitor Cst.

[0073] The duty cycle of the emission control signal may be a ratio of the time (or duration) that the emission control signal having a low level flows through the emission control line Ei to the time (or duration) that the emission control signal having a high level flows through the emission control line Ei. For example, as the duty cycle of the emission control signal becomes higher, the time during which the emission control signal having a low level flows to allow the emission control transistor T3 to be turned on may become longer. As the duty cycle of the emission control signal becomes lower, the time during which the emission control signal having a high level flows to allow the emission control transistor T3 to be turned off / remained turned off may become longer.

[0074] In an embodiment, the duty cycle of the transmission control signal may be associated with a frame.

[0075] Figure 5 is a diagram illustrating an emission control driver according to an embodiment.

[0076] refer to Figure 5 , the emission control driver 30 ′ receives a plurality of clock signals CLK1 , CLK2 , and CLK3 and two start signals SP1 and SP2 as a control signal CONT3 , and includes a plurality of stages 321 , 322 , 323 , 324 , 325 , . . .

[0077] The plurality of stages 321 , 322 , 323 , 324 , 325 , . . . may be coupled to emission control lines E1 , E2 , E3 , E4 , E5 , . . . , respectively.

[0078] Each of the stages 322 , 323 , 324 , 325 , . . . receives the output signals OS1 and OS2 output from the previous stage thereof as an activation signal.

[0079] In an embodiment, the clock signal CLK2 is supplied to all of the stages 321 , 322 , 323 , 324 , 325 , . . . , the clock signal CLK1 is supplied to the odd stages 321 , 323 , 325 , . . . , and the clock signal CLK3 is supplied to the even stages 322 , 324 , .

[0080] The clock signals CLK1 , CLK2 , and CLK3 may be set to have the same period, and the first start signal SP1 and the second start signal SP2 may be supplied once or a plurality of times during one frame period.

[0081] According to an embodiment, the width of the emission control signal may be determined corresponding to the width (or interval / distance) between the first start signal SP1 and the second start signal SP2 (i.e., the time from the first start signal SP1 to the second start signal SP2 having a low level after the first start signal SP1 has a low level). For example, as the width between the first start signal SP1 and the second start signal SP2 is set wider, the duty cycle of the emission control signal may become lower. For example, as the width between the first start signal SP1 and the second start signal SP2 is set narrower, the duty cycle of the emission control signal may become higher.

[0082] The width between the first output signal OS1 and the second output signal OS2 output from the first stage 321 may correspond to the width between the first start signal SP1 and the second start signal SP2. Therefore, the other stages 322, 323, 324, 325, ... may all have the same duty cycle of the emission control signal as the duty cycle of the emission control signal associated with the first stage 321.

[0083] Figure 6 is a diagram illustrating a method according to an embodiment Figure 5 Diagram of one stage of an emission control driver. Figure 7 is a diagram illustrating a method according to an embodiment Figure 6 Figure 1 shows the driving / operation phase of the first driver in the stage. Figure 8 is a diagram illustrating a method according to an embodiment Figure 6 FIG4 is a diagram of the driving / operating phase of the third driver in the stage.

[0084] refer to Figure 6 , illustrates a circuit of the first stage 321 of the emission control driver 30'. Except for connections related to input signals, the circuit configurations of the other stages 322, 323, 324, 325, ... may be substantially the same as that of the first stage 321, and therefore the first stage 321 is described as an example of all these stages.

[0085] The first stage 321 may include a first driver 3211 , a second driver 3212 , and a third driver 3213 .

[0086] The first driver 3211 may generate a first output signal OS1 using the clock signals CLK1 and CLK2 and the first start signal SP1 .

[0087] The second driver 3212 may generate a second output signal OS2 using the clock signals CLK1 and CLK2 and the second start signal SP2 . A circuit configuration of the second driver 3212 may be the same as that of the first driver 3211 .

[0088] The third driver 3213 may generate an emission control signal using the first and second output signals OS1 and OS2 .

[0089] The first driver 3211 outputs the voltage of the voltage source VDD or the clock signal CLK1 as the first output signal OS1. In an embodiment, the first driver 3211 includes six transistors M11 to M16 and two capacitors C11 and C12.

[0090] The voltage source VDD is set to a voltage higher than that of the voltage source VSS. For example, the voltage source VDD may be set to a voltage at which the transistor can be turned off, and the voltage source VSS may be set to a voltage at which the transistor can be turned on.

[0091] One terminal of the transistor M15 is coupled to the voltage source VDD, and the other terminal of the transistor M15 is coupled to the output terminal out1. In addition, a gate terminal of the transistor M15 is coupled to the node N11.

[0092] One end of the transistor M16 is coupled to the output terminal out1, and the other end of the transistor M16 is coupled to the input terminal 36. In addition, the gate terminal of the transistor M16 is coupled to the node N12. The input terminal 36 is supplied with the clock signal CLK1.

[0093] One end of the transistor M14 is coupled to the node N11, and the other end of the transistor M14 is coupled to the voltage source VSS. In addition, the gate terminal of the transistor M14 is coupled to the input terminal 35. The input terminal 35 is supplied with the clock signal CLK2.

[0094] One terminal of the transistor M13 is coupled to the voltage source VDD, and the other terminal of the transistor M13 is coupled to the node N12. In addition, a gate terminal of the transistor M13 is coupled to the node N11.

[0095] One end of the transistor M12 is coupled to the voltage source VDD, and the other end of the transistor M12 is coupled to the node N11. In addition, the gate terminal of the transistor M12 is coupled to the input terminal 33. The input terminal 33 is supplied with the first start signal SP1.

[0096] One end of the transistor M11 is coupled to the node N12 , and the other end of the transistor M11 is coupled to the voltage source VSS. In addition, a gate terminal of the transistor M11 is coupled to the input terminal 33 .

[0097] The capacitor C11 is coupled between the gate terminal of the transistor M15 and the voltage source VDD, and is charged with a voltage corresponding to whether the transistor M15 is turned on or off.

[0098] The capacitor C12 is coupled between the gate terminal of the transistor M16 and the output terminal out1 , and is charged with a voltage corresponding to whether the transistor M16 is turned on or off.

[0099] In an embodiment, the configuration of the second driver 3212 is the same as that of the first driver 3211, except that the second start signal SP2 is supplied to the input terminal 33'. Therefore, the description common to the first and second drivers 3211 and 3212 will not be repeated.

[0100] Figure 7 is a diagram illustrating an operation process of the first driver 3211 according to an embodiment.

[0101] refer to Figure 6 and Figure 7 The operation process is described. When the first start signal SP1 is supplied at a low level, the transistor M11 and the transistor M12 are turned on.

[0102] When transistor M11 is turned on, the voltage of voltage source VSS is supplied to node N12. When the voltage of voltage source VSS is supplied to node N12, transistor M16 is turned on. When transistor M16 is turned on, input terminal 36 is coupled to output terminal out1. In addition, the voltage corresponding to the conduction of transistor M16 is charged in capacitor C12.

[0103] In an embodiment, when the transistor M12 is turned on, the voltage of the voltage source VDD is supplied to the node N11. When the voltage of the voltage source VDD is supplied to the node N11, the transistors M13 and M15 are turned off.

[0104] Subsequently, the first start signal SP1 is supplied at a high level. When the first start signal SP1 is supplied at a high level, transistors M11 and M12 are turned off. At this time, due to the voltage charged in capacitor C12, transistor M16 remains in an on state. During the period in which transistor M16 remains in an on state, clock signal CLK1 is supplied to output terminal out1.

[0105] After the clock signal CLK1 is supplied, the clock signal CLK2 is supplied. When the clock signal CLK2 is supplied, the transistor M14 is turned on. When the transistor M14 is turned on, the voltage of the voltage source VSS is supplied to the node N11. When the voltage of the voltage source VSS is supplied to the node N11, the transistors M13 and M15 are turned on.

[0106] When transistor M13 is turned on, voltage source VDD is coupled to node N12. Therefore, transistor M16 is turned off. When transistor M15 is turned on, voltage source VDD is coupled to output terminal out1. At this time, capacitor C11 is charged with a voltage corresponding to the turn-on of transistor M15. In an embodiment, transistor M15 supplies the voltage of voltage source VDD to output terminal out1 until transistor M12 is turned on by the next first start signal SP1.

[0107] As described above, after the first start signal SP1 is supplied, the first driver 3211 supplies the next clock signal CLK1 (low level) to the output terminal out1. Similarly, when the second start signal SP2 is supplied, the second driver 3212 supplies the next clock signal CLK1 to the output terminal out2. Therefore, the interval between the first output signal OS1 and the second output signal OS2 outputted from the first driver 3211 and the second driver 3212, respectively, corresponds to the interval between the first start signal SP1 and the second start signal SP2.

[0108] refer to Figure 6 The configuration of the third driver 3213 is described.

[0109] In the third driver 3213 , a voltage source VDD or a voltage source VSS is coupled to the output terminal out3 corresponding to the first and second output signals OS1 and OS2 . In an embodiment, the third driver 3213 includes six transistors M1 to M6 and two capacitors C1 and C2 .

[0110] One terminal of the transistor M1 is coupled to the voltage source VDD, and the other terminal of the transistor M1 is coupled to the output terminal out3. In addition, a gate terminal of the transistor M1 is coupled to the node N1.

[0111] One end of the transistor M2 is coupled to the output terminal out3 , and the other end of the transistor M2 is coupled to the voltage source VSS .

[0112] One terminal of the transistor M3 is coupled to the voltage source VDD, and the other terminal of the transistor M3 is coupled to the node N1. In addition, a gate terminal of the transistor M3 is coupled to the node N2.

[0113] The capacitor C1 is coupled between the gate terminal of the transistor M2 and the output terminal out3 , and stores a voltage corresponding to whether the transistor M2 is turned on or off.

[0114] The capacitor C2 is coupled between the gate terminal of the transistor M1 and the voltage source VDD. The capacitor C2 is charged with a voltage corresponding to whether the transistor M1 is turned on or off.

[0115] One end of the transistor M5 is coupled to the voltage source VDD, and the other end of the transistor M5 is coupled to the node N2. In addition, the gate terminal of the transistor M5 is coupled to the input terminal 37. The input terminal 37 is supplied with the first output signal OS1.

[0116] One end of the transistor M6 is coupled to the node N2, and the other end of the transistor M6 is coupled to the voltage source VSS. In addition, the gate terminal of the transistor M6 is coupled to the input terminal 38. The input terminal 38 is supplied with the second output signal OS2.

[0117] One end of the transistor M4 is coupled to the node N1, and the other end of the transistor M4 is coupled to the voltage source VSS. In addition, the gate terminal of the transistor M4 is coupled to the input terminal 37. The fourth transistor M4 is turned on or off according to the voltage supplied to the input terminal 37.

[0118] Figure 8 is a diagram illustrating an operation process of the third driver 3213 according to an embodiment.

[0119] When the first output signal OS1 having a low level is supplied to the input terminal 37, the transistor M4 and the transistor M5 are turned on. At this time, since the input terminal 38 is supplied with a high level voltage, the transistor M6 is turned off.

[0120] When the transistor M5 is turned on, the voltage of the voltage source VDD is supplied to the node N2. In an embodiment, the transistor M2 and the transistor M3 coupled to the node N2 are turned off.

[0121] When transistor M4 is turned on, the voltage of voltage source VSS is supplied to node N1. In an embodiment, transistor M1 coupled to node N1 is turned on. When transistor M1 is turned on, the voltage of voltage source VDD is supplied to output terminal out3. Therefore, the emission control signal having a high level is supplied to emission control line E1 coupled to output terminal out3.

[0122] In the embodiment, the capacitor C2 is charged with a voltage corresponding to the turn-on of the transistor M1, and the capacitor C1 is charged with a voltage corresponding to the turn-off of the transistor M2. Therefore, as a high-level voltage is supplied to the input terminal 37, even when the transistors M4 and M5 are turned off, the voltage of the voltage source VDD is supplied to the output terminal out3 while the transistor M1 is maintained in the on state and the transistor M2 is maintained in the off state.

[0123] Subsequently, as the second output signal OS2 having a low level is supplied to the input terminal 38, the transistor M6 is turned on. At this time, as the high level voltage is supplied to the input terminal 37, the transistor M4 and the transistor M5 are in a turned-off state.

[0124] When the transistor M6 is turned on, the voltage of the voltage source VSS is supplied to the node N2. In an embodiment, the transistor M3 and the transistor M2 coupled to the node N2 are turned on.

[0125] When transistor M3 is turned on, the voltage of voltage source VDD is supplied to node N1. In an embodiment, transistor M1 coupled to node N1 is turned off. When transistor M2 is turned on, the voltage of voltage source VSS is supplied to output terminal out3. Therefore, the emission control signal having a low level is supplied to emission control line E1 coupled to output terminal out3.

[0126] Figure 9 is a diagram including reference according to an embodiment Figure 5 Diagram of the timing controller for the emission control driver discussed.

[0127] refer to Figure 9 ,and Figure 2 Similarly, the timing controller 10 includes a dimming controller 110 and a signal converter 120'. The signal converter 120' is configured to be suitable for the configuration of the emission control driver 30'.

[0128] The signal converter 120' can supply the second start signal SP2 having a low level so that the duty cycle of the emission control signal corresponds to the duty cycle bit stream duty[7:0]. As described above, the duty cycle of the emission control signal can be controlled by controlling the interval between the first start signal SP1 having a low level and the second start signal SP2 having a low level.

[0129] The control of the duty cycle bit stream duty[7:0] performed by the dimming controller 110 may have a Figure 2 The features discussed are substantially the same or similar features, and therefore the related descriptions are not repeated.

[0130] Figure 10 is a diagram illustrating emission control according to an embodiment.

[0131] refer to Figure 10 , the frames can be separated based on the vertical synchronization signal Vsync. The emission control driver 30 can be implemented in the form of a shift register, and an emission control signal having a pulse form substantially the same as that of the emission control signal from the first stage 321 can be sequentially output from the next stage. Figures 5 to 8 The described emission control driver 30 ′ may be an example of the emission control driver 30 .

[0132] refer to Figure 10 , the timing controller 10 uses all of the LSB and MSB of the duty cycle bit stream duty[7:0] to determine the duty cycle. Figure 10In , the LSB set is represented by 2'b10 (ie, b1=1 and b0=0).

[0133] Since information on all bits of the duty cycle bit stream duty[7:0] is required, all transistors coupled to corresponding bit signal lines of the dimming controller 110 need to be driven, and switching power of the dimming controller 110 is not reduced.

[0134] Figure 11 is a diagram illustrating emission control according to an embodiment.

[0135] In an embodiment, k is 2 and n is 4.

[0136] refer to Figure 11 , the timing controller 10 uses (mk) MSBs in the duty cycle bit stream duty[7:0] instead of k LSBs to determine the duty cycle. That is, the timing controller 10 uses six MSBs instead of two LSBs to determine the duty cycle.

[0137] The dimming controller 110 does not control the switching of the transistors coupled to the bit signal lines corresponding to the two LSBs. In an embodiment, a default voltage corresponding to binary level 0 may be applied to the bit signal lines corresponding to the LSBs. Therefore, the switching control power consumption of the transistors corresponding to the LSBs in the timing controller 10 can be reduced.

[0138] Since the timing controller 10 does not use the LSB, Figure 10 Duty cycles equivalent / equal in duty cycle will be represented using only the MSB. In an embodiment, the MSB can be represented using a first duty cycle bit stream duty1[7:0] and a second duty cycle bit stream duty2[7:0] that are different from each other. Figure 10 The duty cycle is equal to or similar to the duty cycle of the MOSFET.

[0139] A first group of frames among the n frames may be controlled for transmission according to a first duty cycle bit stream duty1[7:0], and a second group of frames among the n frames may be controlled for transmission according to a second duty cycle bit stream duty2[7:0].

[0140] To reduce switching power consumption, LSBs of the first duty cycle bit stream duty1 [7:0] and the second duty cycle bit stream duty2 [7:0] are not used, and thus, each LSB may be set to 0.

[0141] For n frames, if Figure 11 The total emission time and total non-emission time associated with Figure 10 The total emission time and total non-emission time associated with Figure 11 Associated configuration to indicate equal or close Figure 10 That is, when the overall duty cycle of Figure 11 For the four frames shown, the sum of the time (C*2) during which the emission control transistor is turned off by the first duty cycle bit stream duty1[7:0] and the time (B*2) during which the emission control transistor is turned off by the second duty cycle bit stream duty2[7:0] is equal to Figure 10 For the four frames shown, the same dimming level can be represented when the emission control transistor is turned off by the duty cycle bit stream duty[7:0] for a period of time (A*4). That is, during n frames, the (mk) MSBs of the average value of the duty cycle bit stream can correspond to the (mk) MSBs of the first duty cycle bit stream, and the dimming level is equal to or close to Figure 10 dimming level.

[0142] In an embodiment, the second duty cycle bit stream duty2[7:0] may have a value that is obtained by adding 2 to the value of the first duty cycle bit stream duty1[7:0]. k Since the duty cycle bit stream has k LSBs, even if you increase the value by 2 k (Decimal number representation), the LSB value does not change. Figure 11 In the associated configuration, since k is 2, the second duty cycle bit stream duty2[7:0] has a value obtained by adding 4 (decimal representation) to the value of the first duty cycle bit stream duty1[7:0].

[0143] In an embodiment, the second duty cycle bit stream duty2[7:0] may have a value greater than 2 added to the value of the first duty cycle bit stream duty1[7:0]. k The value obtained by the value of .

[0144] In an embodiment, the frames of the first group and the frames of the second group may be alternately arranged / arranged in time division. Thus, dithering is achieved, and thus it is possible to provide an image that is smoothly viewed by a user who is sensitive to brightness changes.

[0145] In an embodiment, the LSB set is 2'b10 (ie, b1=1 and b0=0), and for four frames, two second duty cycle bit streams duty2[7:0] and two first duty cycle bit streams duty1[7:0] may be provided.

[0146] In an embodiment, the LSB set is 2'bl 1 (ie, bl = 1 and b0 = 1), and for four frames, three second duty cycle bit streams duty2[7:0] and one first duty cycle bit stream duty1[7:0] may be provided.

[0147] In an embodiment, the LSB set is 2'b01 (ie, b1=0 and b0=1), and for four frames, one second duty cycle bit stream duty2[7:0] and three first duty cycle bit streams duty1[7:0] may be provided.

[0148] In an embodiment, the LSB set is 2'b00 (ie, b1=0 and b0=0), and for four frames, zero second duty cycle bit streams duty2[7:0] and four first duty cycle bit streams duty1[7:0] may be provided and with Figure 10 The duty cycle bit stream associated with the configuration can be equivalent to Figure 11 The configuration is associated with the duty cycle bit stream.

[0149] As an example, parameter values ​​k = 2, n = 4, and m = 8 are given. The parameter values ​​may be configured according to a specific embodiment (eg, a specific product and / or operating environment).

[0150] In the display device and the driving method thereof according to the embodiment, a dimming level similar to the target dimming level may be expressed with minimum switching power consumption of the dimming controller.

[0151] In the display device and the driving / operating method thereof according to the embodiment, the number of dimming levels representable in a low-resolution display panel can be maximized.

[0152] Example embodiments have been described. Although specific terms are employed, they are to be interpreted in a generic and descriptive sense only and not for purposes of limitation. In some cases, features, characteristics, and / or elements described in conjunction with a particular embodiment may be used alone or in combination with features, characteristics, and / or elements described in conjunction with other embodiments, unless expressly stated otherwise. Various changes in form and detail may be made to the described embodiments without departing from the spirit and scope of the appended claims.

Claims

1. A display device, comprising: a pixel comprising a drive transistor, an emission control transistor, and a light-emitting element; an emission control driver configured to supply an emission control signal for determining an emission period and a non-emission period of the pixel; as well as a timing controller configured to determine a duty cycle of the emission control signal based on a duty cycle bit stream configured with a plurality of bits, wherein the timing controller receives a first synchronization pulse, receives a second synchronization pulse, and determines the duty cycle by using a portion of the plurality of bits of the duty cycle bit stream, wherein the second synchronization pulse follows the first synchronization pulse, and there is no intervening synchronization pulse between the first synchronization pulse and the second synchronization pulse, wherein the non-emission period of the pixel during the first frame has a first length and is located between the first synchronization pulse and the second synchronization pulse, wherein the non-emission period of the pixel during the second frame has a second length, wherein the second synchronization pulse is located between the non-emission period of the pixel during the first frame and the non-emission period of the pixel during the second frame, wherein the first length is different from the second length, wherein the emission control transistor is connected between the driving transistor and the light emitting element, and A gate terminal of the emission control transistor receives the emission control signal.

2. The display device according to claim 1, wherein the plurality of bits of the duty cycle bit stream is m bits, wherein the portion of bits are the mk most significant bits of the duty cycle bit stream, and wherein k is a natural number of 1 or greater, and m is a natural number of 2 or greater.

3. The display device according to claim 1, wherein the first length is determined by a first duty cycle bit stream, and The second length is determined by a second duty cycle bit stream.

4. The display device according to claim 3, wherein The second duty cycle bit stream has a value obtained by adding 2 to the first duty cycle bit stream. k The value obtained, and Wherein k is a natural number that is 1 or greater than 1.

5. The display device according to claim 4, wherein The first frames and the second frames are alternately arranged in time division. The display device according to claim 2 , wherein: The mk most significant bits of an average value of the duty cycle bit stream during consecutive frames correspond to the mk most significant bits of the first duty cycle bit stream determining the first length.

7. A method for driving a display device, the method comprising: determining, by a timing controller, a first duty cycle of an emission control signal by using a portion of a plurality of bits of a first duty cycle bit stream, the emission control signal determining an emission period and a non-emission period of a pixel, wherein the timing controller receives a first synchronization pulse and a second synchronization pulse; The timing controller supplies a control signal corresponding to the first duty cycle to an emission control driver; During a first frame, the emission control driver supplies the emission control signal corresponding to the first duty cycle to the pixel; determining, by the timing controller, a second duty cycle of the emission control signal by using a portion of the plurality of bits of the second duty cycle bit stream; The timing controller supplies a control signal corresponding to the second duty cycle to the emission control driver; as well as During a second frame, the emission control driver supplies the emission control signal corresponding to the second duty cycle to the pixel. wherein the second synchronization pulse follows the first synchronization pulse, and there is no intervening synchronization pulse between the first synchronization pulse and the second synchronization pulse, wherein a non-emission period of the pixel during the first frame has a first length and is located between the first synchronization pulse and the second synchronization pulse, wherein the non-emission period of the pixel during the second frame has a second length, wherein the second synchronization pulse is located between the non-emission period of the pixel during the first frame and the non-emission period of the pixel during the second frame, and The first length is different from the second length.

8. The method according to claim 7, wherein the plurality of bits of each of the first duty cycle bit stream and the second duty cycle bit stream is m bits, wherein the portion of bits of each of the first duty cycle bit stream and the second duty cycle bit stream is mk most significant bits, and wherein k is a natural number of 1 or greater, and m is a natural number of 2 or greater.

9. The method according to claim 7, wherein: The first frames and the second frames are alternately arranged in time division.

10. The method according to claim 8, wherein The mk most significant bits of an average value of the duty cycle bit stream during consecutive frames correspond to the mk most significant bits of the first duty cycle bit stream determining the first length.

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