Data processing method for data storage of in-chip one-time-programmable memory

Abstract

A data processing method for data storage of in-chip one-time-programmable memory, the chip comprising a plurality of cores. The data processing method comprises: obtaining a plurality of data respectively corresponding to the plurality of cores, and obtaining a first reference value for the plurality of data; for a first core in the plurality of cores, obtaining a first data value corresponding to the first core in the plurality of data, and obtaining a first difference value based on a difference between the first data value and the first reference value; for each second core in the plurality of cores except the first core: obtaining a second data value corresponding to each second core in the plurality of data, and obtaining a second difference value based on a difference between the first data value and the second data value. The first difference value corresponding to the first core and the corresponding second difference value corresponding to each second core are respectively stored in the one-time-programmable memory. The data processing method can reduce the storage space of data in the in-chip one-time-programmable memory, and save storage resources.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to a data processing method for data storage of in-chip one-time programmable memory. BACKGROUND

[0002] One-time programmable (OTP) memory is a kind of non-volatile memory similar to erasable programmable read-only memory (EPROM), and data (e.g., data, code, signal, etc.) can be programmed into the OTP memory by using a high voltage of a programming tool. Compared with multi-time programmable devices, the programming process of the OTP memory is irreversible, and thus the OTP memory can be applied to applications where programs or data are fixed. SUMMARY

[0003] At least one embodiment of the present disclosure provides a data processing method for data storage of in-chip one-time programmable memory, and the chip includes a plurality of cores. The data processing method includes: obtaining a plurality of data corresponding to the plurality of cores, and obtaining a first reference value for the plurality of data; for a first core in the plurality of cores, obtaining a first data value corresponding to the first core in the plurality of data, and obtaining a first difference value based on a difference between the first data value and the first reference value; for each second core in the plurality of cores except the first core: obtaining a second data value corresponding to each second core in the plurality of data, and obtaining a second difference value based on a difference between the first data value and the second data value. The first difference value corresponding to the first core and the corresponding second difference value corresponding to each second core are respectively stored in the one-time programmable memory. The data processing method can reduce the storage space of data in the in-chip one-time programmable memory, and save storage resources.

[0004] For example, in the data processing method provided by at least one embodiment of the present disclosure, the obtaining of the first reference value for the plurality of data includes determining the first reference value based on a distribution of the plurality of data. In some embodiments, the first reference value can be a mean value of a normal distribution of the plurality of data corresponding to the plurality of cores.

[0005] For example, the data processing method provided by at least one embodiment of the present disclosure further includes: storing the first reference value into the chip.

[0006] For example, in the data processing method provided by at least one embodiment of the present disclosure, the storing of the first difference value corresponding to the first core and the corresponding second difference value corresponding to each second core in the one-time programmable memory includes: converting the first difference value and the second difference value into integers respectively; converting the integers obtained by the conversion into binary codes; and storing the binary codes obtained by the conversion in the one-time programmable memory.

[0007] For example, the data processing method provided by at least one embodiment of the present disclosure further includes: after obtaining a first difference value based on a difference between the first data value and the first reference value, rounding the first difference value; and / or after obtaining a second difference value based on a difference between the first data value and the second data value, rounding the second difference value.

[0008] For example, in the data processing method provided by at least one embodiment of the present disclosure, the rounding includes: directly removing a decimal part of the first difference value.

[0009] At least one embodiment of the present disclosure further provides a data processing method for an in-chip one-time-programmable memory, the chip comprising a plurality of cores. The data processing method comprises: reading a first difference value and at least one second difference value from the one-time-programmable memory, wherein the first difference value corresponds to a first core of the plurality of cores, and each of the at least one second difference value corresponds to a respective second core of at least one second core other than the first core of the plurality of cores; obtaining a first reference value; for the first core, obtaining a first data value corresponding to the first core based on a sum of the first difference value and the first reference value; and for each of the at least one second core other than the first core of the plurality of cores, obtaining a second data value corresponding to the respective second core based on a sum of the first difference value, the second difference value and the first reference value.

[0010] For example, in the data processing method provided by at least one embodiment of the present disclosure, reading the first difference value and the at least one second difference value from the one-time-programmable memory comprises: decoding binary codes corresponding to the first difference value and the second difference value to obtain integers corresponding to the first difference value and the second difference value, respectively; and converting the integers corresponding to the first difference value and the second difference value into the first difference value and the second difference value, respectively.

[0011] At least one embodiment of the present disclosure further provides a chip comprising a plurality of cores and a one-time-programmable memory. A first difference value corresponding to a first core of the plurality of cores and a respective second difference value corresponding to each second core other than the first core of the plurality of cores are stored in the one-time-programmable memory. The first difference value is obtained by a first data value corresponding to the first core and based on a difference between the first data value and a first reference value; and the second difference value is obtained by a second data value corresponding to the each second core and based on a difference between the first data value and the second data value.

[0012] The electronic device includes a memory and at least one processor. The memory has instructions stored thereon that, when executed by the at least one processor, can implement the data processing method provided by any of the embodiments of the present disclosure.

[0013] The electronic device includes a memory and at least one processor. The memory has instructions stored thereon that, when executed by the at least one processor, can implement the data processing method provided by any of the embodiments of the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0014] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings described below only relate to some of the embodiments of the present disclosure, and not limit the present disclosure.

[0015] Figure 1 A schematic diagram of a one-time programmable memory (OTP) chip mounted on a printed circuit board is shown.

[0016] Figure 2 A schematic diagram of a multi-core AI chip according to at least one embodiment of the present disclosure is shown.

[0017] Figure 3 A flowchart of a data processing method for data storage of an in-chip one-time programmable memory according to at least one embodiment of the present disclosure is shown.

[0018] Figure 4 A flowchart of another data processing method for data storage of an in-chip one-time programmable memory according to at least one embodiment of the present disclosure is shown.

[0019] Figure 5 A flowchart of a storage method for storing data into a one-time programmable memory according to at least one embodiment of the present disclosure is shown.

[0020] Figure 6 A schematic diagram of an example multi-core chip for storing temperature calibration parameters is shown.

[0021] Figure 7 A schematic diagram of an electronic device according to an embodiment of the present disclosure is shown.

[0022] Figure 8 A schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0023] In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will be combined with the drawings of the embodiments of the present disclosure to make a clear and complete description of the technical solutions of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without any inventive effort fall within the protection scope of the present disclosure.

[0024] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meaning understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different components. The terms "comprise", "contain", and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right", and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0025] Some embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. In order to keep the following description of the embodiments of the present disclosure clear and brief, detailed descriptions of known functions and known components can be omitted. When any component of the embodiments of the present disclosure appears in more than one figure, the component is denoted by the same or similar reference numeral in each figure.

[0026] As described above, the One Time Programmable (OTP) memory has the characteristic that the programming process is irreversible, and thus can be suitable for applications where the program or data is fixed. For example, in order to calibrate the parameters of a chip, an OTP memory and a register can be added to the chip, the values determined after debugging are programmed into the OTP memory, and the values programmed into the OTP are loaded into the register after the chip is powered on, to complete the calibration of the parameters, thereby providing great convenience and flexibility for subsequent development verification and mass production of the chip. However, in order to save costs, the data in the OTP memory after programming is no longer erasable or rewritable.

[0027] Figure 1 An OTP memory chip mounted on a printed circuit board (PCB) is shown. As Figure 1As shown, the OTP memory chip can be connected through a programming interface reserved on the PCB to program it, i.e. to burn the desired code into the OTP memory chip, which, as mentioned above, cannot be erased or rewritten. Due to the above-mentioned characteristics of the OTP memory, it is applied in various different fields, for example, data solidification for artificial intelligence (AI) chips.

[0028] With the wide application of AI chips, the number of computing cores mounted therein is increasing, for example, general-purpose graphics processing units (GPGPUs), AI accelerators, tensor processors, etc. Figure 2 An example of a multi-core AI chip 200 is shown, which includes 8 (i.e. 2*4) cores 210A-210H, each of which will need to store some data after performing a calculation, so that the next time the AI chip 200 is powered on, it can be directly invoked, which can save power-on time and improve efficiency. In an embodiment, each core in the AI chip can correspond to a computing module 220A-220H. The computing modules 220A-220H are called multiple times when performing, for example, general matrix multiplication (GEMM), for example, 3 times, so the data in these computing modules 220A-220H needs to be stored in, for example, one-time programmable (OTP) memory storage units to store solidified data.

[0029] For example, AI chips, due to the significant increase in demand for computing, the number of computing cores is increasing, and the amount of data to be stored in the OTP memory is also increasing. The demand for storage space of the OTP memory is also increasing. However, the storage cost of different OTP memories is different. Generally speaking, the larger the storage space of the OTP memory, the higher the storage cost of the chip, and thus the greater the cost of storing solidified data.

[0030] To at least address the above problems, at least one embodiment of the present disclosure provides a data processing method for data storage of in-chip one-time programmable memory. The chip comprises a plurality of cores. The data processing method comprises: obtaining a plurality of data respectively corresponding to the plurality of cores, and obtaining a first reference value for the plurality of data; for a first core in the plurality of cores, obtaining a first data value in the plurality of data corresponding to the first core, and obtaining a first difference value based on a difference between the first data value and the first reference value; for each second core in the plurality of cores except the first core: obtaining a second data value in the plurality of data corresponding to each second core, and obtaining a second difference value based on a difference between the first data value and the second data value. The first difference value corresponding to the first core and the corresponding second difference value corresponding to each second core are respectively stored in the one-time programmable memory. The data processing method can more efficiently store data, save storage resources, and at the same time reduce the storage space of data in the in-chip one-time programmable memory, thereby reducing the requirement for the size of the storage space of the OTP memory.

[0031] Figure 3 A flowchart of a data processing method for data storage of in-chip one-time programmable memory according to at least one embodiment of the present disclosure is shown. The data processing method shown in Figure 2 will be described in detail below. Figure 3 .

[0032] As shown in Figure 3 , the data processing method can comprise the following steps S310, S320 and S330.

[0033] Step S310: obtaining a plurality of data respectively corresponding to the plurality of cores 210A-210H, and obtaining a first reference value for the plurality of data. In some embodiments, obtaining the first reference value for the plurality of data can comprise a reference value determined based on the distribution of the plurality of data. For example, when the plurality of data corresponding to the plurality of cores follows a normal distribution, in this case, since the values of the plurality of data following the normal distribution have a certain range but the mean value is fixed, the first reference value can be the mean value of the normal distribution of the plurality of data. In other examples, the plurality of data respectively corresponding to the plurality of cores follows other distribution rules, then the first reference value can be a certain value corresponding to the other distribution, which can be set by experience or determined after measurement.

[0034] Step S320: For a first core of the plurality of cores, obtaining a first data value of the plurality of data corresponding to the first core, and obtaining a first difference value based on a difference between the first data value and a first reference value. The first core can be any one of the plurality of cores 210A-210H, for example, core 210A, 210B or 210E, etc. For the purpose of clarity and brevity, the following will be described with core 210A as the first core, but it should be understood that this is illustrative but not limiting, and in other examples, any other core other than core 210A can also be used as the first core.

[0035] Step S330: For each second core of the plurality of cores other than the first core 210A: obtaining a second data value of the plurality of data corresponding to each second core, and obtaining a second difference value based on a difference between the first data value and the second data value. In the example where core 210A is the first core, each second core other than the first core 210A includes each of cores 210B to 210H.

[0036] Step 340: Storing the first difference value corresponding to the first core 210A and the respective second difference value corresponding to each second core (i.e., each of cores 210B to 210H) in the one-time programming memory, respectively.

[0037] Compared to directly storing the respective first data value corresponding to the first core and the respective second data value corresponding to each second core, as Figure 3 The data processing method shown by storing the difference value instead of the original data value can effectively reduce the number of bits required to store the data, thereby reducing the storage space required to store these data in the OTP, saving costs.

[0038] In at least yet another embodiment of the present disclosure, the data processing method shown by Figure 3 may further include the following step S350.

[0039] Step S35: Storing the first reference value into the chip 200 to facilitate subsequent retrieval when restoring the data.

[0040] Figure 4 A flowchart of yet another data processing method for data storage of an in-chip one-time programming memory according to at least one embodiment of the present disclosure is shown. As Figure 4 shown, the data processing method can include the following steps S410, S420, S430 and S440.

[0041] Step S410: Obtaining a plurality of data corresponding to a plurality of cores, respectively, and obtaining a first reference value for the plurality of data. Step S410 is similar to step S310 in the above Figure 3 , please refer to the description of step S310 above, which will not be repeated here.

[0042] Step S420: For the first core among the plurality of cores, obtain a first data value corresponding to the first core among the plurality of data, and obtain a first difference value based on a difference between the first data value and the first reference value. Step S420 is similar to step S320 in the above Figure 3 described above with respect to step S320, which will not be repeated here.

[0043] Step S430: Round the first difference value. The rounding can include directly removing the decimal part of the first difference value, for example, the rounded first difference value obtained by rounding the first difference value 9.6 can be 9. In some embodiments of the present disclosure, directly removing the decimal part of the first difference value can include directly removing the decimal part of the first difference value by rounding, for example, in the above example, the rounded first difference value obtained by rounding the first difference value 9.6 can be 10. In some other embodiments of the present disclosure, the first difference value can also be multiplied by a corresponding positive integer power of 10 to convert it into an integer according to the number of digits of the decimal part of the first difference value. For example, when the first difference value is 9.6, the first difference value 9.6 can be multiplied by 10 to convert it into an integer 96. In yet another example, the first difference value is 2.423, the first difference value can be rounded to 2 or converted into an integer 24 (multiplying by 10), 242 (multiplying by 10 2 ) or 2423 (multiplying by 10 3 ).

[0044] Step S440: For each second core among the plurality of cores except the first core: obtain a second data value corresponding to each second core among the plurality of data, obtain a second difference value based on a difference between the first data value and the second data value, and optionally round the second difference value. Step S440 is basically similar to step S330 in the above Figure 3 described above with respect to step S330, except that in step S440, after obtaining the second difference value based on the difference between the first data value and the second data value, the obtained second difference value can be further rounded in a similar manner to the rounding of the first difference value as described above at step S430. However, it should be understood that the rounding of the second difference value is not necessary, for example, in some examples, if there is a higher requirement for the accuracy of the stored data, the step of rounding the second difference value is omitted. Other parts of step S440 can be seen in the above description with respect to step S330, which will not be repeated here.

[0045] Step S450: Store the first difference value corresponding to the first core 210A and the corresponding second difference value corresponding to each second core (i.e., each of the cores 210B to 210H) in the one-time programmable memory, respectively. Step S450 is similar to step S340 in the above Figure 3 described above with respect to step S340, which will not be repeated here.

[0046] Figure 5 Further shown is a flowchart of a storage method for storing the first difference and the second difference into the OTP memory. As shown, the storage method can include steps S510, S520, S530 and S540. Figure 5

[0047] Step S510: obtaining the first difference and the second difference. The first difference can be obtained, for example, based on step S320 of the method 300 or step S420 of the method 400, and the second difference can be obtained, for example, based on step S330 of the method 300 or step S440 of the method 400, which will not be described in detail herein. Figure 3 Figure 4 Step S520: converting the first difference and the second difference into integers respectively. For example, the first difference and the second difference can be converted into integers respectively by using the rounding method described in step S430. In some embodiments, the decimal part of the first difference and the second difference can be removed directly. Alternatively, in other embodiments, the first difference and the second difference can be multiplied by a corresponding positive integer power of 10 according to the number of bits of the decimal part of the first difference and the second difference respectively, so as to convert the first difference and the second difference into integers respectively. Figure 3 Figure 4 Step S530: converting the converted integers into binary codes.

[0048] Step S540: storing the converted binary codes into the OTP memory.

[0049] As can be seen from the above, the first difference and the second difference are stored into the OTP memory in the form of binary codes, and the stored binary codes are converted from the first difference and the second difference after rounding, so that in general, the number of bits of the binary codes converted after removing the decimal part of the first difference and the second difference directly is relatively small, and the storage space of the OTP memory required is also small.

[0050]

[0051] Figure 5

[0052] ​​​​​​For example, in the example of the first difference value of 9.6 as described above, the first difference value after rounding can be 9 or 96. Without considering the sign bit, the binary code converted from 9 requires 4 bits, while the binary code converted from 96 requires 7 bits, obviously the former requires less bits and thus less corresponding storage space. When the data value to be stored is large, for example, when the first difference value to be stored is 238.2, although removing the decimal part directly and then converting to binary code reduces the accuracy of the stored first difference value, for the first difference value, only 0.08% accuracy is sacrificed (238.2-238) / 238, and 4 bits are saved for storing data. Obviously, the binary code converted after removing the decimal part of the first difference value directly requires less bits for storage, significantly reducing the demand for storage space of the OTP memory.

[0053] For illustrative purposes, the data processing method for data storage of in-chip one-time programmable memory according to at least one embodiment of the present disclosure will be described in detail below in combination with an example of parameter calibration of a circuit for temperature calibration and Figure 6 For illustrative purposes, the data processing method for data storage of in-chip one-time programmable memory according to at least one embodiment of the present disclosure will be described in detail below in combination with an example of parameter calibration of a circuit for temperature calibration and Figure 6 A multi-core chip 600 for storing temperature calibration parameters is shown, which includes four processor cores 610A, 610B, 610C, and 610D.

[0054] Generally speaking, for each processor core, temperature calibration can be performed according to the following formula:

[0055]

[0056] where T is the temperature, N is the measurement value, and R is the bit width of the accuracy. Y and K are parameters that need to be calibrated, and the distribution of both Y and K follows a normal distribution for multiple sets of data of multiple processor cores. For example, it can be learned from experience that the mean of the normal distribution of Y is 708.9, and the mean of the normal distribution of K is 334.8. That is, in this example, the multiple data corresponding to the multiple processor cores include multiple values of K and multiple values of Y, one of the multiple values of K and the corresponding one of the multiple values of Y are stored in the same processor core of the multiple processor cores, wherein the first reference value of K is 334.8 and the first reference value of Y is 708.9.

[0057] For example, the multiple data corresponding to the multi-core chip 600 can include 4 values of K (K1, K2, K3, K4) and 4 values of Y (Y1, Y2, Y3, Y4); as Figure 6As shown, K1, K2, K3, K4 respectively correspond to Y1, Y2, Y3, Y4, and further correspond to the four processor cores 610A, 610B, 610C, 610D of the multi-core chip 600, as shown in Table 1 below.

[0058] Processor core 610A Processor core 610B Processor core 610C Processor core 610D K1 K2 K3 K4 -356.1 -349.7 -358.9 -351.8 Y1 Y2 Y3 Y4 683.4 678.2 687.7 686.6

[0059] Table 1

[0060] For example, the values of K1 and Y1 will be stored into the OTP memory of the processor core 610A of the multi-core chip 600; the values of K2 and Y2 will be stored into the OTP memory of the processor core 610B of the multi-core chip 600; the values of K3 and Y3 will be stored into the OTP memory of the processor core 610C of the multi-core chip 600; and the values of K4 and Y4 will be stored into the OTP memory of the processor core 610D of the multi-core chip 600. In other embodiments, instead of storing the respective corresponding data on each processor core respectively, other ways of allocating the OTP memory can be employed, for example, a same OTP memory can be provided for these processor cores, which includes different fields respectively for storing the values of K and Y corresponding to these processor cores respectively, which can be provided independently of the plurality of processor cores, or for example, in a certain processor core.

[0061] Table 2 below shows the original data corresponding to each processor core of the multi-core chip 600 and the number of bits required for each.

[0062]

[0063]

[0064] Table 2

[0065] For the processor core 610A, the value of K1 (K1 = -356.1) and the value of Y1 (Y1 = 683.4) corresponding to the processor core 610A are obtained, and based on the first reference value of K being 334.8 and the first reference value of Y being 708.9 as described above, the first difference value of K (i.e., the difference between the value of K1 and the first reference value of K, K1-K) is -21.3, and the first difference value of Y (i.e., the difference between the value of Y1 and the first reference value of Y, Y1-Y) is -25.5. The first difference value of K and the first difference value of Y are respectively rounded, for example, by directly removing the decimal part, and the obtained rounded first difference value of K is -21, and the obtained first difference value of Y is -25.

[0066] For the processor core 610B, the processor core 610C and the processor core 610D, the values of corresponding K and Y are obtained respectively. For example, for the processor core 610B, the value of K2 (K2 = -349.7) and the value of Y2 (Y1 = 678.2) corresponding to the processor core 610B are obtained; for the processor core 610C, the value of K3 (K3 = -358.9) and the value of Y3 (Y3 = 687.7) corresponding to the processor core 610C are obtained; and for the processor core 610D, the value of K4 (K4 = -351.8) and the value of Y4 (Y4 = 686.6) corresponding to the processor core 610D are obtained. Since the data stored on the same chip can be similar but not exactly the same, for example, the plurality of values K1, K2, K3 and K4 of K stored in the multi-core AI chip 600 are similar but not exactly the same, therefore, a plurality of second difference values of K (i.e., K2-K1, K3-K1, K4-K1) to be respectively stored in the processor core 610B, the processor core 610C and the processor core 610D can be obtained based on the difference between K1 and K2, K3, K4. Compared with the second difference values that can be obtained based on the first reference value of K and the difference between K2, K3, K4, the second difference values obtained based on the difference between K1 and K2, K3, K4 are smaller, and the required storage space is also smaller. In this case, the second difference values of K include 6.4, -2.8, 4.3 respectively corresponding to the processor core 610B, the processor core 610C and the processor core 610D. Similarly, the second difference values of Y include -5.2, 4.3 and 3.2 respectively corresponding to the processor core 610B, the processor core 610C and the processor core 610D.

[0067] Then, the first difference value and the plurality of second difference values of K and the first difference value and the plurality of second difference values of Y are rounded as described above, and the rounded difference values are converted into binary codes, which will not be described here. In the example of the embodiment, for the sake of simplicity, the first difference value and the plurality of second difference values of K and the first difference value and the plurality of second difference values of Y are also rounded by directly removing the decimal part.

[0068] Table 3 shows the data corresponding to each processor core of the multi-core chip 600 after the data processing as described above and the corresponding number of bits.

[0069]

[0070] Table 3

[0071] As can be seen from Table 2 and Table 3, by using the data processing method provided according to at least one embodiment of the present disclosure, the number of bits for storing the parameters can be reduced from 108 bits to 29 bits, which significantly saves the resources required for storing the data, thereby reducing the requirement for the size of the storage space of the OTP memory.

[0072] The at least one embodiment of the present disclosure also provides a chip including a plurality of cores and a one-time programmable (OTP) memory in which data processed via the above data processing method is stored. Wherein, a first difference value corresponding to a first core of the plurality of cores and a respective second difference value corresponding to each second core of the plurality of cores except the first core are stored in the one-time programmable memory. The first difference value is obtained by a first data value corresponding to the first core and based on a difference between the first data value and a first reference value. The second difference value is obtained by a second data value corresponding to each second core and based on a difference between the first data value and the second data value.

[0073] For example, the OTP memory corresponding to each core can be provided on each core for storing data (e.g., data obtained based on the values of Y and K) corresponding to the core, i.e., each core stores data corresponding to the core in the plurality of data respectively; or the same OTP memory can be provided for the plurality of cores, different fields of the OTP memory corresponding to different cores, for storing a plurality of data (e.g., data obtained based on the values of Y and K) corresponding to the plurality of cores respectively.

[0074] The at least one embodiment of the present disclosure also provides a data processing method for a one-time programmable memory in a chip including a plurality of cores, for restoring data stored in the chip and processed via the above data processing method. The data processing method can include: reading a first difference value and at least one second difference value from the one-time programmable memory, for example, decoding binary codes corresponding to the first difference value and the second difference value to obtain integers corresponding to the first difference value and the second difference value respectively, and converting the integers corresponding to the first difference value and the second difference value into the first difference value and the second difference value respectively. The first difference value corresponds to a first core of the plurality of cores, and each second difference value of the at least one second difference value corresponds to a respective second core of at least one second core of the plurality of cores except the first core.

[0075] The data processing method can also include, for example, obtaining a first reference value stored in the chip. For the first core of the plurality of cores, a first data value corresponding to the first core can then be obtained based on a sum of the first difference value and the first reference value. For each second core of the at least one second core of the plurality of cores except the first core, a second data value corresponding to each second core can be obtained based on a sum of the first difference value, the second difference value and the first reference value.

[0076] The at least one embodiment of the present disclosure also provides an electronic device including a memory and at least one processor. The memory has instructions stored thereon, which when executed by the at least one processor, can implement the data processing method provided by any embodiment of the present disclosure.

[0077] Figure 7 A schematic diagram of an electronic device 700 is shown according to an embodiment of the present disclosure. As shown, the electronic device 700 includes a processor 710 and a memory 720. The memory 720 is configured to store non-transitory computer-readable instructions (e.g., one or more computer program modules). The processor 710 is configured to execute the non-transitory computer-readable instructions, which, when executed by the processor 710, can perform one or more steps of the data processing method described above. The memory 720 and the processor 710 can be interconnected by a bus system and / or other forms of connection mechanisms (not shown). Figure 7 The processor 710 can be, for example, a central processing unit (CPU), a graphics processing unit (GPU), or other forms of processing units having data processing and / or program executing capabilities. For example, the central processing unit (CPU) can be of X86 or ARM architecture, etc. The processor 710 can be a general purpose processor or a special purpose processor, and can control other components in the electronic device 700 to perform desired functions.

[0078] The memory 720 can include, for example, any combination of one or more computer program products. The computer program product can include various forms of computer-readable storage media for storing information that is used or generated during the execution of the one or more computer programs by the processor 710, such as volatile memory (e.g., random access memory (RAM) and / or cache), non-volatile memory (e.g., read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), compact disc read-only memory (CD-ROM), USB memory, flash memory, etc.). One or more computer program modules can be stored on the computer-readable storage media, and the processor 710 can execute the one or more computer program modules to implement various functions of the electronic device 700. Various application programs and various data used and / or generated by the application programs, etc. can also be stored in the computer-readable storage media.

[0079] It should be noted that the specific functions and technical effects of the electronic device 700 in the embodiments of the present disclosure can refer to the description of the data processing method above, which will not be described here again.

[0080] At least one embodiment of the present disclosure further provides a computer-readable storage medium, which non-transitorily stores computer-executable instructions. When the computer-executable instructions are executed by a computer, the data processing method provided by any embodiment of the present disclosure can be implemented.

[0081]

[0082] A schematic diagram of a computer-readable storage medium according to an embodiment of the present disclosure is shown. As shown, Figure 8 Figure 8 ​As shown, the storage medium 800 is configured to store non-transitory computer readable instructions 810. For example, when the non-transitory computer readable instructions 810 are executed by a computer, one or more steps of the data processing method according to the above can be performed.

[0083] For example, the storage medium 800 can be applied in the electronic device 700 described above. For example, the storage medium 800 can be the memory 720 in the electronic device 700 as shown. Figure 7 For example, the relevant description about the storage medium 800 can refer to the corresponding description of the memory 720 in the electronic device 700 as shown. Figure 7 For example, the relevant description about the storage medium 800 can refer to the corresponding description of the memory 720 in the electronic device 700 as shown.

[0084] For the present disclosure, the following points also need to be explained:

[0085] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0086] (2) In the case of no conflict, the features in the same and different embodiments of the present disclosure can be combined with each other.

[0087] The above is only a specific implementation of the present disclosure, but the protection scope of the present disclosure is not limited to this. Any person skilled in the art can easily think of changes or replacements within the technical range disclosed by the present disclosure, which should be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A data processing method for storing data in an on-chip one-time programmable memory, the chip comprising multiple cores, the data processing method comprising: Acquire multiple data corresponding to the plurality of cores, and acquire a first reference value for the plurality of data; For the first core among the plurality of cores, a first data value corresponding to the first core is obtained from the plurality of data, and a first difference is obtained based on the difference between the first data value and the first reference value; For each of the plurality of cores other than the first core: Obtain the second data value corresponding to each of the plurality of data, and A second difference is obtained based on the difference between the first data value and the second data value; as well as The first difference is stored in the one-time programmable memory corresponding to the first core and the corresponding second difference is stored in each of the second cores.

2. The data processing method according to claim 1, wherein, The process of obtaining the first reference value for the plurality of data includes: A first reference value is determined based on the distribution of the multiple data points.

3. The data processing method according to claim 2, wherein, The first reference value is the mean of the normal distribution of multiple data corresponding to the multiple kernels.

4. The data processing method according to claim 2 or 3 further includes: The first reference value is stored in the chip.

5. The data processing method according to claim 1, wherein, The one-time programmable memory stores the first difference corresponding to the first core and the corresponding second difference corresponding to each of the second cores, including: Convert the first difference and the second difference into integers respectively; Convert the obtained integer into binary code; and The converted binary code is stored in the one-time programmable memory.

6. The data processing method according to claim 1 further includes: After obtaining the first difference based on the difference between the first data value and the first reference value, the first difference is rounded down. and / or After obtaining the second difference based on the difference between the first data value and the second data value, the second difference is rounded.

7. The data processing method according to claim 6, wherein, The rounding includes: Remove the decimal part of the first difference directly.

8. A data processing method for an on-chip one-time programmable memory, the chip comprising multiple cores, the data processing method comprising: Read a first difference and at least one second difference from the one-time programmable memory, wherein the first difference corresponds to a first core among the plurality of cores, and each of the at least one second difference corresponds to a corresponding second core among at least one second core among the plurality of cores other than the first core; Obtain the first reference value; For the first core, a first data value corresponding to the first core is obtained based on the sum of the first difference and the first reference value; For each of at least one second core among the plurality of cores other than the first core: Based on the sum of the first difference, the second difference, and the first reference value, a second data value corresponding to each of the second cores is obtained.

9. The data processing method according to claim 8, wherein, Reading the first difference and the at least one second difference from the one-time programmable memory includes: Decode the binary codes corresponding to the first difference and the second difference to obtain integers corresponding to the first difference and the second difference, respectively; and The integers corresponding to the first difference and the second difference are converted into the first difference and the second difference, respectively.

10. A chip, comprising: Multiple cores; as well as A one-time programmable memory, wherein a first difference value corresponding to a first core among the plurality of cores and a corresponding second difference value corresponding to each second core among the plurality of cores other than the first core are stored in the one-time programmable memory. The first difference is obtained by using a first data value corresponding to the first core and based on the difference between the first data value and the first reference value. The second difference is obtained by using a second data value corresponding to each of the second cores, and based on the difference between the first data value and the second data value.

11. An electronic device, comprising: A memory that stores instructions; At least one processor, wherein the instructions are executed by the at least one processor to implement the data processing method according to any one of claims 1-9.

12. A computer-readable storage medium that non-transitorily stores computer-executable instructions, which, when executed by a computer, are used to implement the data processing method according to any one of claims 1-9.

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