Substrate trench etching method

Abstract

The application discloses a substrate trench etching method, which comprises the following steps: forming a groove with a slanted side wall on a substrate surface; forming a protective layer on the inner surface of the groove; removing the protective layer in the central region of the groove and retaining the protective layer on the slanted side wall of the edge of the groove; etching the substrate to form a trench with a set depth in the substrate, and meanwhile removing the protective layer on the slanted side wall of the edge of the groove and forming a rounded top corner morphology on the top edge of the trench. The application can obtain an ideal rounded silicon top corner morphology, and reduce the risk of electric leakage caused by sharp top corners after subsequent medium filling.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor etching technology, and more specifically, relates to a substrate trench etching method. Background Technology

[0002] In existing shallow trench isolation (STI) etching processes, the shape of the silicon trench determines whether there are voids or defects in the subsequent oxide layer filling. The smoothness of the silicon trench corners determines the performance of tip leakage current. Sharp corners create high edge electric fields on the sidewalls of the shallow trench isolation, causing leakage current to form double humps on the gate current-voltage curve, and in severe cases, leading to dielectric breakdown and affecting electrical properties. Rounding the top corners can solve this problem. In the industry, the common practice is to perform lateral etching of the hard mask using hot phosphoric acid and diluted hydrofluoric acid after dry etching, exposing the sharp corners of the silicon trench and the hard mask. During subsequent substrate oxidation, these sharp corners can be passivated, reducing leakage current caused by the sharp corners. Figures 1a-1c As shown.

[0003] However, relying solely on the sharp corners of the substrate silicon oxide trenches results in insufficient corner passivation, still posing a risk of tip leakage. Therefore, in shallow trench etching where critical dimensions are small, an additional etching step is added before silicon etching to form rounded corners. Due to the protection of the hard mask, achieving rounded corners using only dry etching is very difficult. Common silicon corner morphologies after dry etching are shown in the attached figure. Figure 1a As shown. If the top corners can be rounded, a shape like the one shown in the attached image can be formed. Figure 2 The ideal shape shown is of great significance in reducing leakage current caused by sharp corners. Summary of the Invention

[0004] The purpose of this invention is to propose a shallow trench etching method for silicon substrates to achieve rounded silicon apex corners and reduce the risk of leakage current caused by sharp apex corners after subsequent dielectric filling.

[0005] To achieve the above objectives, the present invention proposes a substrate trench etching method, comprising:

[0006] A groove with inclined sidewalls is formed on the substrate surface;

[0007] A protective layer is formed on the inner surface of the groove;

[0008] Remove the protective layer in the central region of the groove, while retaining the protective layer on the inclined sidewalls of the groove edge;

[0009] The substrate is etched to form a trench of a set depth, while the protective layer on the inclined sidewalls of the trench edge is removed and a rounded apex shape is formed at the top edge of the trench.

[0010] Optionally, the substrate includes a single-crystal silicon layer, a hard mask layer, an amorphous carbon layer, and a patterned photoresist layer distributed sequentially from bottom to top.

[0011] Optionally, forming a groove with inclined sidewalls on the substrate surface includes:

[0012] An opening is etched in the amorphous carbon layer and the hard mask layer using a first etching gas to expose the surface of the single-crystal silicon layer;

[0013] A second etching gas is used to etch a groove with inclined sidewalls onto the surface of the monocrystalline silicon layer exposed by the opening.

[0014] Optionally, the first etching gas includes a hydrogen-containing hydrocarbon gas, a dilution gas, and oxygen;

[0015] The second etching gas includes hydrogen-containing hydrocarbon gas, diluent gas, oxygen, and chlorine.

[0016] Optionally, forming a protective layer on the inner surface of the groove includes:

[0017] The substrate is etched using a third etching gas to remove the amorphous carbon layer and oxidize the single-crystal silicon on the inner surface of the groove to form silicon oxide, thereby forming the protective layer.

[0018] Optionally, the third etching gas includes oxygen, nitrogen, and helium.

[0019] Optionally, removing the protective layer in the central region of the groove while retaining the protective layer on the inclined sidewalls of the groove edge includes:

[0020] The hard mask layer and the single-crystal silicon layer are etched using a fourth etching gas to remove the protective layer in the central region of the groove, while retaining the protective layer on the inclined sidewalls of the groove edge.

[0021] Optionally, the fourth etching gas includes hydrogen-containing fluorocarbon gas and hydrogen bromide, wherein the flow ratio of the hydrogen-containing fluorocarbon gas to hydrogen bromide in the fourth etching gas ranges from 2.5:1 to 5:1.

[0022] Optionally, forming a trench of a predetermined depth in the substrate, while removing the protective layer on the inclined sidewalls of the trench edge and forming a rounded apex shape at the top edge of the trench, includes:

[0023] The hard mask layer and the single-crystal silicon layer are etched using a fifth etching gas to form a trench of a set depth in the single-crystal silicon layer. At the same time, the protective layer on the inclined sidewall of the trench edge is removed and a rounded apex shape is formed at the top edge of the trench.

[0024] Optionally, the fifth etching gas includes hydrogen-containing fluorocarbon gas and hydrogen bromide, and the flow ratio of the hydrogen-containing fluorocarbon gas and hydrogen bromide in the fifth etching gas is in the range of 1:100-1:150.

[0025] Optionally, the hydrogen-containing fluorocarbon gas is at least one of CHF3, CH2F2, and CH3F.

[0026] Optionally, during the etching of the single-crystal silicon layer using the fifth etching gas, the etching is performed using a lower electrode pulse radio frequency mode.

[0027] The beneficial effects of this invention are as follows:

[0028] In the method of the present invention, a groove with inclined sidewalls is first formed on the substrate surface, and then a protective layer is formed on the inner surface of the groove. After that, the protective layer in the central region of the groove is removed, while the protective layer on the inclined sidewall of the groove edge is retained. The remaining protective layer can serve as an equivalent mask for the top of the sidewall of the etching trench, thus protecting the top edge of the trench sidewall. This allows the top edge of the etching morphology to be etched later than the middle part during the subsequent trench etching process, ultimately forming a rounded apex morphology at the top edge of the trench, thereby reducing the risk of leakage current caused by sharp apex after subsequent dielectric filling.

[0029] The system of the present invention has other features and advantages that will be apparent from or will be set forth in detail in the accompanying drawings and following detailed description, which together serve to explain the particular principles of the invention. Attached Figure Description

[0030] The above and other objects, features and advantages of the present invention will become more apparent from the accompanying drawings, in which like reference numerals generally denote like parts.

[0031] Figures 1a-1c The diagrams show the morphology of the silicon substrate after dry etching, wet etching, and substrate oxidation in the shallow trench isolation etching process.

[0032] Figure 2 A schematic diagram of the morphology of an ideal rounded silicon apex is shown.

[0033] Figure 3The diagram illustrates the film structure and principle of the existing corner rounding method.

[0034] Figure 4 A schematic diagram of the etching effect of the existing corner rounding method is shown.

[0035] Figure 5 An atomic micrograph of the etching morphology of the prior art corner rounding method is shown.

[0036] Figure 6 A step diagram of a substrate trench etching method according to an embodiment of the present invention is shown.

[0037] Figure 7 This diagram illustrates the film structure of a silicon substrate in a substrate trench etching method according to an embodiment of the present invention.

[0038] Figure 8 This diagram illustrates a method for forming a groove with inclined sidewalls in a substrate trench etching process according to an embodiment of the present invention.

[0039] Figure 9a and Figure 9b The images show electron microscope (EM) images of the "micro-trench" morphology and the inclined sidewall morphology of the groove in a substrate trench etching method according to an embodiment of the present invention.

[0040] Figure 10 This diagram illustrates the formation of a silicon oxide protective layer on top of a single-crystal silicon layer in a substrate trench etching method according to an embodiment of the present invention.

[0041] Figure 11 This diagram illustrates a substrate trench etching method according to an embodiment of the present invention, in which the central portion of the protective layer is removed while the edge portion is retained.

[0042] Figure 12 This diagram illustrates the formation of rounded silicon apex corners in a substrate trench etching method according to an embodiment of the present invention.

[0043] Figure 13a The image shows an electron microscope (EM) image of a sharp silicon apex obtained by existing shallow trench etching.

[0044] Figure 13b An electron microscope image of a rounded silicon apex obtained by a substrate trench etching method according to an embodiment of the present invention is shown. Detailed Implementation

[0045] like Figure 3 As shown, the prior art provides a method for rounding the apex corners of a silicon wafer using a fluorocarbon polymer. This method involves reactive ion etching performed after a trench 11 structure is formed on the surface of a substrate silicon wafer 10 placed on a base at the bottom of a processing chamber. The method includes the following steps:

[0046] Step 1. Introduce a mixture of fluorocarbons and inert gases into the vacuum processing chamber;

[0047] Step 2. Apply a high-frequency radio frequency source to the processing chamber to generate plasma of fluorocarbons in the mixed gas;

[0048] Step 3. Form a polymer film 20 containing fluorocarbons at the apex 12 of the trench 11 on the surface of the silicon wafer 10;

[0049] Step 4. The surface of the silicon wafer 10 is chemically etched with a polymer containing fluorocarbons to round the apex 12. The etching time of the polymer on the apex is longer than 30s, preferably longer than 60s.

[0050] In step 1, the fluorocarbon compound is a gas of carbon tetrafluoride (CF4), perfluorobutadiene (C4F6), or octafluorocyclobutane (C4F8). The fluorocarbon compound also contains trifluoromethane (CHF3), which accelerates the reaction of the mixed gas on the surface of the silicon wafer 10, forming a thin film 20 of its polymer, and covering the sidewalls and apex 12 of the channel 11. The mixed gas also contains oxygen (O2) and argon (Ar), with the O2 flow rate being less than the fluorocarbon compound flow rate.

[0051] The method of using a fluorocarbon polymer to round the corners of a silicon wafer also includes a low-frequency radio frequency power supply applied to a chamber processing base to accelerate charged ions generated by ionization from a high-frequency radio frequency source and control the energy of incident particles.

[0052] The effect of using the corner rounding method is shown below. Figure 4 and Figure 5 As shown.

[0053] This method has the following drawbacks:

[0054] 1. The above-mentioned corner rounding treatment is a post-processing performed after silicon etching. It takes a long time (>60s, with the best effect requiring 120s) to show its effect. For the current mainstream film structure of IC etching, the selectivity of the C / F-based gas used is not enough for the hard mask, resulting in a very obvious etching effect. This can easily lead to insufficient mask 30 remaining, affecting subsequent wet cleaning and CMP endpoint capture.

[0055] 2. To achieve slope control for rounded corners, this method requires the addition of low-frequency radio frequency bias and argon (Ar) to provide physical sputtering etching ions. For advanced process technology, the extremely small critical dimensions, high aspect ratio, silicon sidewalls, and bottom treatment require more careful handling. Since it uses C / F-based etching gas, the addition of bias and Ar will aggravate the damage to the silicon surface, which may cause voids during vapor deposition of silicon oxide and affect electrical properties.

[0056] The substrate trench etching method of the present invention can achieve rounded silicon apex corners by dry etching, thereby reducing the risk of leakage current caused by sharp apex corners after subsequent dielectric filling.

[0057] The invention will now be described in more detail with reference to the accompanying drawings. While preferred embodiments of the invention are shown in the drawings, it should be understood that the invention can be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that the invention will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art.

[0058] Example

[0059] like Figure 6 As shown, a substrate trench etching method includes:

[0060] S1: A groove with inclined sidewalls is formed on the substrate surface;

[0061] The substrate used in this embodiment includes a single-crystal silicon layer 105, a hard mask layer 104, and an amorphous carbon layer 103 arranged sequentially from bottom to top; the specific film structure of the substrate is shown in the attached figure. Figure 7 As shown, from top to bottom, they are: photoresist layer 101 (PR), dielectric antireflective layer 102 (Darc), amorphous carbon layer 103 (ACL), hard mask layer 104 (ONOHard mask) composed of silicon oxide, silicon nitride and silicon oxide, and single crystal silicon layer 105.

[0062] Generally, shallow trench etching processes are classified according to the film layer distribution into dielectric anti-reflection layer etching, amorphous carbon layer etching, hard mask etching, ashing etching to remove the top amorphous carbon layer, through-etching, and single-crystal silicon etching. Among them, dielectric anti-reflection layer etching is used to define the critical dimension (CD) and improve the critical dimension uniformity (CDU), while amorphous carbon layer etching is used for pattern transfer. Before performing step S1, the photoresist layer 101 needs to be patterned, and the patterned photoresist layer 101 is used as a mask to perform opening etching on the hard mask layer 104.

[0063] Step S1 includes the main etching process of the hard mask layer and the over-etching process of the hard mask layer, as detailed below:

[0064] S101: Perform the main etching process step of the hard mask layer, using the first etching gas to etch an opening in the amorphous carbon layer and the hard mask layer to expose the top surface of the single crystal silicon layer;

[0065] Preferably, the first etching gas in this step includes a hydrogen-containing hydrocarbon gas, a dilution gas, and oxygen. The process parameters for the main etching step of the hard mask layer include:

[0066] The chamber pressure range is 5-10 mT;

[0067] The upper electrode RF power range is 500-1000W;

[0068] The lower electrode RF power range is 200-300W;

[0069] The chamber temperature range is 40-60℃.

[0070] The hard mask layer 104 is completely etched through using the above etching process parameters, exposing the surface of the single-crystal silicon layer.

[0071] S102: Perform the hard mask layer over-etching process step, using the second etching gas to etch a groove shape with inclined sidewalls on the top surface of the single crystal silicon layer exposed by the opening;

[0072] Preferably, the second etching gas in this step includes a hydrogen-containing hydrocarbon gas, a dilution gas, oxygen, and chlorine. The process parameters for the hard mask layer over-etching process step include:

[0073] The chamber pressure range is 10-40 mT;

[0074] The upper electrode RF power range is 500-1000W;

[0075] The lower electrode RF power range is 300-500W;

[0076] The chamber temperature range is 40-70℃;

[0077] The process time range is 10-30 seconds.

[0078] The top of the monocrystalline silicon layer 105 is pre-treated using the above etching process parameters to form a shallow, over-etched groove morphology on the top of the monocrystalline silicon layer 105. In practice, the sidewall angles formed by the over-etched groove morphology need to be as tilted as possible. If necessary, an unfavorable morphology of "micro-trench" type can be formed (this type of morphology, when transferred to the bottom of the monocrystalline silicon, will affect the subsequent dielectric filling). See attached... Figure 8 , Figure 9a and Figure 9b As shown.

[0079] In this step, the sloping morphology or "micro-trench" type groove morphology formed by over-etching will cause the single-crystal silicon to protrude significantly from the upper hard mask. This part is an important component of the subsequent rounded corner. Subsequent ashing etching will form an oxide layer (protective layer) on the surface of this part, as shown in the attached figure. Figure 10 As shown. The through-etching process retains the oxide layer in that area as an equivalent mask, as illustrated in the attached diagram. Figure 11As shown, the purpose is to protect the etching of this part of the single-crystal silicon as much as possible from the etching of the middle part of the single-crystal silicon, so as to ultimately form a rounded apex corner at the top of the single-crystal silicon.

[0080] S2: A protective layer is formed on the inner surface of the groove;

[0081] This step is to perform the ashing etching process, using a third etching gas to remove the amorphous carbon layer and oxidize the single crystal silicon on the inner surface of the groove to silicon oxide to form a protective layer;

[0082] Preferably, the third etching gas in this step includes oxygen, nitrogen, and helium, and the protective layer is a silicon oxide layer. The process parameters for the ashing etching step include:

[0083] The chamber pressure range is 5-20 mT;

[0084] The upper electrode RF power range is 800W-1500W;

[0085] The lower electrode RF power range is 50-200W;

[0086] The chamber temperature range is 40-70℃;

[0087] The process time range is 50-100 seconds.

[0088] The residual amorphous carbon layer 103 on top of the hard mask layer 104 is completely removed using the above etching process parameters. This ensures that the hard mask layer 104 is used as the mask for etching in the subsequent single-crystal silicon etching process, instead of using the amorphous carbon layer 103. Simultaneously, the single-crystal silicon on the inner surface of the groove is oxidized, covering the inner surface of the groove with a layer of silicon oxide to form a protective layer, as shown in the attached figure. Figure 10 As shown.

[0089] S3: Remove the protective layer in the central area of ​​the groove, and retain the protective layer on the sloping sidewalls at the edge of the groove.

[0090] This step involves performing a through-etching process, using a fourth etching gas to remove the protective layer in the central region of the groove, while retaining the protective layer on the inclined sidewalls at the edge of the groove.

[0091] Preferably, in this step, the fourth etching gas includes a hydrogen-containing fluorocarbon gas (CHF) and hydrogen bromide, wherein the hydrogen-containing fluorocarbon gas is at least one of CHF3, CH2F2, and CH3F. The flow rate ratio of the hydrogen-containing fluorocarbon gas to hydrogen bromide in the fourth etching gas ranges from 2.5:1 to 5:1; the process parameters throughout the etching process steps include:

[0092] The chamber pressure range is 20-50 mT;

[0093] The upper electrode RF power range is 800W-1500W;

[0094] The lower RF power range is 50-200W;

[0095] The chamber temperature range is 40-60℃;

[0096] The process time range is 10-30 seconds.

[0097] Specifically, unlike the CHF3+O2 gas in existing technology 1, where O2 combines with C and H elements to promote the dissociation of CHF3 and accelerate the etching rate of silicon oxide, this step requires reducing the etching rate of silicon oxide. Therefore, a combination of CHF+HBr is used. Since HBr contains H and is a polymer component, and Br has a very low etching rate for Si-O, the CHF+HBr combination results in a very slow etching rate for silicon oxide. Combined with the polymer deposition on the sidewalls, this makes the middle of the protective layer easier to etch and the edges less prone to etching. This is equivalent to adding an equivalent mask to the top edge of the single-crystal silicon layer, improving the etching resistance of the single-crystal silicon located at the edge of the groove. The combination of hydrogen bromide and hydrogen-containing fluorine gas results in a very slow etching rate for silicon oxide, and the hydrogen-containing fluorine gas has the effect of forming polymers and depositing on the sidewalls. Therefore, the silicon oxide layer (protective layer) formed by the ashing step is always etched in the middle first and then at the edges, as shown in the attached diagram. Figure 11 As shown.

[0098] S4: Etch the substrate to form trenches of a set depth in the substrate, while removing the protective layer on the inclined sidewalls of the trench edges and forming a rounded apex shape at the top edge of the trench;

[0099] This step is to perform a single-crystal silicon etching process. The single-crystal silicon layer 105 is etched using the fifth etching gas to form a trench of a set depth in the single-crystal silicon layer 105. At the same time, the protective layer on the inclined sidewall of the trench edge is removed and a rounded silicon apex shape is formed at the top edge of the trench.

[0100] The fifth etching gas used in this step includes hydrogen-containing fluorocarbon gas and hydrogen bromide, and the flow ratio of hydrogen-containing fluorocarbon gas to hydrogen bromide in the fifth etching gas is lower than that in the fourth etching gas, thereby increasing the etching rate of single-crystal silicon.

[0101] Preferably, the flow ratio of hydrogen-containing hydrocarbon gas to hydrogen bromide in the fifth etching gas is in the range of 1:100-1:150. The process parameters for the single-crystal silicon etching step include:

[0102] Chamber pressure: 20-50 mT;

[0103] Top electrode RF power: 800W-1500W;

[0104] Lower electrode RF power: 50-200W, lower electrode RF pulse duty cycle range: 30%-60%, pulse frequency range: 100-300Hz;

[0105] The chamber temperature range is 50-70℃.

[0106] like Figure 12 As shown, this step uses the lower electrode RF pulse mode to improve the tilt or micro-trench morphology of the bottom of the single crystal silicon, and can solve the problem of the tilt or micro-trench morphology of the top of the single crystal silicon after the hard mask etching process being transferred to the bottom and affecting the subsequent dielectric filling.

[0107] Figure 13a This shows an electron microscope image of a sharp silicon apex obtained by existing shallow trench etching. Figure 13b The image shows an electron microscope (EM) image of a rounded silicon apex obtained by a substrate trench etching method according to an embodiment of the present invention. It can be seen that the etching method of this embodiment can obtain an ideal rounded apex morphology, thereby effectively reducing the risk of leakage current caused by sharp apex after subsequent dielectric filling and improving the performance of semiconductor devices.

[0108] The various embodiments of the present invention have been described above. These descriptions are exemplary and not exhaustive, nor are they limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A method for etching trenches on a substrate, characterized in that, include: A groove with inclined sidewalls is formed on the surface of a substrate, the substrate comprising a single-crystal silicon layer, a hard mask layer, an amorphous carbon layer and a patterned photoresist layer distributed sequentially from bottom to top. Forming the groove with inclined sidewalls on the surface of the substrate includes: etching an opening in the amorphous carbon layer and the hard mask layer to expose the surface of the single-crystal silicon layer using a first etching gas; and etching the groove with inclined sidewalls on the surface of the single-crystal silicon layer exposed by the opening using a second etching gas. Forming a protective layer on the inner surface of the groove includes: etching the substrate with a third etching gas to remove the amorphous carbon layer, and oxidizing the single-crystal silicon on the inner surface of the groove to silicon oxide to form the protective layer; Remove the protective layer in the central region of the groove, while retaining the protective layer on the inclined sidewalls of the groove edge; The substrate is etched to form a trench of a predetermined depth, while the protective layer on the inclined sidewalls of the trench edge is removed and a rounded apex shape is formed at the top edge of the trench. During the etching process, the protective layer on the inclined sidewalls of the trench edge acts as an equivalent mask to cause the etching of single-crystal silicon at the top edge of the trench to lag behind the etching of single-crystal silicon in the middle part.

2. The substrate trench etching method according to claim 1, characterized in that, The first etching gas includes a hydrogen-containing hydrocarbon gas, a diluent gas, and oxygen; The second etching gas includes hydrogen-containing hydrocarbon gas, diluent gas, oxygen, and chlorine.

3. The substrate trench etching method according to claim 1, characterized in that, The third etching gas includes oxygen, nitrogen, and helium.

4. The substrate trench etching method according to claim 1, characterized in that, Removing the protective layer from the central region of the groove while retaining the protective layer on the inclined sidewalls of the groove edge includes: The hard mask layer and the single-crystal silicon layer are etched using a fourth etching gas to remove the protective layer in the central region of the groove, while retaining the protective layer on the inclined sidewalls of the groove edge.

5. The substrate trench etching method according to claim 4, characterized in that, The fourth etching gas includes hydrogen-containing fluorocarbon gas and hydrogen bromide, and the flow ratio of the hydrogen-containing fluorocarbon gas to hydrogen bromide in the fourth etching gas ranges from 2.5:1 to 5:

1.

6. The substrate trench etching method according to claim 1, characterized in that, The process of forming a trench of a predetermined depth in the substrate, while removing the protective layer on the inclined sidewalls of the trench edge and forming a rounded apex shape at the top edge of the trench, includes: The hard mask layer and the single-crystal silicon layer are etched using a fifth etching gas to form a trench of a set depth in the single-crystal silicon layer. At the same time, the protective layer on the inclined sidewall of the trench edge is removed and a rounded apex shape is formed at the top edge of the trench.

7. The substrate trench etching method according to claim 6, characterized in that, The fifth etching gas includes hydrogen-containing fluorocarbon gas and hydrogen bromide, and the flow ratio of the hydrogen-containing fluorocarbon gas and hydrogen bromide in the fifth etching gas is in the range of 1:100-1:

150.

8. The substrate trench etching method according to any one of claims 2, 5, and 7, characterized in that, The hydrogen-containing fluorocarbon gas is at least one of CHF3, CH2F2, and CH3F.

9. The substrate trench etching method according to claim 6, characterized in that, During the etching of the single-crystal silicon layer using the fifth etching gas, the etching is performed using a lower electrode pulse radio frequency mode.

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