Variable selectivity soi etching method

Abstract

The present application relates to a variable selectivity SOI etching method, which etches silicon-on-insulator material by the following steps: (1) providing a silicon-on-insulator substrate; (2) depositing a variable selectivity composite hard mask instead of a traditional hard mask with invariable selectivity; (3) applying glue; (4) making a plate, defining the area to be etched by a photoetching plate; (5) etching the photoresist of the defined area; (6) etching the composite hard mask; (7) removing the glue; (8) etching the top layer of silicon with a first selectivity by using a second etching method; (9) etching the buried oxygen layer with a second selectivity by using a third etching method. The present application is different from the traditional etching technology, can avoid damage to the sidewall of the deep trench when etching the buried oxygen layer, and does not need to use an excessively thick hard mask when etching the buried oxygen layer with a thickness of 0.5 μm or more, thereby reducing the cost of the process, relieving the mask stress and improving the stability of the process.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor manufacturing, and in particular to a variable selectivity SOI etching method. BACKGROUND

[0002] SOI (Silicon On Insulator) high voltage integrated circuits are widely used due to their high speed, low power consumption, radiation resistance and easy isolation. As the core device of SOI high voltage integrated circuits, the low vertical breakdown voltage of SOI lateral devices limits their application in high voltage power integrated circuits. A series of new structures have been proposed by domestic and foreign scholars to improve the vertical withstand voltage of SOI lateral devices, and special deep trench isolation structures also require the etching of thick buried oxide layers on the silicon-on-insulator. However, the existing technology cannot etch thick buried oxide layers while protecting the surface of the silicon wafer and being compatible with BCD processes. SUMMARY

[0003] Based on the above reasons, the purpose of the present application is to provide a variable selectivity SOI etching method.

[0004] To achieve the above-mentioned application purposes, the technical solutions of the present application are as follows:

[0005] A variable selectivity SOI etching method for etching a silicon-on-insulator material by the following steps:

[0006] (1) providing a silicon-on-insulator wafer;

[0007] (2) depositing a variable selectivity composite hard mask instead of a traditional hard mask with non-variable selectivity;

[0008] (3) applying glue;

[0009] (4) making a plate, defining the area to be etched with a photoetching plate;

[0010] (5) etching the photoresist in the defined area;

[0011] (6) etching the composite hard mask using a first etching method;

[0012] (7) removing the glue;

[0013] (8) etching the top layer of silicon with a first selectivity using a second etching method;

[0014] (9) etching the buried oxide layer with a second selectivity using a third etching method, the second selectivity being different from the first selectivity.

[0015] As a preferred mode, the silicon-on-insulator wafer has a top layer of silicon with a thickness greater than 2 μm and less than 25 μm, and a buried oxide layer with a thickness greater than 0.5 μm and less than 4.5 μm.

[0016] As a preferred mode, the composite hard mask of step (2) comprises, from bottom to top, a first oxide layer, a silicon nitride layer, a second oxide layer, a polysilicon layer, and a third oxide layer.

[0017] As a preferred mode, the composite hard mask, the first oxide layer is obtained by thermal oxidation, the silicon nitride layer is obtained by low pressure chemical vapor deposition, the second oxide layer is obtained by low pressure chemical vapor deposition, the polysilicon layer is obtained by low pressure chemical vapor deposition, and the third oxide layer is obtained by low pressure chemical vapor deposition.

[0018] As a preferred mode, the defined region of step (5) is in the shape of a circular ring, a long strip, a circular hole, or a square hole.

[0019] As a preferred mode, the first etching method for etching the composite hard mask of step (6) is reactive ion etching with a pressure of 30-300 MT, a power of 300-1000 W, and a gas flow rate of CF4: 50 to 150 Sccm and Ar: 10 to 150 Sccm.

[0020] As a preferred mode, the second etching method for etching the top layer of silicon of step (8) is reactive ion etching with a pressure of 10-300 MT, a power of 300-1000 W, and a gas ratio of SF6: 50 to 150 Sccm and O2: 5 to 60 Sccm, and after the etching is completed, a polymer or an oxide is used to protect the sidewall.

[0021] As a preferred mode, the third etching method for etching the buried oxide layer of step (9) is plasma or reactive ion etching with a pressure of 30-300 MT, a power of 300-1000 W, and a gas flow rate of CF4: 5 to 80 Sccm, Ar: 10 to 150 Sccm, and CHF3: 50 to 150 Sccm, Ar: 10 to 150, and finally, a wet method is used to rinse away the residual polymer.

[0022] As a preferred mode, the first selection ratio is greater than 20 and the second selection ratio is greater than 50. In this way, the silicon wafer can be prevented from being damaged too much during etching, which can cause interface defect problems.

[0023] As a preferred mode, the first selection ratio is 35 and the second selection ratio is 100.

[0024] In one embodiment, the first etching method is reactive ion etching with high anisotropy, which can simultaneously etch the oxide layer, the silicon nitride layer, and the polysilicon layer.

[0025] In one embodiment, the second etching method is fluorine-based gas reactive ion etching with very strong anisotropy and a silicon-to-oxide selection ratio greater than 20.

[0026] In one of the embodiments, the third etching method is to first introduce a gas to form a silicon sidewall protection, and then use plasma etching to remove the third oxide layer; and then use a wet etching with a large selectivity of oxide to silicon and strong isotropy.

[0027] The present application has the advantages that the present application can avoid damage to the deep trench sidewall when etching the buried oxide layer, and when etching the buried oxide layer with a thickness of 0.5 μm or more, a too thick hard mask is not needed, the cost of the process is reduced, the mask stress is relieved, and the stability of the process is improved. BRIEF DESCRIPTION OF DRAWINGS

[0028] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which like reference characters refer to like parts throughout and in which the preferred embodiment of the present application is shown by way of illustration. The drawings are not necessarily drawn to scale, emphasis instead being placed upon illustrating the principles of the present application.

[0029] Figure 1 A perspective view of the silicon-on-insulator material of Example 2 after etching;

[0030] Figure 2 A front view of the silicon-on-insulator material of Example 2 after etching;

[0031] Figure 3 A schematic view of the substrate of the silicon-on-insulator material of Example 2;

[0032] Figure 4 A schematic view of the first oxide layer of Example 2;

[0033] Figure 5 A schematic view of the silicon nitride layer of Example 2;

[0034] Figure 6 A schematic view of the second oxide layer of Example 2;

[0035] Figure 7 A schematic view of the polysilicon layer of Example 2;

[0036] Figure 8 A schematic view of the third oxide layer of Example 2;

[0037] Figure 9 A schematic view of the photoresist of Example 2;

[0038] Figure 10 A schematic view of the first etching method of Example 2;

[0039] Figure 11 A schematic view of the photoresist after removal of the photoresist of Example 2;

[0040] Figure 12Figure 6 is a schematic diagram of the buffer etching before the third etching method in Example 2.

[0041] Figure 13 Figure 6 is a schematic diagram of the buffer etching before the third etching method in Example 2.

[0042] Figure 14 Figure 7 is a schematic diagram of the third etching method after the third etching method in Example 2.

[0043] Figure 15 Figure 8 is a schematic diagram of the removing the composite hard mask after the third etching method in Example 2.

[0044] Figure 16 Figure 9 is a SEM experimental diagram after the first etching method in Example 2.

[0045] Figure 17 Figure 10 is a SEM experimental diagram after the second etching method in Example 2.

[0046] Figure 18 Figure 11 is a SEM experimental diagram after the third etching method in Example 2.

[0047] Figure 19 Figure 12 is a schematic diagram of the variable selection ratio composite hard mask of the present application.

[0048] Figure 20 Figure 13 is a schematic diagram of the first selection ratio, the second selection ratio and the conventional selection ratio of the present application.

[0049] 101 is a substrate, 102 is an insulating layer, 103 is a buried oxygen layer, 104 is a deep trench, 105 is a silicon substrate on the insulating layer, 106 is a first oxide layer, 107 is a silicon nitride layer, 108 is a second oxide layer, 109 is a polysilicon layer, 110 is a third oxide layer, and 111 is a photoresist. DETAILED DESCRIPTION

[0050] The process manufacturing method for enhancing the buried layer electric field structure according to the present application is further described in detail below in combination with the accompanying drawings and specific embodiments. The advantages and features of the present application will be more apparent according to the following description and claims. It should be noted that the accompanying drawings are in a very simplified form and use non-precise proportions, which are only used to facilitate and clarify the purpose of assisting the description of the embodiments of the present application.

[0051] Example 1

[0052] The present embodiment provides a variable selection ratio SOI etching method, which etches a silicon-on-insulator material by the following steps:

[0053] (1) providing a silicon-on-insulator substrate; the silicon-on-insulator substrate has a top layer silicon thickness greater than 2 μm and less than 25 μm, and a buried oxygen layer thickness greater than 0.5 μm and less than 4.5 μm.

[0054] (2) depositing a composite hard mask with variable selectivity instead of a conventional hard mask with non-variable selectivity; the composite hard mask of step (2) comprises, from bottom to top, a first oxide layer 106, a silicon nitride layer 107, a second oxide layer 108, a polysilicon layer 109, and a third oxide layer 110. The composite hard mask is formed by thermal oxidation for the first oxide layer, low pressure chemical vapor deposition for the silicon nitride layer, low pressure chemical vapor deposition for the second oxide layer, low pressure chemical vapor deposition for the polysilicon layer, and low pressure chemical vapor deposition for the third oxide layer.

[0055] (3) applying glue;

[0056] (4) making a mask to define the area to be etched;

[0057] (5) etching the defined area of the photoresist; the defined area of step (5) is in the shape of a ring, a long strip, a circular hole, or a square hole.

[0058] (6) etching the composite hard mask using a first etching method; the first etching method for etching the composite hard mask is reactive ion etching with a pressure of 30-300 MT, a power of 300-1000 W, and a gas flow rate of CF4: 50 to 150 Sccm, Ar: 10 to 150 Sccm.

[0059] (7) removing the photoresist;

[0060] (8) etching the top layer of silicon using a second etching method with a first selectivity; the second etching method for etching the top layer of silicon is reactive ion etching with a pressure of 10-300 MT, a power of 300-1000 W, and a gas ratio of SF6: 50 to 150 Sccm, O2: 5 to 60 Sccm, and using a polymer or an oxide to protect the sidewall after etching.

[0061] (9) etching the buried oxide layer using a third etching method with a second selectivity, which is different from the first selectivity. The third etching method for etching the buried oxide layer of step (9) is plasma or reactive ion etching with a pressure of 30-300 MT, a power of 300-1000 W, and a gas flow rate of CF4: 5 to 80 Sccm, Ar: 10 to 150 Sccm, CHF3: 50 to 150 Sccm, Ar: 10 to 150, and finally using a wet method to remove residual polymers.

[0062] Example 2

[0063] The present embodiment provides a variable selectivity SOI etching method, comprising the following steps:

[0064] (1) providing a substrate 101, an insulating layer 102, and a silicon-on-insulator wafer 105 formed on the insulating layer, as shown inFigure 3 As shown;

[0065] (2) An oxide layer 106 of a certain thickness is grown on the substrate by oxidation, such as... Figure 4 As shown, in order to improve the quality of the oxide layer and the defect stress on the silicon surface, this step adopts direct furnace tube oxidation growth;

[0066] (3) A silicon nitride layer 107 of a certain thickness is deposited on the first oxide layer using low-pressure chemical vapor deposition, such as... Figure 5 As shown, low-pressure chemical vapor deposition is used to facilitate silicon nitride shaping and silicon nitride film uniformity.

[0067] (4) A second oxide layer 108 of a certain thickness is deposited on the silicon nitride layer using low-pressure chemical vapor deposition, such as... Figure 6 As shown, low-pressure chemical vapor deposition is used to facilitate the protection of the underlying silicon nitride layer;

[0068] (5) A polycrystalline silicon layer 109 of a certain thickness is deposited on the second oxide layer using low-pressure chemical vapor deposition, such as... Figure 7 As shown, this step plays a major role in the etching of the buried oxide layer, and low-pressure chemical vapor deposition is used.

[0069] (6) A third oxide layer 110 of a certain thickness is deposited on the polycrystalline silicon layer using low-pressure chemical vapor deposition, such as... Figure 8 As shown, atmospheric pressure, low pressure, and plasma-assisted chemical vapor deposition can all be used;

[0070] (7) Apply photoresist, using photoresist 111 with a thickness of approximately 1 micrometer, such as... Figure 9 As shown;

[0071] (8) Define the region on the silicon layer using a photomask, and develop the image. The defined region can be annular, elongated, circular, or square. After development and inspection, etch the composite hard mask using the first etching method to etch the deep trench 104 to the silicon surface, as shown in the diagram. Figure 10 and Figure 16 SEM experiments show that the selectivity ratio of the oxide layer to silicon nitride does not need to be too stringent, but uniformity and anisotropy must be ensured. Fluorine-based dry reactive ion etching was used, with a pressure of 30–300 MT and a power of 300–1000 W. The gas ratio was: CF4: 50 to 150 Sccm, Ar: 10 to 150 Sccm. The gas types included, but were not limited to, those listed above. By adjusting the oxygen content, a certain selectivity ratio of the oxide layer to silicon could be achieved, and the anisotropy could be controlled by adjusting the number of fluorine atoms and ion energy.

[0072] (9) Remove adhesive and clean, as follows: Figure 11 As shown;

[0073] (10) etching the top layer of silicon with a first selectivity ratio, and etching the top layer of silicon with a second etching method, pressure 10-300 MT, power 300-1000 W, gas ratio: SF6 50 to 150 Sccm, O2: 5 to 60 Sccm, gas types including but not limited to the above types, etching the deep trench 104 to the insulating layer 102, as shown in Figure 12 With Figure 17 SEM experiments show that the selectivity ratio of silicon to the oxide layer at this step is selected according to the top layer of silicon, and when the top layer of silicon is thin, it can not be too harsh, and when the top layer of silicon is greater than 20 microns, it is best to ensure that the first selectivity ratio of silicon to the oxide layer is greater than 20, and the first selectivity ratio of silicon to the oxide layer in this embodiment is 35; fluorine-based gas, chlorine or bromine gas dry plasma etching, by adjusting the oxygen or hydrogen content, the first selectivity ratio of silicon to the oxide layer can be met, and chlorine or bromine gas can ensure very high anisotropy;

[0074] (11) etching the buried oxide layer with a second selectivity ratio, as shown in Figure 13 The selectivity ratio of the oxide layer to silicon nitride can not be too harsh, and the selectivity ratio of the hard mask to silicon is not required, the main purpose is to remove the third oxide layer at the same time of etching the buried oxide, and to achieve automatic conversion of the composite hard mask; the second selectivity ratio is preferably greater than 50, and the second selectivity ratio in this embodiment is 100.

[0075] The third etching method for etching the buried oxide layer is: pressure 30-300 MT, power 300-1000 W, gas flow: CF4 45 to 80 Sccm, Ar: 10 to 150 Sccm, CHF3 50 to 150 Sccm, Ar: 10 to 150, gas types including but not limited to the above types, etching the buried oxide layer 103 to a certain depth of the insulating layer 102, as shown in Figure 14 With Figure 18 SEM experiments show that at this time, the polysilicon layer in the composite hard mask plays a major role, the selectivity ratio of the oxide layer to silicon nitride can not be too harsh, but the second selectivity ratio to silicon must be ensured, and it has good uniformity and anisotropy, fluorine-based gas dry plasma etching, by adjusting the hydrogen content, when the hydrogen concentration is greater than 40%, the silicon etching rate is almost 0, adjusting the ratio of oxygen / nitrogen can have a certain selectivity ratio to silicon nitride, adjusting the number of fluorine atoms and ion energy to control the anisotropy; finally, the etched sidewall polymer and chemical reaction residues can be etched with dilute hydrofluoric acid buffered with ammonium fluoride, which can accurately control the etching, stabilize the etching process, and have good isotropy and high selectivity ratio;

[0076] (13) stripping the composite hard mask, as shown in Figure 15 Stripping the polysilicon layer uses dry etching, stripping the silicon nitride layer uses hot phosphoric acid or fluorine-based gas plus oxygen / nitrogen plasma dry etching; dilute hydrofluoric acid buffered with ammonium fluoride.

Claims

1. A variable selectivity SOI etching method, characterized by An SOI material is etched by the following steps: (1) providing an SOI substrate; (2) depositing a composite hard mask with variable selectivity; the composite hard mask comprises, from bottom to top, a first oxide layer, a silicon nitride layer, a second oxide layer, a polysilicon layer, and a third oxide layer; (3) applying photoresist; (4) defining the area to be etched by a photomask; (5) etching the photoresist in the defined area; (6) etching the composite hard mask using a first etching method; (7) removing the photoresist; (8) etching the top silicon layer using a second etching method with a first selectivity; (9) etching the buried oxide layer using a third etching method with a second selectivity different from the first selectivity.

2. The method of claim 1 wherein: the SOI etch is a variable selectivity SOI etch. The SOI substrate has a top silicon layer with a thickness greater than 2 µm and less than 25 µm, and a buried oxide layer with a thickness greater than 0.5 µm and less than 4.5 µm.

3. The method of claim 1 wherein: the SOI etch is a variable selectivity SOI etch. The composite hard mask has a first oxide layer grown by thermal oxidation, a silicon nitride layer deposited by low-pressure chemical vapor deposition, a second oxide layer deposited by low-pressure chemical vapor deposition, a polysilicon layer deposited by low-pressure chemical vapor deposition, and a third oxide layer deposited by low-pressure chemical vapor deposition.

4. The method of claim 1 wherein: the SOI etch is a variable selectivity SOI etch. The defined area in step (5) is in the shape of a circular ring, a long strip, a circular hole, or a square hole.

5. The method of claim 1 wherein: the SOI etch is a variable selectivity SOI etch. The first etching method for etching the composite hard mask in step (6) is reactive ion etching with a pressure of 30-300 MT, a power of 300-1000 W, and a gas flow rate of CF4: 50-150 Sccm and Ar: 10-150 Sccm.

6. The method of claim 1 wherein: the SOI etch is a variable selectivity SOI etch. The second etching method for etching the top silicon layer in step (8) is reactive ion etching with a pressure of 10-300 MT, a power of 300-1000 W, and a gas ratio of SF6: 50-150 Sccm and O2: 5-60 Sccm, and a polymer or oxide is used to protect the sidewall after etching.

7. The method of claim 1 wherein: the SOI etch is a variable selectivity SOI etch. The third etching method for etching the buried oxide layer in step (9) is plasma or reactive ion etching with a pressure of 30-300 MT, a power of 300-1000 W, and a gas flow rate of CF4: 5-80 Sccm, Ar: 10-150 Sccm, and CHF3: 50-150 Sccm, and finally a wet etching is used to remove the residual polymer.

8. The method of claim 1 wherein: the SOI etch is a variable selectivity SOI etch. The first selectivity is greater than 20, and the second selectivity is greater than 50.

9. The method of claim 1 wherein: the SOI etch is a variable selectivity SOI etch. The first selectivity is 35, and the second selectivity is 100.

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