A method for fabricating GaN P-FET devices using selective epitaxy.

Abstract

The application belongs to the technical field of power semiconductors, and relates to a manufacturing method of a GaN P-FET device by using a selective epitaxy process. In the manufacturing method, a dielectric is first deposited on a GaN cap layer and a hard mask is formed by etching to define the position of a gate, then a P-GaN layer and a SiN x passivation layer, then source and drain electrodes with ohmic contacts are formed at both ends, then the hard mask is removed, a recessed gate is made at the position, and finally an enhancement-mode GaN P-FET is realized. Compared with a recessed gate technology for realizing an enhancement-mode P-FET by etching a P-GaN layer under a gate partially or entirely, the application reduces lattice damage introduced by etching the P-GaN layer, improves the quality of a gate interface and prevents the reduction of hole mobility in a channel, and does not need to control the precision of recess etching.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology, and more specifically, relates to a method for manufacturing a GaNP-FET device using selective epitaxy. Background Technology

[0002] For power module design, CMOS topology offers the most energy-efficient solution for large-scale integration and mixed-signal applications. GaN CMOS topology requires monolithic integration of N-channel and P-channel field-effect transistors on a GaN substrate; therefore, realizing high-performance GaN-based P-channel field-effect transistors (P-FETs) is crucial for the development and application of GaN ICs. Currently, GaN P-FETs typically utilize two-dimensional hole gas (2DHG) channels formed by polarization at the GaN / AlGaN heterojunction to conduct current; however, this structure is usually depletion-mode. Developing enhancement-mode GaN P-FETs is a pressing issue to address in order to achieve complementary logic in low-power GaN CMOS circuits. Groove gate technology is the main technique for realizing enhancement-mode GaN P-FETs; however, etching to form a grooved gate introduces lattice damage, reduces the quality of the gate interface, and decreases hole mobility at the channel, degrading output characteristics and affecting device reliability and stability. Summary of the Invention

[0003] This invention, based on the application requirements of GaN P-FET devices, proposes a method for manufacturing GaN P-FET devices using selective epitaxial growth. First, a dielectric material is deposited on the GaN cap layer, and a hard mask is formed by etching to define the gate position. Then, a P-GaN layer and a SiN layer are sequentially grown using metal-organic chemical vapor deposition (MOCVD). x A passivation layer is applied, followed by the formation of ohmic contacts at the source and drain ends. The hard mask is then removed, and a recessed gate is fabricated at this location, ultimately realizing an enhancement-mode GaN P-FET. Simultaneously, this invention reduces lattice damage introduced by etching the recessed gate, ensuring the mobility of the 2DHG remains unaffected, and also reduces the interface state density.

[0004] To achieve the above-mentioned objectives, the technical solution of the present invention is as follows:

[0005] A method for manufacturing a GaN P-FET device using selective epitaxy, characterized by comprising the following steps:

[0006] Step 1: Prepare substrate 1, form GaN buffer layer 2 on substrate 1, form GaN channel layer 3 on GaN buffer layer 2, form AlGaN barrier layer 4 on GaN channel layer 3, and finally form GaN cap layer 5 on AlGaN barrier layer 4.

[0007] Step 2: A dielectric material is deposited on the GaN cap layer 5 using chemical vapor deposition, and photolithography is used to etch away the two ends of the dielectric material, thereby forming a hard mask 6 in the middle of the upper surface of the GaN cap layer 5.

[0008] Step 3: Using metal-organic chemical vapor deposition (MOCVD), P-GaN layers 7 and SiN layers 7 are successively formed on both ends of the upper surface of the GaN cap layer 5, which are also the two ends of the hard mask 6. x Passivation layer 8, and SiN x The height of passivation layer 8 is lower than that of hard mask 6;

[0009] Step 4: Etch to remove the hard mask 6;

[0010] Step 5: Etching SiN x At both ends of the passivation layer 8, the holes required for the source electrode 9 and drain electrode 10 are exposed on both ends of the upper surface of the P-GaN layer 7.

[0011] Step 6: Deposit the P-type ohmic contact metal required for the source 9 and drain 10, using a stripping process and annealing to form the source 9 and drain 10;

[0012] Step 7: Deposit the metal required for the gate 11 using a stripping process to form the gate 11, which fills the groove formed after removing the hard mask 6 and extends to both sides along the upper surface of the groove.

[0013] As a preferred embodiment, the gate 11 formed in step 7 is a MIS gate or a Schottky gate.

[0014] As a preferred embodiment, the gate 11 formed in step 7 is a MIS gate. The specific method is as follows: first, a gate dielectric 12 is deposited on the device surface using a low-temperature dielectric deposition technique, and the gate dielectric 12 is photolithographically and etched to expose the source 9 and drain 10; then, the metal required for the gate 11 is deposited on the gate dielectric 12, and a stripping process is used to form the gate 11. The gate 11 fills the groove formed after removing the hard mask 6 and extends to both sides along the upper surface of the groove.

[0015] As a preferred embodiment, the gate 11 formed in step 7 is a Schottky gate. The specific method is as follows: depositing material to form the Schottky contact of the gate 11, using a stripping process to form the gate 11, the gate 11 filling the groove formed after removing the hard mask 6, and extending to both sides along the upper surface of the groove.

[0016] As a preferred embodiment, the metal material used for the gate 11 includes, but is not limited to, one of Ni, Au, Ti, TiN, and combinations thereof.

[0017] As a preferred embodiment, the material used for the gate dielectric 12 includes, but is not limited to, SiN. xOne of Al2O3, HfO2, and combinations thereof.

[0018] The beneficial effect of this invention is that a hard mask is first formed by depositing and etching a dielectric material on a GaN cap layer, and then P-GaN and SiN layers are selectively epitaxially grown on this structure. x A passivation layer is applied, and finally the SiO2 mask is removed to form a grooved gate. Compared to the grooved gate technology that uses partial or complete etching of the P-GaN layer under the gate to realize enhancement-mode P-FETs, this invention reduces lattice damage introduced by etching the P-GaN layer, improves the quality of the gate interface, prevents a decrease in channel hole mobility, and eliminates the need to control the precision of the groove etching. Attached Figure Description

[0019] Figure 1 This is a two-dimensional structural schematic diagram of Example 1.

[0020] Figure 2 This is the process flow diagram of Example 1.

[0021] Figure 3 These are the specific process steps of Example 1, wherein:

[0022] (a) is a schematic diagram of the device structure after material preparation in step 1 of the process flow of Example 1;

[0023] (b) is a schematic diagram of the device structure after forming a hard mask and photolithography in step 2 of the process flow of Example 1;

[0024] (c) is a schematic diagram of the device structure after regrowing the P-GaN layer and passivation layer in step 3 of the process flow of Example 1.

[0025] (d) is a schematic diagram of the device structure after removing the hard mask in step 4 of the process flow of Example 1;

[0026] (e) is a schematic diagram of the device structure after etching the passivation layer to form the source and drain holes in step 5 of the process flow of Example 1.

[0027] (f) is a schematic diagram of the device structure after the source and drain conductive materials are formed in step 6 of the process flow of Example 1;

[0028] (g) is a schematic diagram of the device structure after the gate conductive material is formed in step 7 of the process flow of Example 1;

[0029] Figure 4 This is a two-dimensional structural schematic diagram of Example 2. Detailed Implementation

[0030] The technical solution of the present invention will now be described in detail with reference to the accompanying drawings and embodiments:

[0031] Example 1:

[0032] Step 1: Prepare substrate 1, form GaN buffer layer 2 on substrate 1, form GaN channel layer 3 on GaN buffer layer 2, form AlGaN barrier layer 4 on GaN channel layer 3, and finally form GaN cap layer 5 on AlGaN barrier layer 4.

[0033] Step 2: A dielectric material is deposited on the GaN cap layer 5 using chemical vapor deposition, and photolithography is used to etch away the two ends of the dielectric material, thereby forming a hard mask 6 in the middle of the upper surface of the GaN cap layer 5.

[0034] Step 3: Using metal-organic chemical vapor deposition (MOCVD), P-GaN layers 7 and SiN layers 7 are successively formed on both ends of the upper surface of the GaN cap layer 5, which are also the two ends of the hard mask 6. x Passivation layer 8, and SiN x The height of passivation layer 8 is lower than that of hard mask 6;

[0035] Step 4: Etch to remove the hard mask 6;

[0036] Step 5: Etching SiN x At both ends of the passivation layer 8, the holes required for the source electrode 9 and drain electrode 10 are exposed on both ends of the upper surface of the P-GaN layer 7.

[0037] Step 6: Deposit the P-type ohmic contact metal required for the source 9 and drain 10, using a stripping process and annealing to form the source 9 and drain 10;

[0038] Step 7: Deposit the metal required for the gate 11 using a stripping process to form the gate 11, which fills the groove formed after removing the hard mask 6 and extends to both sides along the upper surface of the groove.

[0039] The GaN P-FET device fabricated using the above method first deposits and etches a dielectric material on the GaN cap layer to form a hard mask, and then selectively epitaxially grows a P-GaN layer and a SiN layer on this structure. x A passivation layer is applied, and finally the hard mask is removed to form a recessed gate. Compared to the recessed gate technology that uses partial or complete etching of the P-GaN layer under the gate to realize enhancement-mode P-FETs, this invention reduces lattice damage introduced by etching the P-GaN layer, improves the quality of the gate interface, prevents a decrease in channel hole mobility, and eliminates the need to control the precision of the recessed etching.

[0040] Example 2:

[0041] The difference between this example and Example 1 is that the process in step 7 is different, and the gate 11 is a MIS gate. Specifically, in step 7, a low-temperature dielectric deposition technique is first used to deposit a gate dielectric 12 on the device surface, and the gate dielectric 12 is photolithographically and etched to expose the source 9 and drain 10; then, the metal required for the gate 11 is deposited on the gate dielectric 12, and a lift-off process is used to form the gate 11. The gate 11 fills the groove formed after removing the hard mask 6 and extends to both sides along the upper surface of the groove.

[0042] The GaN P-FET device fabricated using the above method first deposits and etches a dielectric material on the GaN cap layer to form a hard mask, and then selectively epitaxially grows a P-GaN layer and a SiN layer on this structure. x A passivation layer is applied, and finally the hard mask is removed to form a recessed gate. Compared to the recessed gate technology that uses partial or complete etching of the P-GaN layer under the gate to realize enhancement-mode P-FETs, this invention reduces lattice damage introduced by etching the P-GaN layer, improves the quality of the gate interface, prevents a decrease in channel hole mobility, and eliminates the need to control the precision of the recessed etching.

Claims

1. A method for manufacturing a GaN P-FET device using selective epitaxy, characterized in that, Includes the following steps: Step 1: Prepare a substrate (1), form a GaN buffer layer (2) on the substrate (1), form a GaN channel layer (3) on the GaN buffer layer (2), form an AlGaN barrier layer (4) on the GaN channel layer (3), and finally form a GaN cap layer (5) on the AlGaN barrier layer (4). Step 2: Chemical vapor deposition is used to deposit a dielectric material on the GaN cap layer (5), and photolithography is used to etch away the two ends of the dielectric material, thereby forming a hard mask (6) in the middle of the upper surface of the GaN cap layer (5). Step 3: Using metal-organic chemical vapor deposition (MOCVD), P-GaN layers (7) and SiN layers are successively formed at both ends of the upper surface of the GaN cap layer (5), which are also the two ends of the hard mask (6). x Passivation layer (8), and SiN x The height of the passivation layer (8) is lower than that of the hard mask (6); Step 4: Etch to remove the hard mask (6); Step 5: Etching SiN x At both ends of the passivation layer (8), the holes required for the source (9) and drain (10) are exposed on the upper surface of the P-GaN layer (7); Step 6: Deposit the P-type ohmic contact metal required for the source (9) and drain (10), and perform a stripping process and annealing to form the source (9) and drain (10); Step 7: Deposit the metal required for the gate (11) using a stripping process to form the gate (11), which fills the groove formed after removing the hard mask (6) and extends to both sides along the upper surface of the groove.

2. The method for manufacturing a GaN P-FET device using selective epitaxy according to claim 1, characterized in that, The gate (11) formed in step 7 is a MIS gate or a Schottky gate.

3. The method for manufacturing a GaN P-FET device using selective epitaxy according to claim 2, characterized in that, The gate (11) formed in step 7 is a MIS gate. The specific method is as follows: first, a gate dielectric (12) is deposited on the device surface using a low-temperature dielectric deposition technique, and the gate dielectric (12) is photolithographically and etched to expose the source (9) and drain (10); then, the metal required for the gate (11) is deposited on the gate dielectric (12), and a stripping process is used to form the gate (11). The gate (11) fills the groove formed after removing the hard mask (6) and extends to both sides along the upper surface of the groove.

4. A method for manufacturing a GaN P-FET device using selective epitaxy according to claim 2, characterized in that, The gate (11) formed in step 7 is a Schottky gate. The specific method is as follows: depositing material to form the Schottky contact of the gate (11), using a stripping process to form the gate (11), the gate (11) fills the groove formed after removing the hard mask (6), and extends to both sides along the upper surface of the groove.

5. A method for manufacturing a GaN P-FET device using selective epitaxy according to claim 1, characterized in that, The gate (11) is made of one or a combination of Ni, Au, Ti, TiN.

6. A method for manufacturing a GaN P-FET device using selective epitaxy according to claim 1, characterized in that, The gate dielectric (12) is made of SiN. x One of Al2O3, HfO2, or a combination thereof.

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