Method for manufacturing a metal oxide semiconductor device and device

Abstract

The embodiment of the present application relates to a kind of metal oxide semiconductor device preparation method and device, by providing substrate with drift region, drift region has first conductive type;Form shallow trench isolation structure on the first selected position of substrate, and form local oxidation isolation structure on the second selected position of substrate;Wherein, second selected position is located above drift region;Ion implantation is carried out on the entire upper surface of substrate;Wherein, at the first selected position, shallow trench isolation structure blocks the ion entering substrate;At the second selected position, the ion is implanted to pass through local oxidation isolation structure, to form the top layer with second conductive type in drift region below local oxidation isolation structure;Second conductive type is opposite in electrical property with first conductive type;Not only reduce surface electric field, but also reduce the on-resistance of device, save process time, reduce process cost.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a preparation method of a metal oxide semiconductor device and the device. BACKGROUND

[0002] With the development of the times, the application field of semiconductor devices has been expanded from traditional industrial control, communication, computer, consumer electronics to new fields such as new energy, smart grid, rail transit, and automotive electronics. Lateral double-diffused MOSFET (LDMOS) has both high voltage resistance and large current of discrete devices, and also takes advantage of high density and intelligent logic control of low-voltage integrated circuits. A single chip realizes the functions that originally required multiple chips, greatly reducing the size of the device, reducing costs, improving energy efficiency, and meeting the development direction of modern power electronic devices towards miniaturization, intelligence, and low energy consumption.

[0003] The breakdown voltage, as a key parameter for measuring the reliability and use range of PN junction, is particularly important for device performance. The prior art forms a doped top layer on the surface of the drift region to increase the depletion of the drift region and reduce the surface electric field (Resurf), thereby ultimately improving the breakdown voltage of the device. However, how to further achieve low on-resistance (Rsp) while improving the breakdown voltage is still an important technical problem for those skilled in the art to solve. In addition, the specific process for forming the doped top layer also needs to be further improved. SUMMARY

[0004] Therefore, the embodiments of the present application provide a preparation method of a metal oxide semiconductor device and the device to solve at least one problem in the background art.

[0005] In a first aspect, the embodiments of the present application provide a preparation method of a metal oxide semiconductor device, which comprises:

[0006] providing a substrate with a drift region, the drift region having a first conductivity type;

[0007] forming a shallow trench isolation structure at a first selected position on the substrate, and forming a local oxidation isolation structure at a second selected position on the substrate; wherein the second selected position is located above the drift region;

[0008] performing ion implantation on the entire upper surface of the substrate; wherein at the first selected locations, the shallow trench isolation structure blocks the implanted ions from entering the substrate; at the second selected locations, the implanted ions pass through the local oxidation isolation structure to form a top layer having a second conductivity type in the drift region under the local oxidation isolation structure; the second conductivity type is electrically opposite to the first conductivity type.

[0009] In an optional implementation of the first aspect of the present application, the depth of the local oxidation isolation structure is 800 Å~ 1200 Å; and / or, the depth of the shallow trench isolation structure is 3500 Å~ 4500 Å.

[0010] In an optional implementation of the first aspect of the present application, the first conductivity type is N type, and the second conductivity type is P type.

[0011] In an optional implementation of the first aspect of the present application, before the performing ion implantation on the entire upper surface of the substrate, the method further comprises:

[0012] forming a well region having a second conductivity type in the substrate;

[0013] forming a gate structure on the substrate; wherein along the thickness direction of the substrate, the gate structure at least partially overlaps with the well region; the gate structure covers the region of the substrate between the well region and the drift region.

[0014] In an optional implementation of the first aspect of the present application, the metal oxide semiconductor device is an N type lateral diffusion metal oxide semiconductor device.

[0015] In a second aspect, the embodiments of the present application provide a metal oxide semiconductor device, comprising:

[0016] a substrate having a drift region, the drift region having a first conductivity type;

[0017] a shallow trench isolation structure at a first selected location on the substrate, and a local oxidation isolation structure at a second selected location on the substrate; wherein the second selected location is above the drift region;

[0018] a top layer in the drift region under the local oxidation isolation structure, the top layer having a second conductivity type; the second conductivity type is electrically opposite to the first conductivity type.

[0019] In an optional implementation of the second aspect of the present application, the depth of the local oxidation isolation structure is 800-1200 angstroms; and / or, the depth of the shallow trench isolation structure is 3500-4500 angstroms.

[0020] In an optional implementation of the second aspect of the present application, the first conductivity type is N type and the second conductivity type is P type.

[0021] In an optional implementation of the second aspect of the present application, the method further comprises:

[0022] a well region located in the substrate, the well region having the second conductivity type;

[0023] a gate structure located on the substrate; wherein, along the thickness direction of the substrate, the gate structure at least partially overlaps with the well region; the gate structure covers the region of the substrate between the well region and the drift region.

[0024] In an optional implementation of the second aspect of the present application, the metal oxide semiconductor device is an N type lateral diffusion metal oxide semiconductor device.

[0025] The metal oxide semiconductor device provided by the embodiments of the present application and the preparation method thereof have the following advantages. The top layer having the second conductivity type is formed in the drift region below the local oxidation isolation structure, which not only increases the depletion of the drift region, reduces the surface electric field, and improves the breakdown voltage of the device, but also, compared with the shallow trench isolation structure, the depth of the local oxidation isolation structure is smaller, and the larger longitudinal cross-sectional area available for electron movement can be reserved in the drift region by using the depth advantage of the local oxidation isolation structure, thereby reducing the on-resistance (Rsp) of the device. On this basis, the local oxidation isolation structure is not used for isolation on the entire substrate, but is used above the position where the top layer having the second conductivity type is to be formed, and the shallow trench isolation structure is still arranged at other positions, so that ion implantation is performed by using the height difference between the shallow trench isolation structure and the local oxidation isolation structure to form the top layer having the second conductivity type in the drift region below the local oxidation isolation structure. In this way, local ion implantation is not required to be performed using a photolithography mask, so that the process time is saved and the process cost is reduced. Meanwhile, the shallow trench isolation structure is used for isolation at the first selected position, which avoids the bird beak problem caused by the local oxidation isolation structure.

[0026] Additional aspects and advantages of the present application will be made apparent by the following description and the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0027] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate exemplary embodiments of the present application and together with the description serve to explain the present application. In the drawings:

[0028] Figure 1 A cross-sectional structure schematic diagram of the NLDMOS device in the comparative example;

[0029] Figure 2 A flowchart of the preparation method of the metal oxide semiconductor device provided in the embodiments of the present application;

[0030] Figures 3 to 9 A cross-sectional structure schematic diagram of the NLDMOS device in the preparation process provided in the embodiments of the present application. DETAILED DESCRIPTION

[0031] The exemplary embodiments of the present application will be described more fully hereinafter with reference to the accompanying drawings, in which exemplary embodiments of the present application are shown. The present application may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0032] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. However, it will be apparent to one skilled in the art that the present application can be practiced without one or more of these specific details. In other instances, well-known features have not been described in detail to avoid obscuring the present application. There is no intention to limit the present application to the exact details shown, nor to the exact description needed to practice the present application.

[0033] In the drawings, the size of layers, regions, elements and the relative sizes of the same can be exaggerated for clarity. Like numbers signify like elements throughout.

[0034] It will be understood that when an element or layer is referred to as being "on", "adjacent", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent, connected or coupled to the other element or layer, or one or more intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on", "directly adjacent", "directly connected to", or "directly coupled to" another element or layer, then there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. can be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present application and, similarly, a second element, component, region, layer or section discussed below could be termed a first element, component, region, layer or section without departing from the teachings of the present application.

[0035] Spatially relative terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for ease of description to describe one element or feature's relationship to another element(s) or feature(s) as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if a device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" can encompass both an orientation of above and below. The device can be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

[0036] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the present application. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising", when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] For a thorough understanding of the present application, detailed steps and detailed structures will be presented in the following description in order to illustrate the technical solutions of the present application. The preferred embodiments of the present application are described in detail as follows, however, in addition to these detailed descriptions, the present application can also have other implementation manners.

[0038] Figure 1 A schematic diagram of a cross-sectional structure of an NLDMOS device in a comparative example. The NLDMOS device is specifically an N-type LDMOS device, i.e., an N-type lateral diffusion metal oxide semiconductor device. In the comparative example, the top layer 114 is formed by using a method in the prior art. Specifically, in order to add the top layer 114 to reduce the surface electric field of the NLDMOS device, it is necessary to first form a mask layer on the substrate 110 in the preparation process, and to pattern the mask layer to have an opening exposing a preset formation region of the top layer 114; next, local ion implantation is performed by using the patterned mask layer to form the top layer 114 in the drift region 111; then, the shallow trench isolation structure 120 is formed on the top layer 114. In addition, the shallow trench isolation structure 120 is also formed at other positions of the device that need to be isolated. In the art, the shallow trench isolation structure can also be referred to as STI (Shallow Trench Isolation).

[0039] In the comparative example, under the condition that the depth of the drift region 111 is constant, after the top layer 114 is formed, the remaining depth of the drift region 111 at the corresponding position is small due to the deep depth of the shallow trench isolation structure 120, so that the longitudinal cross-sectional area is small, and the on-resistance of the device is large. Here, the longitudinal cross-sectional area refers to the cross-sectional area in the thickness direction of the substrate 110, i.e., the cross-sectional area in the direction perpendicular to the substrate plane.

[0040] Moreover, in order to form the top layer 114 by ion implantation, it is necessary to first form the corresponding patterned mask layer, which increases the photolithography process cost and complicates the process flow.

[0041] Based on this, the present application provides a preparation method of a metal oxide semiconductor device, please refer to Figure 2 The method comprises the following steps:

[0042] Step 201, providing a substrate having a drift region, the drift region having a first conductivity type;

[0043] Step 202, forming a shallow trench isolation structure at a first selected position on the substrate, and forming a local oxidation isolation structure at a second selected position on the substrate; wherein the second selected position is located above the drift region;

[0044] Step 203: Ion implantation is performed on the entire upper surface of the substrate; wherein, at a first selected location, a shallow trench isolation structure blocks the implanted ions from entering the substrate; at a second selected location, the implanted ions pass through a localized oxide isolation structure to form a top layer having a second conductivity type in a drift region below the localized oxide isolation structure; the second conductivity type is electrically opposite to the first conductivity type.

[0045] Understandably, the embodiments of this application, by forming a top layer with a second conductivity type in the drift region below the localized oxide isolation structure, not only increase the depletion of the drift region and reduce the surface electric field, thus improving the breakdown voltage of the device; at the same time, compared with the shallow trench isolation structure, the localized oxide isolation structure has a smaller depth. Utilizing this depth advantage of the localized oxide isolation structure, a larger longitudinal cross-sectional area for electron movement can be retained in the drift region, thereby reducing the on-resistance of the device; based on this, the localized oxide isolation structure is not used for isolation on the entire substrate, but rather above the area where the top layer with the second conductivity type needs to be formed, while shallow trench isolation structures are still provided at other locations. Ion implantation is then performed using the height difference between the shallow trench isolation structure and the localized oxide isolation structure to form a top layer with the second conductivity type in the drift region below the localized oxide isolation structure. Thus, localized ion implantation is not required using a photolithography mask, saving process time and reducing process costs; simultaneously, using a shallow trench isolation structure for isolation at the first selected location avoids the bird's beak problem caused by the localized oxide isolation structure.

[0046] Below, in conjunction with Figures 3 to 9 The schematic diagram of the cross-sectional structure of the NLDMOS device shown in the fabrication process provides a further detailed explanation of the technical solution of this application.

[0047] It should be noted that the method for fabricating metal oxide semiconductor devices provided in this application embodiment can be used for the fabrication of LDMOS devices, especially NLDMOS devices, but this does not mean that it is only applicable to the fabrication of LDMOS devices or NLDMOS devices. Obviously, other metal oxide semiconductor devices with similar requirements can also be fabricated using the method provided in this application embodiment.

[0048] First, please refer to Figure 3 Step 201 is performed, providing a substrate 110 with a drift region 111.

[0049] In the embodiments of the present application, the term "substrate" refers to a carrier on which a subsequent material layer is added, which can be a growth substrate or can include an epitaxial layer. The upper surface of the substrate generally refers to the side on which the semiconductor device is formed. In addition, the substrate also includes a lower surface opposite the upper surface, the plane on which the upper surface and the lower surface of the substrate lie, or the central plane in the thickness direction of the substrate in the strict sense, i.e., the substrate plane is determined; the direction parallel to the substrate plane is the planar direction along the substrate. The direction perpendicular to the substrate plane is the thickness direction of the substrate, or the height direction of the device, the depth direction of each region; the thickness direction of the substrate is also the layer stacking direction of the subsequent deposition of each material layer on the substrate.

[0050] The substrate 110 is specifically a semiconductor substrate, for example, a silicon substrate.

[0051] The drift region 111 can be a region having a first conductivity type.

[0052] In some embodiments, the drift region 111 can be formed by ion doping of the substrate 110 with a first conductivity type, and the specific process of doping is, for example, ion implantation. Specifically, the substrate 110 can have a second conductivity type. Taking an NLDMOS device as an example, the substrate 110 is a P-type semiconductor substrate, and the drift region 111 is an N-type drift region. Moreover, the drift region 111 can be specifically an HNDR region (HV N-Drift region implant).

[0053] In addition, in other embodiments, the substrate 110 includes a growth substrate and an epitaxial layer having a first conductivity type formed by epitaxy on the growth substrate, and the drift region 111 can be a part of the region in the epitaxial layer.

[0054] Optionally, the metal-oxide-semiconductor device can have at least two drift regions 111, so as to form at least two drain regions in subsequent processes.

[0055] Next, please refer to Figure 4 Step 202 is performed to form a shallow trench isolation structure 120 at a first selected position on the substrate 110, and to form a local oxidation isolation structure 130 at a second selected position on the substrate 110; wherein the second selected position is located above the drift region 111.

[0056] Specifically, the local oxidation isolation structure 130 can be formed in a part of the region above the drift region 111; in other words, the local oxidation isolation structure 130 does not completely cover above the drift region 111.

[0057] The local oxidation isolation structure 130 is, for example, a local oxidation of silicon (LOCOS) isolation structure.

[0058] The depth of the local oxidation isolation structure 130 is, for example, 800-1200 angstroms. Research shows that when the depth of the local oxidation isolation structure 130 is less than 800 angstroms, the isolation effect can not be guaranteed; when the depth of the local oxidation isolation structure 130 is greater than 1200 angstroms, ions injected in a subsequent process to form the top layer 114 having the second conductivity type can not be able to pass through the local oxidation isolation structure 130. As a specific example, the depth of the local oxidation isolation structure 130 is 1000 angstroms.

[0059] The depth of the shallow trench isolation structure 120 is, for example, 3500-4500 angstroms. Research shows that when the depth of the shallow trench isolation structure 120 is less than 3500 angstroms, ions injected in a subsequent process to form the top layer 114 having the second conductivity type can pass through the shallow trench isolation structure 120 and form a doped region in the substrate 110 below the shallow trench isolation structure 120, reducing device yield; when the depth of the shallow trench isolation structure 120 is greater than 4500 angstroms, the shallow trench isolation process takes a long time, which is not conducive to shortening the overall device process. As a specific example, the depth of the shallow trench isolation structure 120 is 4000 angstroms.

[0060] Please continue to refer to Figure 4 In a specific example, the height of the upper surface of the local oxidation isolation structure 130 is higher than the height of the upper surface of the substrate 110. Compared with the shallow trench isolation structure 120, the height of the upper surface of the local oxidation isolation structure 130 is higher than the height of the upper surface of the shallow trench isolation structure 120.

[0061] Next, please refer to Figure 7 Step 203 is performed, ion implantation is performed on the entire upper surface of the substrate 110; wherein, at the first selected position (refer to the position where the shallow trench isolation structure 120 is located in the figure), the shallow trench isolation structure 120 blocks the implanted ions from entering the substrate 110; at the second selected position (refer to the position where the local oxidation isolation structure 130 is located in the figure), the implanted ions pass through the local oxidation isolation structure 130 to form the top layer 114 having the second conductivity type in the drift region 111 below the local oxidation isolation structure 130; the second conductivity type is electrically opposite to the first conductivity type.

[0062] Specifically, in the embodiments of the present application, no mask layer is provided for forming the top layer 114, and the corresponding photolithography process is omitted, and the height difference between the shallow trench isolation structure 120 and the local oxidation isolation structure 130 is utilized to form the top layer 114 by Blanket IMP (blanket ion implantation).

[0063] The second conductivity type is opposite to the first conductivity type, which means that if the first conductivity type is N type, the second conductivity type is P type, and if the first conductivity type is P type, the second conductivity type is N type. In other words, the second conductivity type and the first conductivity type are opposite conductivity types.

[0064] As a specific embodiment, the first conductivity type is N type, and the second conductivity type is P type. In this way, the top layer 114 can be referred to as a Ptop layer (P type top layer).

[0065] The main function of the top layer 114 is to reduce the surface electric field and improve the breakdown voltage; the top layer 114, the local oxidation isolation structure 130 on the top of the drift region 111, and the polysilicon field plate (not shown in the figure) together form a double reduced surface field (Double Resurf) effect.

[0066] The top layer 114 is located below the local oxidation isolation structure 130 and is arranged adjacent to the local oxidation isolation structure 130. In other words, the upper surface of the top layer 114 can be adjacent to the lower surface of the local oxidation isolation structure 130, and there is no other functional layer or other doped region between the two.

[0067] Next, please refer to Figure 5 As a specific embodiment, before ion implantation is performed on the entire upper surface of the substrate 110, the method can further include: forming a well region 112 with the second conductivity type in the substrate 110.

[0068] Specifically, the well region 112 with the second conductivity type is a P type well region. The well region 112 with the second conductivity type can be formed between the two drift regions 111. In the NLDMOS device, the well region 112 with the second conductivity type is specifically a middle voltage P well region (MVP).

[0069] In addition, the method can further include: forming a well region 113 with the first conductivity type in the drift region 111.

[0070] Specifically, the well region 113 with the first conductivity type is an N-type well region. The well region 113 with the first conductivity type is formed in the region of the drift region 111 between the shallow trench isolation structure 120 and the local oxidation isolation structure 130. In the NLDMOS device, the well region 113 with the first conductivity type is specifically a middle voltage N-well region (MVN).

[0071] For the sake of distinction, the well region 112 with the second conductivity type can also be referred to as the first well region 112, and the well region 113 with the first conductivity type can also be referred to as the second well region 113.

[0072] Next, please refer to Figure 6 As a specific implementation, the method can further include: forming a gate structure on the substrate 110 (please refer to 140, 141, 150 in the figure); wherein, along the thickness direction of the substrate 110, the gate structure at least partially overlaps the first well region 112; the gate structure covers the region of the substrate 110 between the first well region 112 and the drift region 111.

[0073] Specifically, the gate structure can include a gate dielectric layer 140 and a gate 150 formed on the substrate 110 in sequence; in addition, it can also include a gate sidewall 141. The gate dielectric layer 140 can be a gate oxide layer, such as a silicon oxide layer. The gate 150 can be a polysilicon gate. The gate sidewall 141 covers the sidewall of the gate 150; the material of the gate sidewall 141 can be the same as that of the gate dielectric layer 140.

[0074] In this specific implementation, when step 203 is performed, the gate structure serves as a barrier layer for ion implantation, blocking the implanted ions from entering the substrate 110. Therefore, no ions are implanted in the region of the substrate 110 between the first well region 112 and the drift region 111.

[0075] Further, when step 203 is performed, the parts of the device structure that are directly in contact with the implanted ions are the shallow trench isolation structure 120, the local oxidation isolation structure 130, the first well region 112, the second well region 113, and the gate structure. Among them, the shallow trench isolation structure 120 and the gate structure can both block the implanted ions from entering the substrate 110 (specifically, entering the region of the substrate 110 below the shallow trench isolation structure 120 and the region below the gate structure); while the first well region 112 and the second well region 113 are themselves doped regions formed by ion implantation, and the effect of the implanted ions on the first well region 112 and the second well region 113 is within an acceptable range; only at the position of the local oxidation isolation structure 130, the implanted ions enter the drift region 111 below the local oxidation isolation structure 130, thereby forming the top layer 114.

[0076] It can be understood that the structure of the gate dielectric layer 140 and the gate 150 formed in sequence is only schematically shown in the figure, and although the gate dielectric layer 140 and the gate 150 both have flat upper surfaces in the figure, in the actual process, the upper surfaces of the gate dielectric layer 140 and the gate 150 can not be flat due to the influence of the topography of the local oxidation isolation structure 130.

[0077] In addition, the number of the gate structures can be two, and the two gate structures at least partially overlap with the first well region 112 at two ends of the first well region 112 respectively; one of the two gate structures covers the region of the substrate 110 between one end of the first well region 112 and one drift region 111, and the other covers the region of the substrate 110 between the other end of the first well region 112 and the other drift region 111.

[0078] The part of the first well region 112 overlapping with the gate structure is formed as a channel of the device.

[0079] Next, please refer to Figure 8 As a specific embodiment, the method can further include: forming a body region 115 having a second conductivity type in the first well region 112; forming a body pull-out region 117 of the second conductivity type heavily doped and a source region 118 of the first conductivity type heavily doped in the body region 115; and forming a drain region 116 of the first conductivity type heavily doped in the second well region 113.

[0080] Specifically, the first well region 112 is a middle voltage P well region, the body region 115 having the second conductivity type is a Pbody region, the body pull-out region 117 of the second conductivity type heavily doped is a P+ region, and the source region 118 of the first conductivity type heavily doped and the drain region 116 of the first conductivity type heavily doped are both N+ regions.

[0081] The body pull-out region 117 and the source region 118 are laterally contacted.

[0082] Next, please refer to Figure 9As a specific embodiment, the method can further include: forming an interlayer dielectric film (not shown in the figure) on the substrate 110; forming a contact hole through the interlayer dielectric film, the contact hole exposing the source region 118, the body lead-out region 117, the drain region 116 and the gate 150; filling a contact plug in the interlayer dielectric film and forming a metal layer on the upper surface of the interlayer dielectric film, and further forming a source electrode 171, a drain electrode 172 and a gate electrode 173 by photoetching; correspondingly, the contact plug filled in the interlayer dielectric film is a source contact plug 161, a drain contact plug 162 and a gate contact plug 163 respectively. The source electrode 171 is in contact with the source region 118 and the body lead-out region 117 through the source contact plug 161, the drain electrode 172 is in contact with the drain region 116 through the drain contact plug 162, and the gate electrode 173 is in contact with the gate 150 through the gate contact plug 163.

[0083] As a specific embodiment, the metal oxide semiconductor device is an N-type lateral diffusion metal oxide semiconductor device.

[0084] On this basis, the embodiment of the present application further provides a metal oxide semiconductor device, please continue to refer to Figure 9 The device includes:

[0085] The substrate 110 has a drift region 111, and the drift region 111 has a first conductivity type;

[0086] The shallow trench isolation structure 120 is located at a first selected position on the substrate 110, and the local oxidation isolation structure 130 is located at a second selected position on the substrate 110; wherein the second selected position is located above the drift region 111;

[0087] The top layer 114 is located in the drift region 111 below the local oxidation isolation structure 130, and the top layer 114 has a second conductivity type; the second conductivity type is opposite in electrical properties to the first conductivity type.

[0088] As a specific embodiment, the depth of the local oxidation isolation structure 130 is 800Å~1200Å; and / or, the depth of the shallow trench isolation structure 120 is 3500Å~4500Å.

[0089] As a specific embodiment, the first conductivity type is N-type, and the second conductivity type is P-type.

[0090] As a specific embodiment, the device further includes:

[0091] The well region 112 is located in the substrate 110, and the well region 112 has the second conductivity type;

[0092] A gate structure is located on the substrate 110; wherein, along the thickness direction of the substrate 110, the gate structure at least partially overlaps with the well region 112; the gate structure covers the region of the substrate 110 between the well region 112 and the drift region 111.

[0093] As a specific embodiment, the metal oxide semiconductor device is an N-type lateral diffusion metal oxide semiconductor device.

[0094] It should be noted that the metal oxide semiconductor device embodiments provided in the present application and the preparation method embodiments of the metal oxide semiconductor device belong to the same concept; the technical features in the technical solutions recorded in each embodiment can be arbitrarily combined without conflict.

[0095] It should be understood that the above embodiments are exemplary and are not intended to include all possible embodiments included in the claims. Various modifications and changes can also be made to the above embodiments without departing from the scope of the present disclosure. Similarly, any combination of the technical features of the above embodiments can also be made to form additional embodiments of the present application which may not have been explicitly described. Therefore, the above embodiments only express several embodiments of the present application and do not limit the protection scope of the patent of the present application.

Claims

1. A method of manufacturing a metal oxide semiconductor device, characterized by, The method comprises: providing a semiconductor substrate with a drift region, the drift region having a first conductivity type; forming a shallow trench isolation structure at a first selected position on the semiconductor substrate, and forming a local oxidation isolation structure at a second selected position on the semiconductor substrate; wherein the second selected position is above the drift region; performing ion implantation on the entire upper surface of the semiconductor substrate; wherein at the first selected position, the shallow trench isolation structure blocks the implanted ions from entering the semiconductor substrate; at the second selected position, the implanted ions pass through the local oxidation isolation structure to form a top layer having a second conductivity type within the drift region below the local oxidation isolation structure; the second conductivity type is electrically opposite to the first conductivity type.

2. The method for manufacturing a metal oxide semiconductor device according to claim 1, wherein The depth of the local oxidation isolation structure is 800-1200 angstroms; and / or, the depth of the shallow trench isolation structure is 3500-4500 angstroms.

3. The method of producing a metal-oxide semiconductor device according to claim 1, wherein The first conductivity type is N-type, and the second conductivity type is P-type.

4. The method for manufacturing a metal oxide semiconductor device according to claim 1, wherein Before performing ion implantation on the entire upper surface of the semiconductor substrate, the method further comprises: forming a well region having a second conductivity type within the semiconductor substrate; forming a gate structure on the semiconductor substrate; wherein along the thickness direction of the semiconductor substrate, the gate structure at least partially overlaps with the well region; the gate structure covers the region of the semiconductor substrate between the well region and the drift region.

5. The method of producing a metal oxide semiconductor device according to claim 1, wherein The metal oxide semiconductor device is an N-type lateral diffusion metal oxide semiconductor device.

6. A metal oxide semiconductor device, characterized by, Comprise: a semiconductor substrate with a drift region, the drift region having a first conductivity type; a shallow trench isolation structure at a first selected position on the semiconductor substrate, and a local oxidation isolation structure at a second selected position on the semiconductor substrate; wherein the second selected position is above the drift region; a top layer within the drift region below the local oxidation isolation structure, the top layer having a second conductivity type; the top layer is formed by performing ion implantation on the entire upper surface of the semiconductor substrate, during which at the first selected position, the shallow trench isolation structure blocks the implanted ions from entering the semiconductor substrate, and at the second selected position, the implanted ions pass through the local oxidation isolation structure to form the top layer; the second conductivity type is electrically opposite to the first conductivity type.

7. The metal oxide semiconductor device of claim 6, wherein, The depth of the local oxidation isolation structure is 800-1200 angstroms; and / or, the depth of the shallow trench isolation structure is 3500-4500 angstroms.

8. The metal oxide semiconductor device of claim 6, wherein, The first conductivity type is N-type, and the second conductivity type is P-type.

9. The metal oxide semiconductor device of claim 6, wherein, Further comprise: a well region having a second conductivity type within the semiconductor substrate; a gate structure on the semiconductor substrate; wherein along the thickness direction of the semiconductor substrate, the gate structure at least partially overlaps with the well region; the gate structure covers the region of the semiconductor substrate between the well region and the drift region.

10. The metal oxide semiconductor device of claim 6, wherein, The metal oxide semiconductor device is an N-type lateral diffusion metal oxide semiconductor device. The metal oxide semiconductor device is an N-type lateral diffusion metal oxide semiconductor device.

Images