Three-dimensional core particle packaging process and structure integrated at back of deep trench device

Abstract

The application relates to a three-dimensional core particle packaging process and structure integrated with deep groove devices at the back of the device. The application comprises the following steps: providing a core particle packaging substrate, wherein the core particle packaging substrate comprises a main chip and a core particle group which is plasticized on the front surface of the main chip, the core particle group comprises at least one core particle, and the core particles in the core particle group are interconnected with the main chip; performing a deep groove device integration process on the back surface of the main chip of the core particle packaging substrate to integrate required deep groove devices on the back surface of the main chip, the deep groove devices comprise deep groove capacitors and / or deep groove inductors, and the deep groove devices are electrically connected with the main chip and / or corresponding core particles in the core particle group; after the deep groove device integration, preparing an outgoing connection assembly on the back surface of the main chip, and using the prepared outgoing connection assembly to lead out the core particle packaging body formed by electrically connecting the main chip, the core particle group and the deep groove devices from the back surface of the main chip. The application can meet the large-area integration of deep groove capacitors and deep groove inductors, and improve the integration density and reliability.

Description

Technical Field

[0001] This invention relates to a three-dimensional chip packaging process and structure, and more particularly to a three-dimensional chip packaging process and structure for back-side integration of deep trench devices. Background Technology

[0002] As the number of system I / O (input / output) devices continues to increase, traditional two-dimensional packaging structures can no longer meet application requirements, necessitating higher-density three-dimensional stacked packaging structures. However, traditional three-dimensional packaging structures, limited by conventional packaging processes, cannot meet extremely high-density I / O demands, requiring the adoption of more advanced packaging technologies for integration.

[0003] As the voltage switching frequency of power systems continues to increase, capacitors need to be placed as close as possible to the power network. However, traditional solutions use discrete capacitors soldered onto the PCB (Printed Circuit Board), which fails to meet the proximity requirement.

[0004] As system power supplies increase, the required inductance values ​​embedded in these systems also increase. However, high-inductance inductors at the chip level are relatively scarce in the industry, making it difficult to achieve the required inductance values ​​for practical applications. Currently, high-inductance inductors are mostly integrated using external high-inductance passive components.

[0005] As explained above, in existing technologies, when capacitors and high-inductance inductors need to be integrated, they are often packaged separately and then interconnected on a PCB board to form a system, i.e., a two-dimensional system. This two-dimensional system results in a relatively large final system size, failing to meet the requirements for a compact and lightweight design. Furthermore, the use of separate packages increases the interconnect length between signals, which cannot meet the requirements for high frequency and high speed.

[0006] In 3D stacked packaging, a large area is required during stacking. Therefore, how to effectively achieve large-area integration of capacitors and inductors is a technical problem that urgently needs to be solved in 3D stacked packaging. Summary of the Invention

[0007] The purpose of this invention is to overcome the shortcomings of the existing technology and provide a three-dimensional chip packaging process and structure for back-side integration of deep trench devices, which can meet the large-area integration of deep trench capacitors and deep trench inductors, and improve the integration density and reliability.

[0008] According to the technical solution provided by the present invention, the three-dimensional chip packaging process for back-side integration of the deep trench device includes:

[0009] A chip packaging substrate is provided, wherein the chip packaging substrate includes a main chip and a chip assembly molded on the front side of the main chip, the chip assembly including at least one chip, and the chip in the chip assembly being interconnected with the main chip;

[0010] For the above-mentioned chip packaging substrate, a deep trench device integration process is performed on the back side of the main chip to integrate the required deep trench devices on the back side of the main chip. The deep trench devices include deep trench capacitors and / or deep trench inductors, and the deep trench devices are electrically connected to the corresponding chip adapters in the main chip and / or chip group.

[0011] After the deep trench device is integrated, a lead-out connection component is prepared on the back side of the main chip. The chip package formed by the main chip, chip assembly, and deep trench device adapter electrical connection is led out from the back side of the main chip using the prepared lead-out connection component.

[0012] When integrating deep trench devices on the back side of the main chip, the integration process includes...

[0013] The required device slots are fabricated on the back side of the main chip, and the device slots extend perpendicularly from the back side of the main chip to the front side of the main chip.

[0014] A device body is fabricated within the aforementioned device groove, wherein the device body fills the device groove to form the desired deep groove device using the filled device body.

[0015] For deep-groove capacitors within deep-groove devices, the deep-groove capacitors include deep-groove interdigitated capacitors, wherein,

[0016] The device slot includes a capacitor slot for forming the deep slot interdigitated capacitor, and the device body includes interdigitated capacitor electrodes for forming the deep slot interdigitated capacitor.

[0017] The interdigitated capacitor electrode includes alternating first capacitor electrode bodies and second capacitor electrode bodies.

[0018] For the deep trench inductor within the deep trench device, the deep trench inductor is spiral-shaped, wherein,

[0019] The device slots include inductor slots for forming deep trench inductors, which are spiral-shaped within the main chip;

[0020] The device body includes inductor pillars for forming deep trench inductors, and within the main chip, the shape of the inductor pillars matches the shape of the inductor trench.

[0021] When performing deep trench device integration on the chip packaging substrate, the chip packaging substrate is first temporarily bonded to a support carrier. After the temporary bonding, the molding layer in the chip packaging substrate for molding the chip assembly is in contact with the support carrier.

[0022] After the lead-out connection assembly is fabricated, the bonding connection between the support carrier and the molding layer is released to form the desired core package.

[0023] The lead-out connection assembly includes a back metal layer fabricated on the back side of the main chip and a set of solder balls adapted to the back metal layer, wherein...

[0024] The back metal layer includes a back first pad and a back second pad. The back first pad is connected to the on-chip interconnect post in the main chip. The deep trench device is electrically connected to the main chip and the corresponding chip adapter in the chip group through the back first pad and the on-chip interconnect post electrically connected to the back first pad.

[0025] The solder ball assembly includes a plurality of first solder balls and a plurality of second solder balls. The first solder balls are aligned with the first pad on the back side for electrical connection, and the second solder balls are aligned with the second pad on the back side for electrical connection.

[0026] The main chip includes several device component areas, among which,

[0027] The device component area corresponds directly to the front side of the main chip. One chip in the chip group is electrically connected to the corresponding device component area in the main chip. The deep-groove device is electrically connected to the corresponding device component area in the main chip through the on-chip connection post, so that the chip and the main chip are interconnected, and the deep-groove device is electrically connected to the main chip and / or the corresponding chip.

[0028] The preparation of the chip encapsulation substrate includes:

[0029] A main chip is provided, and a front metal layer is formed on the front side of the main chip;

[0030] A chip assembly is provided, wherein the chips in the chip assembly are soldered and bonded to a front metal layer to electrically connect with the corresponding device component area in the main chip using the soldered and bonded front metal layer.

[0031] A molding process is performed to mold the chips within the chip assembly onto the front side of the main chip to form a chip package substrate.

[0032] When preparing the back metal layer, the back side of the main chip is first thinned so that the ends of the on-chip interconnects are exposed from the back side of the main chip.

[0033] After thinning, the required back metal layer is fabricated on the back of the main chip.

[0034] A three-dimensional chip packaging structure for back-side integration of a deep-groove device is prepared using the above-described packaging process.

[0035] Advantages of the present invention: interconnecting the chips in the chip group with the main chip, and integrating deep trench devices on the back of the main chip, including deep trench capacitors or deep trench inductors, thereby forming a chip package, improving system integration and reducing package size.

[0036] Integrating deep-slot capacitors and / or deep-slot inductors on the back of the main chip eliminates the need for external capacitors / inductors compared to existing technologies, reducing the overall package size and facilitating system integration while ensuring a significant improvement in system performance. Furthermore, compared to traditional surface-mount capacitors and inductors, integrating deep-slot capacitors and inductors on the back of the main chip allows for large-area integration, increasing integration density and reliability, while avoiding crowded space on the front side, further enabling a significant increase in capacitance and inductance values.

[0037] Furthermore, the electrical connection to the device component area and / or core allows deep-slot capacitors and deep-slot inductors to be closer to the device component area and / or core where electrical connection is required, thereby improving device performance.

[0038] In traditional SIP packaging, the chip and the main chip are interconnected by direct soldering bonding, which reduces the transmission path of high-frequency signals and is suitable for high-frequency applications; it can effectively expand the application scenarios of chip packages. Attached Figure Description

[0039] Figures 1 to 14 This is one embodiment of the packaging process of the present invention, wherein,

[0040] Figure 1 This is a schematic diagram of the main chip unit and the chip assembly provided by the present invention.

[0041] Figure 2 This is a schematic diagram showing the interconnection between the chip and the main chip unit within the chip group of the present invention.

[0042] Figure 3 This is a schematic diagram of the core assembly after being encapsulated using a molding substrate according to the present invention.

[0043] Figure 4 This is a schematic diagram of the molding layer formed by thinning the molding substrate according to the present invention.

[0044] Figure 5 This is a schematic diagram of the present invention after temporary bonding with the support carrier plate.

[0045] Figure 6 This is a schematic diagram of the main chip formed by thinning the back side of the main chip substrate according to the present invention.

[0046] Figure 7 This is a schematic diagram showing the capacitor and inductor slots fabricated on the back of the main chip according to the present invention.

[0047] Figure 8 This is a schematic diagram of one embodiment of the capacitor groove of the present invention.

[0048] Figure 9 This is a schematic diagram of one embodiment of the inductor groove of the present invention.

[0049] Figure 10 This is a schematic diagram of the deep trench capacitor and deep trench inductor fabricated according to the present invention.

[0050] Figure 11 This is a schematic diagram of the lead-out connection component after the present invention has been prepared.

[0051] Figure 12 This is a schematic diagram of one embodiment of the deep trench capacitor of the present invention.

[0052] Figure 13 This is a schematic diagram of one embodiment of the deep trench inductor of the present invention.

[0053] Figure 14 This is a schematic diagram of the mental encapsulation formed according to the present invention.

[0054] Explanation of reference numerals in the attached diagram: 1-Main chip substrate, 2-Device component area, 3-In-chip interconnect pillar, 4-Front-side metal layer, 5-Core chip, 6-Core chip pad, 7-Molded substrate, 8-Molded layer, 9-Supporting carrier, 10-Main chip, 11-Capacitor slot, 12-Inductor slot, 13-First vertical slot of capacitor, 14-Second vertical slot of capacitor, 15-First horizontal slot of capacitor, 16-Second horizontal slot of capacitor, 17-Spiral slot, 18-First electrode of capacitor, 19-Second electrode of capacitor, 20-Inductor pillar, 21-Deep slot capacitor, 22-Deep slot inductor, 23-First pad on the back side, 24-Second pad on the back side, 25-First solder ball connecting to the back side, 26-Second solder ball connecting to the back side, 27-First electrode body connector, 28-Second electrode body connector, 29-First pin of capacitor, 30-Second pin of capacitor, 31-First pin of inductor, 32-Second pin of inductor. Detailed Implementation

[0055] The present invention will be further described below with reference to specific accompanying drawings and embodiments.

[0056] To achieve large-area integration of capacitors and inductors and improve integration density and reliability, this invention employs a deep-groove device composed of capacitors and / or inductors integrated on the back side. In one embodiment of this invention, the three-dimensional chip packaging process for back-side integration of the deep-groove device includes:

[0057] A chip packaging substrate is provided, wherein the chip packaging substrate includes a main chip 10 and a chip assembly molded on the front side of the main chip 10, the chip assembly including at least one chip 5, and the chip 5 in the chip assembly being interconnected with the main chip 10.

[0058] For the above-mentioned chip packaging substrate, a deep trench device integration process is performed on the back side of the main chip 10 to integrate the required deep trench devices on the back side of the main chip 10. The deep trench devices include deep trench capacitors 21 and / or deep trench inductors 22, and the deep trench devices are adapted to be electrically connected to the corresponding chip 5 in the main chip 10 and / or chip group.

[0059] After the deep trench device is integrated, a lead-out connection component is prepared on the back side of the main chip 10. The chip package formed by the main chip 10, the chip assembly, and the deep trench device adapter electrical connection is led out from the back side of the main chip 10 using the prepared lead-out connection component.

[0060] In the specific process, a chip packaging substrate needs to be provided first. The chip packaging substrate provided includes at least a main chip 10 and a chip group molded on the front side of the main chip 10. The chip group includes at least one chip 5. The chip 5 is generally a small chip (Chiplet) prepared by existing processes. The size of the chip 5 is smaller than that of the main chip 10.

[0061] The main chip 10 can adopt a commonly used form. Generally, the main chip 10 has a front side and a back side corresponding to the front side. For example, the front side of the main chip 1 is used as the component side. Therefore, the chip 5 is electrically connected to the front side of the main chip 10 to realize the interconnection between the chip 5 and the main chip 10. Specifically, the interconnection means that the chip 5 and the main chip 10 can perform the required information exchange. In order to protect the chip 5, the chip assembly needs to be encapsulated on the front side of the main chip 10 using a molding compound layer 8.

[0062] In one embodiment of the present invention, the preparation of the chip encapsulation substrate includes:

[0063] A main chip 10 is provided, and a front metal layer 4 is disposed on the front side of the main chip 10;

[0064] A chip assembly is provided, wherein the chip 5 in the chip assembly is soldered and bonded to the front metal layer 4 so as to electrically connect the soldered and bonded front metal layer 4 to the corresponding device component area 2 in the main chip 10.

[0065] A molding process is performed to mold the chip 5 within the chip assembly onto the front side of the main chip 10 to form a chip package substrate.

[0066] like Figures 1-6 The diagram illustrates a specific implementation step for providing a chip packaging substrate. Figures 1-6 In this process, the main chip 10 is formed from the main chip substrate 1 through a manufacturing process.

[0067] Figure 1The system provides a main chip substrate 1 and a chip assembly. The main chip substrate 1 includes several device component regions 2, which correspond to the front side of the main chip substrate 1. Specifically, the device component regions 2 are located within the front side or exposed from the front side. The number and corresponding functions of the device component regions 2 within the main chip substrate 1 can be selected and determined according to the actual application scenario. For example, the device component regions 2 can be functional areas such as power supply or storage. The device component regions 2 within the main chip substrate 1 can be independent of each other or interconnected. The interrelationship between the device component regions 2 can be selected according to actual needs. The main chip substrate 1 and the device component regions 2 within it can be fabricated using existing commonly used techniques, specifically based on the ability to fabricate the required main chip substrate 1.

[0068] Figure 1 In this design, several on-chip interconnect pillars 3 are embedded within the main chip substrate 1. These on-chip interconnect pillars 3 are typically made of copper. The ends of the on-chip interconnect pillars 3 adjacent to the front side of the main chip substrate 1 are electrically connected to the corresponding device component areas 2. The number of on-chip interconnect pillars 3 is generally no more than the number of device component areas 2 within the main chip substrate 1. The length of the on-chip interconnect pillars 3 is generally less than the thickness of the main chip substrate 1. The contact and electrical connection between the on-chip interconnect pillars 3 and the corresponding device component areas 2 within the main chip substrate 1 can be selected as needed to meet the actual packaging requirements.

[0069] In order to achieve connection and cooperation with the chip assembly, a front metal layer 4 is also provided on the front side of the main chip substrate 1. The front metal layer 4 can be prepared using existing commonly used processes. The front metal layer 4 covers the front side of the main chip substrate 1, and the on-chip interconnect pillars 3 and device component areas 2 are achieved by using the front metal layer 4 to achieve the required electrical connection and cooperation.

[0070] Figure 1 The figure illustrates an implementation where a chip assembly includes two chips 5. In the figure, the two chips 5 correspond to the front side of the main chip substrate 1 and are interconnected with the main chip substrate 1. The two chips 5 can be the same chip or two different chips. Chips 5 serve as functional chips, and their specific functions can be selected according to actual needs. The interconnection between chips 5 and the main chip substrate 1 is illustrated when several device component areas 2 are disposed within the main chip substrate 1.

[0071] Each chip 5 generally includes a chip pad 6, and the fit between the chip pad 6 and the chip 5 is consistent with existing methods. When the chip 5 is interconnected with the main chip substrate 1, the chip pad 6 of the chip 5 is soldered and bonded to the front metal layer 4. As can be seen from the above description, at this time, the chip 5 can be electrically connected to the device component area 2 within the main chip substrate 1 to achieve the required interconnection between the chip 5 and the main chip 10, such as... Figure 2 As shown.

[0072] To protect the front side of the main chip substrate 1 and the chip assembly, a molding process is required on the front side of the main chip substrate 1. After the molding process, a molding substrate 7 is obtained. The chip assembly is then molded onto the front side of the main chip substrate 1 using the molding substrate 7. The thickness of the molding substrate 7 is greater than the height of the chip 5, meaning that the chip 5 is entirely located within the molding substrate 7. Figure 3 As shown. The molding process, and the process of obtaining the molding substrate 7 based on the molding process, can be consistent with existing methods, as long as the desired molding substrate 7 can be obtained.

[0073] After obtaining the molding substrate 7, the molding substrate 7 can be thinned using commonly used thinning methods to obtain the molding layer 8. The thickness of the thinning of the molding substrate 7 should be such that the back side of the core 5 is exposed. Figure 4 As shown, when the back side of core 5 is exposed, it facilitates heat dissipation of core 5 or subsequent stacking processes.

[0074] To facilitate deep-groove device integration, a support substrate 9 is provided. The support substrate 9 is temporarily bonded to the molding compound 8. After temporary bonding, the back surfaces of the molding compound and the core 5 make corresponding contact with the support substrate 9. Figure 5 As shown.

[0075] The support carrier 9 can adopt commonly used forms, such as a glass carrier, and can be selected according to actual needs. The support carrier 9 is used to position the back side of the main chip substrate 1 facing upwards, so that the back side of the main chip substrate 1 can be processed. As described above, the length of the in-chip interconnect 3 is less than the thickness of the main chip substrate 1. Therefore, the back side of the main chip substrate 1 needs to be thinned so that the end of the in-chip interconnect 3 adjacent to the main chip substrate 1 is exposed. At this point, the main chip 1 is formed using the main chip substrate 1. Figure 6 As shown.

[0076] use Figures 1-6 After the chip packaging substrate is prepared by the process steps, deep trench device integration needs to be performed on the back side of the main chip 10. In one embodiment of the present invention, when performing deep trench device integration on the back side of the main chip 10, the integration process includes...

[0077] The required device slots are fabricated on the back side of the main chip 10, and the device slots extend vertically from the back side of the main chip 10 toward the front side of the main chip 10.

[0078] A device body is fabricated within the aforementioned device groove, wherein the device body fills the device groove to form the desired deep groove device using the filled device body.

[0079] For the chip packaging substrate prepared above, the deep trench device is electrically connected to the corresponding device element area 2 within the main chip 10 via the on-chip connection post 3, so that the chip 5 is interconnected with the main chip 10, and the deep trench device is electrically connected to the main chip 10 and / or the corresponding chip 5. Specifically, the interconnection between the chip 5 and the main chip 10 is achieved when the deep trench device is electrically connected to the corresponding device element area 2 via the on-chip connection post 3.

[0080] Figures 7-10 The diagram illustrates one implementation process for integrating deep trench devices on the back side of the main chip 10. Figure 7 In this process, device slots are fabricated on the back side of the main chip 10 using commonly used techniques. Specifically, the deep-slot devices can be deep-slot capacitors 21 and / or deep-slot inductors 22, and the type of deep-slot device can be determined according to the actual application scenario. When the deep-slot device includes a deep-slot capacitor 21, the device slot includes at least a capacitor slot 11; when the deep-slot device includes a deep-slot inductor 22, the device slot includes at least an inductor slot 12. Specifically, the corresponding number of deep-slot capacitors 21 and deep-slot inductors 22, their positions within the main chip 10, and their connection and cooperation states with the chip 5 and device component area 2 can be selected as needed to meet the actual application requirements.

[0081] Figure 7 The diagram shows a device slot that includes both a capacitor slot 11 and an inductor slot 12. Generally, the capacitor slot 11 and the inductor slot 12 are fabricated on the back side of the main chip 10 using the same process steps. The specific process conditions and procedures for fabricating the capacitor slot 11 and the inductor slot 12 can be selected according to actual needs, with the aim of fabricating the required capacitor slot 11 and inductor slot 12.

[0082] Capacitor slots 11 and inductor slots 12 extend vertically from the back of the main chip 10 towards the front of the main chip 10. The corresponding openings of the capacitor slots 11 and inductor slots 12 are located on the back of the main chip 10. Of course, when fabricating the capacitor slots 11 and inductor slots 12, it is necessary to avoid the on-chip connection pillars 3. The position of the capacitor slots 11 and inductor slots 12 within the main chip 10 is determined to meet actual connection and fit requirements, such as proximity to the power network as mentioned in the background art, and ensuring electrical connection with the required device component areas 2 and the chip 5. Therefore, after determining the chip package configuration, the distribution of the capacitor slots 11 and inductor slots 12 within the main chip 10 can be determined.

[0083] After the device tank is prepared, the device body can be prepared by processes such as electroplating. The device body is filled in the device tank, that is, the device body and the device tank are used to form the required deep tank device.

[0084] right Figure 7 The implementation includes both capacitor tank 11 and inductor tank 12. Electroplating and other processes are used to fill capacitor electrodes in capacitor tank 11 and inductor electrodes in inductor tank 12. The specific filling process and procedures can be selected according to actual needs, so as to form capacitor electrodes and inductor electrodes.

[0085] like Figure 8 and Figure 12 The diagram illustrates one embodiment of the deep trench capacitor 21. Specifically, the deep trench capacitor 21 within the deep trench device includes a deep trench interdigitated capacitor, wherein...

[0086] The device slot includes a capacitor slot 11 for forming the deep slot interdigitated capacitor, and the device body includes interdigitated capacitor electrodes for forming the deep slot interdigitated capacitor.

[0087] The interdigitated capacitor electrodes include alternating capacitor first electrode bodies 18 and capacitor second electrode bodies 19.

[0088] In practical implementation, the deep-slot capacitor 21 can be a deep-slot interdigitated capacitor. When a deep-slot interdigitated capacitor is used... Figure 8 One embodiment of capacitor slot 11 is shown in the figure. Figure 8 In the main chip 10, the capacitor slot 21 includes several alternately distributed first vertical slots 13 and second vertical slots 14. The number of first vertical slots 13 and second vertical slots 14 can be selected according to actual needs, based on meeting the actual requirements. The first vertical slots 13 and second vertical slots 14 are parallel to each other and extend vertically from the back side of the main chip 10 to the front side.

[0089] One end of each of the first longitudinal slots 13 of the capacitors is interconnected via the first transverse slot 15, and one end of each of the second longitudinal slots 14 of the capacitors is interconnected via the second transverse slot 16. The first transverse slot 15 and the first longitudinal slot 13 are interconnected, and the second transverse slot 16 and the second longitudinal slot 14 are interconnected. The length direction of the first transverse slot 15 is parallel to the length direction of the second transverse slot 16.

[0090] Figure 12 In one embodiment of forming a deep-groove interdigitated capacitor using filled capacitor electrodes, the capacitor electrodes filled in the capacitor groove 21 are interdigitated capacitor electrodes, which include alternating capacitor first electrode bodies 18 and capacitor second electrode bodies 19. Figure 8 In the capacitor, the first electrode body 18 is formed by an electrode filled in the first longitudinal groove 13 of the capacitor, and the second electrode body 19 is formed by an electrode filled in the second longitudinal groove 14 of the capacitor.

[0091] Depend on Figure 8As can be seen from the above, during filling, a first electrode connector 22 will be formed in the first transverse slot 15 of the capacitor, and a second electrode connector 23 will be formed in the second transverse slot 16 of the capacitor. The first electrode connector 22 and the first electrode 18 of the capacitor are in contact with each other and are integrated, and the second electrode connector 23 and the second electrode 19 of the capacitor are in contact with each other and are integrated.

[0092] Figure 9 and Figure 13 The image shows one embodiment of a deep trench inductor 22. Specifically, the deep trench inductor 22 within the deep trench device is spiral-shaped.

[0093] The device slot includes an inductor slot 12 for forming a deep trench inductor 22, the inductor slot 12 being spiral-shaped within the main chip 10;

[0094] The device body includes inductor posts 20 for forming a deep trench inductor 22, and within the main chip 10, the shape of the inductor posts 20 is consistent with the shape of the inductor trench 22.

[0095] In practice, the deep trench inductor 22 can be spiral-shaped. Of course, the deep trench inductor 22 can also take other forms, depending on whether it can form the required inductance value. Corresponding to the capacitor trench 11, the depth of the inductor trench 12 is also less than the thickness of the main chip 10.

[0096] Figure 9 The image shows one embodiment of the inductor slot 12. Figure 9 The inductor slot 12 is spiral-shaped, thus forming a spiral slot 17. Figure 9 In this process, the size of the spiral groove 17 and the spiral distribution can be selected according to actual needs, so as to form the required inductor groove 12.

[0097] Figure 13 In the process, the inductor post 20 is formed after filling the spiral groove 17. The spiral inductor post 20 can be used to form the required deep groove inductor 22. Generally, the inductor post 20 is formed in the same process as the first electrode body 18 and the second electrode body 19 of the capacitor. Of course, the inductor post 20 needs to be insulated from the main chip 10, and the first electrode body 18, the second electrode body 19, etc. of the capacitor also need to be insulated from the main chip 10.

[0098] Figure 10 This is a schematic diagram showing the simultaneous fabrication of a deep trench capacitor 21 and a deep trench inductor 22 within the main chip 10. In this case, the deep trench device includes a deep trench capacitor 21 and a deep trench inductor 22. Figure 10 In the middle, the deep trench capacitor 21 and the deep trench inductor 22 cannot be electrically connected to the device component area 2 on the front of the main chip 10 and the on-chip connection post 3.

[0099] Figure 11The present invention describes an embodiment of a lead-out connection assembly fabricated on the back side of the main chip 10 after deep trench device integration. The lead-out connection assembly includes a back metal layer fabricated on the back side of the main chip 10 and a set of solder balls adapted to the back metal layer.

[0100] The back metal layer includes a back first pad 23 and a back second pad 24. The back first pad 23 is connected to the on-chip interconnect 3 in the main chip 10. The deep trench device is adapted to be electrically connected to the main chip 10 and the corresponding chip 5 in the chip group through the back first pad 23 and the on-chip interconnect 3 electrically connected to the back first pad 23.

[0101] The solder ball assembly includes a plurality of first solder balls 25 and a plurality of second solder balls 26. The first solder balls 25 are aligned and electrically connected to the first pad 23 on the back side, and the second solder balls 26 are aligned and electrically connected to the second pad 24 on the back side.

[0102] In the specific process, a back metal layer is first prepared on the back side of the main chip 10, and then the solder ball assembly is prepared.

[0103] After the deep trench capacitor 21 and deep trench inductor 22 are prepared, in order to achieve the adaptive electrical connection with the device component area 2 in the main chip 10, a back metal layer needs to be prepared on the back side of the main chip 10. The back metal layer can be prepared by the RDL (ReDistribution Layer) process.

[0104] Figure 11 In the process, the back metal layer includes a first back pad 23 and a second back pad 24. Generally, the first back pad 23 and the second back pad 24 are independent of each other. The first back pad 23 is aligned and electrically connected to the on-chip interconnect post 3, and the second back pad 24 is aligned and electrically connected to the corresponding area on the back of the main chip 10. The corresponding area on the back of the main chip 10 generally refers to the functional area for implementation of the lead-out.

[0105] The back metal layer covers the back of the main chip 10. The back metal layer enables the deep trench capacitor 21, deep trench inductor 22 and the corresponding device component area 2 to make the required electrical connection.

[0106] After the back metal layer is prepared, a first capacitor pin 29 is formed at one end of the first electrode body connector 22 using the first back pad 23, and a second capacitor pin 30 is formed at one end of the second electrode body connector 23, as follows. Figure 12 As shown. Using the first pin 29 and the second pin 30 of the capacitor, the deep slot capacitor 21 can be electrically connected to the on-chip connection post 3.

[0107] Similarly, using the first pad 3 on the back side, the first inductor pin 31 and the second inductor pin 32 are formed to be electrically connected to the inductor post 20, as shown below. Figure 13 As shown. The first pin 31 and the second pin 32 of the inductor are used to achieve an adapter electrical connection with the on-chip connection post 3.

[0108] Figure 14 In this configuration, the first pin 29 of the capacitor is electrically connected to a corresponding adjacent on-chip connection post 3, and the second pin 30 of the capacitor is electrically connected to a corresponding adjacent second pad 24 on the back side. The first pin 31 and the second pin 32 of the inductor are respectively electrically connected to their corresponding adjacent on-chip connection posts 3. Of course, in specific implementations, the first pin 29, the second pin 30 of the capacitor, the first pin 31, and the second pin 32 of the inductor can also have other connection states, depending on the required connection specifications.

[0109] In summary, since the on-chip connection post 3 is adapted to the device component area 2 for electrical connection, the deep trench capacitor 21 and the deep trench inductor 22 are electrically connected to the device component area 2 through the corresponding on-chip connection post 3, or adapted to the corresponding chip 5 based on the electrical connection with the corresponding device component area 2.

[0110] After the back metal layer is prepared, the first solder ball 25 is soldered onto the first back pad 29, and the second solder ball 26 is soldered onto the second back pad 24. The first solder ball 25 and the second solder ball 26 can be directly soldered using existing commonly used soldering methods, specifically to achieve the required alignment connection between the solder ball group and the back metal layer.

[0111] After fabricating the lead-out connection assembly, the bonding connection between the support carrier plate 9 and the molding layer 8 is released to form the required core package, such as... Figure 14 As shown. When disconnecting the bonded connection with the support carrier 9, commonly used techniques can be employed, which are generally related to the temporary bonding method used. Specifically, the goal is to separate the support carrier 9 from the molding layer 8, forming a core package after separation.

[0112] Based on the above description, a three-dimensional chip packaging structure integrated on the back of a deep trench device can be obtained, which is prepared using the above packaging process.

[0113] In one embodiment of the present invention, the three-dimensional chip package structure prepared by the packaging process is the final chip package, such as... Figure 14 As shown. The specific details of the resulting chip package can be found in the above description and will not be repeated here. The above packaging process can be a wafer-level process; after the process, a dicing step will yield a single chip package.

[0114] The present invention interconnects the chip 5 in the chip group with the main chip 10, and integrates deep trench devices on the back of the main chip 10. The deep trench devices include deep trench capacitors 21 or deep trench inductors 22, thus forming a chip package, improving system integration and reducing the size of the package.

[0115] Integrating deep-slot capacitors 21 and / or deep-slot inductors 22 on the back of the main chip 10 eliminates the need for externally mounted capacitors / inductors compared to existing technologies, reducing the overall package size and facilitating system integration while ensuring a significant improvement in system performance. Furthermore, compared to traditional surface-mount capacitors and inductors, integrating deep-slot capacitors 21 and deep-slot inductors on the back of the main chip 10 allows for large-area integration of deep-slot capacitors and inductors, improving integration density and reliability, while avoiding crowded space on the front side, further enabling a significant increase in capacitance and inductance values.

[0116] Furthermore, the deep trench capacitor 21 and deep trench inductor 22 are adapted to electrical connections with the device component area 2 and / or core 5, allowing the device component area 2 and / or core 5 to be electrically connected closer, thereby improving the device performance.

[0117] For traditional SIP (System In Package) packaging, the chip 5 and the main chip 10 are interconnected by direct soldering bonding, which reduces the transmission path of high-frequency signals and is suitable for high-frequency applications; it can effectively expand the application scenarios of the chip package.

Claims

1. A process for a three-dimensional core particle package of back-integrated deep-trench devices, characterized by, include: A chip packaging substrate is provided, wherein the chip packaging substrate includes a main chip and a chip assembly molded on the front side of the main chip, the chip assembly including at least one chip, and the chip in the chip assembly being interconnected with the main chip; For the above-mentioned chip packaging substrate, a deep trench device integration process is performed on the back side of the main chip to integrate the required deep trench devices on the back side of the main chip. The deep trench devices include deep trench capacitors and / or deep trench inductors, and the deep trench devices are electrically connected to the corresponding chip adapters in the main chip and / or chip group. After the deep trench device is integrated, a lead-out connection component is fabricated on the back side of the main chip. The chip package formed by the main chip, chip assembly, and deep trench device adapter electrical connection is led out from the back side of the main chip using the fabricated lead-out connection component. When performing deep trench device integration on the chip packaging substrate, the chip packaging substrate is first temporarily bonded to a support carrier. After the temporary bonding, the molding layer in the chip packaging substrate for molding the chip assembly is in contact with the support carrier. After the lead-out connection assembly is fabricated, the bonding connection between the support carrier and the molding layer is released to form the required core package. The lead-out connection assembly includes a back metal layer fabricated on the back side of the main chip and a set of solder balls adapted to the back metal layer, wherein... The back metal layer includes a back first pad and a back second pad. The back first pad is connected to the on-chip interconnect post in the main chip. The deep trench device is electrically connected to the main chip and the corresponding chip adapter in the chip group through the back first pad and the on-chip interconnect post electrically connected to the back first pad. The solder ball group includes a plurality of first solder balls and a plurality of second solder balls, wherein the first solder balls are aligned and electrically connected to the first solder pad on the back side, and the second solder balls are aligned and electrically connected to the second solder pad on the back side. The main chip includes several device component areas, among which, The device component area corresponds directly to the front side of the main chip. One chip in the chip group is electrically connected to the corresponding device component area in the main chip. The deep-groove device is electrically connected to the corresponding device component area in the main chip through the on-chip connection post, so that the chip and the main chip are interconnected, and the deep-groove device is electrically connected to the main chip and / or the corresponding chip. The preparation of the chip encapsulation substrate includes: A main chip is provided, and a front metal layer is formed on the front side of the main chip; A chip assembly is provided, wherein the chips in the chip assembly are soldered and bonded to a front metal layer to electrically connect with the corresponding device component area in the main chip using the soldered and bonded front metal layer. A molding process is performed to mold the chips within the chip assembly onto the front side of the main chip to form a chip package substrate.

2. The process for 3D core package of back integration of deep trench device according to claim 1, characterized in that, When integrating deep trench devices on the back side of the main chip, the integration process includes... The required device slots are fabricated on the back side of the main chip, and the device slots extend perpendicularly from the back side of the main chip to the front side of the main chip. A device body is fabricated within the aforementioned device groove, wherein the device body fills the device groove to form the desired deep groove device using the filled device body.

3. The process for 3D chiplet packaging with backside integration of deep trench devices of claim 2, wherein, For deep-groove capacitors within deep-groove devices, the deep-groove capacitors include deep-groove interdigitated capacitors, wherein, The device groove comprises a capacitor groove for forming the deep trench interdigital capacitor, and the device body comprises an interdigital capacitor electrode for forming the deep trench interdigital capacitor. The interdigital capacitor electrode comprises capacitor first electrode bodies and capacitor second electrode bodies which are alternately distributed.

4. The process for 3-D chiplet packaging with backside integration of deep trench devices of claim 2, wherein, The deep trench inductor in the deep trench device is in a spiral shape, wherein, The device groove comprises an inductor groove for forming the deep trench inductor, and the inductor groove is in a spiral shape in the main chip. The device body comprises an inductor column for forming the deep trench inductor, and the shape of the inductor column is consistent with the shape of the inductor groove in the main chip.

5. The process of claim 1, wherein the backside integration of 3D die package for deep trench device is characterized by When the back metal layer is prepared, the back of the main chip is thinned first so that the end of the in-chip connecting column in the main chip is exposed from the back of the main chip. After the thinning, the required back metal layer is prepared on the back of the main chip.

6. A three-dimensional core particle package structure with backside integration of deep-trench devices, characterized in that, The package process is prepared by using the package process of any one of claims 1-5.

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