Electronic device comprising a package with an interconnect structure

Abstract

Embodiments of the present disclosure relate to electronic devices including packages having interconnect structures. A support substrate has a mounting face and a connecting face opposite the mounting face. An electronic chip is mounted to the mounting face and a connector matrix is mounted to the connecting face. The support substrate includes an interconnect structure formed by a pair of conductive interconnect tracks that electrically connect the electronic chip to the connector matrix and circulate differential signals. Two interconnect tracks of the pair of conductive interconnect tracks extend facing each other at different depths of the support substrate. An isolation structure in the support substrate laterally isolates the pair of conductive interconnect tracks. Isolation plates above and below the pair of conductive interconnect tracks provide further isolation.

Description

[0001] Priority

[0002] This application claims priority to French Patent Application No. 2106999 filed on June 29, 2021, the contents of which are incorporated herein in their entirety by reference to the maximum extent legally permissible. TECHNICAL FIELD

[0003] Embodiments of the present description relate to the field of electronic devices comprising a package of integrated electronic chips, and more particularly to electrical interconnections in the package. BACKGROUND

[0004] The package of such an electronic device generally comprises a support substrate forming a package substrate. The support substrate has a first face, called upper face, to which an electronic chip is attached, and a second face, called lower face, opposite the first face, carrying a matrix of connectors intended to be assembled on a printed circuit board.

[0005] The support substrate comprises an interconnection structure for connecting the electronic chip to the connectors of the matrix of connectors.

[0006] The interconnection structure generally comprises electrically conductive tracks configured to circulate electrical signals between the electronic chip and the matrix of connectors.

[0007] In particular, the interconnection structure can comprise at least one pair of electrically conductive tracks, called differential pair, configured to circulate a differential signal.

[0008] In particular, the differential pair serves to reduce or even cancel electronic noise related to the transmission of the signal. To this end, the differential pair can circulate two complementary signals having opposite signs and values.

[0009] As the two complementary signals are inverted, the difference between the two signals of the two tracks is sufficient to cancel the noise superimposed during transmission.

[0010] Traditionally, the differential pair is formed by two mutually parallel coplanar electrically conductive tracks. In order to ensure the integrity of the signal, the two tracks of the pair are spaced apart by a minimum width to comply with impedance matching conditions.

[0011] The interconnection structure can comprise a plurality of mutually parallel coplanar differential pairs.

[0012] In this way, the interconnection structure occupies a space in the plane of the differential pairs over a distance that depends on the width of the interconnection tracks of the individual differential pairs, the distance between the interconnection tracks of the same differential pair, and the distance between the various differential pairs. Thus, the more the number of differential pairs, the greater the space occupied by the interconnection structure in the support substrate.

[0013] Moreover, it is important to reduce or even eliminate the dissonance between the signals flowing in the different differential pairs, commonly referred to as "crosstalk". This is because such crosstalk can cause interference and can lead to signal loss.

[0014] To reduce or even eliminate the crosstalk between the differential pairs, conductive tracks, referred to as isolation tracks, can be added, which are connected to a reference point, in particular to ground, to isolate the differential pairs.

[0015] These isolation tracks are located between the differential pairs and are coplanar with the latter. In this way, these isolation tracks further increase the size of the interconnection structure.

[0016] However, the size of the support substrate limits the available space for the interconnection structure. Therefore, the more the number of differential pairs the interconnection structure has, the more space the support substrate needs laterally, i.e. in the plane of the interconnection tracks of the differential pairs.

[0017] To reduce the lateral space requirement of the interconnection structure, two conventional solutions can be envisaged.

[0018] The first solution consists in reducing the number of differential pairs. The drawback of this solution is that the number of differential signals that can be transmitted between the electronic chip and the connector matrix is also reduced.

[0019] The second solution consists in reducing the width of the isolation tracks between the differential pairs and / or the distance between the interconnection tracks of the differential pairs and the isolation tracks. However, such a solution has the drawback of increasing the crosstalk between the differential pairs.

[0020] Therefore, there is a need to propose a solution to reduce the lateral space requirement of the differential pairs, in particular when multiple pairs are combined together, while guaranteeing the integrity of each pair of differential signals. SUMMARY

[0021] According to one aspect, an electronic device comprising an electronic chip and a package is proposed.

[0022] The package comprises a connector matrix and a support substrate having a mounting face and a connection face opposite the mounting face.

[0023] The electronic chip is mounted to the mounting face and the connector matrix is mounted to the connection face.

[0024] The support substrate comprises an interconnection structure comprising pairs of conductive interconnection tracks, referred to as differential pairs, connecting the electronic chip to the connector matrix, the pairs of interconnection tracks being configured to circulate differential signals.

[0025] The pair of interconnection tracks comprises two interconnection tracks extending opposite each other at different depths of the substrate, while being separated from each other by a dielectric layer of the substrate.

[0026] Therefore, the distance that this differential pair extends across in width is equal to the width of its interconnecting tracks. Thus, compared to a differential pair with coplanar interconnecting tracks, this differential pair occupies a finite space in width, and the distance it extends across in width is equal to the sum of the width of its interconnecting tracks and the distance between the two tracks.

[0027] Therefore, compared to interconnect structures with coplanar interconnect track pairs, this differential pair can limit the lateral dimensions of the interconnect structure in the supporting substrate.

[0028] This allows for an increase in the number of differential pairs in the interconnect structure without compromising its performance in transmitting differential signals.

[0029] Specifically, the dielectric layer of the substrate between the two interconnect traces has sufficient thickness to ensure the integrity of the differential signal in the differential pair.

[0030] According to one embodiment, the substrate further includes a structure for isolating electromagnetic fields, the structure being configured to be electrically connected to an electrical reference point.

[0031] The isolation structure includes at least two pairs of conductive rails, called isolation rails, which are configured to be electrically connected to a reference point.

[0032] Each pair of isolation tracks comprises two isolation tracks that extend relative to each other at different depths of the substrate and are separated from each other by the dielectric layer.

[0033] The pair of interconnected tracks are located between the two pairs of isolated tracks and are parallel to the latter.

[0034] Therefore, the isolation structure can limit crosstalk between signals of each differential pair, thereby ensuring the integrity of the differential signal.

[0035] In particular, at least two pairs of isolation tracks are located on each side of at least one pair of interconnecting tracks, so that crosstalk caused by signals from sources located on both sides of the differential pair can be limited.

[0036] Furthermore, the two isolation tracks of each pair are located at two different depths of the substrate, thereby limiting crosstalk caused by signals from sources located at these two depths.

[0037] Furthermore, the constant lateral spacing allows crosstalk to be continuously limited along the interconnect tracks of each differential pair.

[0038] Preferably, the interconnect structure comprises multiple pairs of parallel interconnect tracks. Each pair of interconnect tracks is then located between and parallel to two pairs of isolation tracks.

[0039] Therefore, the interconnect structure allows many different differential signals to be transmitted in parallel because there are many differential pairs integrated in the structure.

[0040] Furthermore, the isolation structure is optimized to include a minimum number of pairs of isolation tracks, so that the required space can be limited and the differential pairs are protected from crosstalk.

[0041] According to an embodiment, the isolation structure comprises conductive vias through the dielectric layer electrically connecting the two conductive tracks of each pair of isolation tracks.

[0042] The vias are regularly arranged along the isolation tracks.

[0043] Thus, the vias of the isolation structure can form a vertical isolation wall to limit crosstalk due to signals from sources located on the side of each differential pair.

[0044] According to an embodiment, the isolation structure comprises a first plate configured to be electrically connected to the reference point.

[0045] The first plate extends parallel to the dielectric layer, the first plate being located on the same side as the substrate mounting face opposite the interconnection structure and outside the dielectric layer.

[0046] Thus, the first plate of the isolation structure can form a first horizontal isolation wall, located on the same side as the substrate mounting face, for limiting crosstalk due to signals from sources located above the first plate on the same side as the mounting face.

[0047] According to an embodiment, the isolation structure comprises a second plate configured to be electrically connected to the reference point.

[0048] The second plate extends parallel to the dielectric layer, the second plate being located on the same side as the substrate connection face facing the interconnection structure and outside the dielectric layer.

[0049] Thus, the second plate of the isolation structure can form a second horizontal isolation wall, located on the same side as the substrate connection face, for limiting crosstalk due to signals from sources located below the second plate on the same side as the connection face.

[0050] According to an embodiment, said dielectric layer of the substrate has a thickness between 25 micrometers and 840 micrometers. BRIEF DESCRIPTION OF DRAWINGS

[0051] Other advantages and features will appear from the detailed description of embodiments, which are in no way limiting, and from the study of the attached drawings, on which:

[0052] Figure 1 a cross-sectional view of an electronic device is schematically illustrated;

[0053] Figure 2 a perspective view of a differential pair is schematically illustrated;

[0054] Figure 3a cross-sectional view of the substrate is schematically shown; Figure 1 a cross-sectional view of the substrate is schematically shown;

[0055] Figure 4 a perspective view of the differential pair and the board in the first position is schematically shown;

[0056] Figure 5 a perspective view of the differential pair and the board in the second position is schematically shown; and

[0057] Figure 6 a perspective view of the differential pair and the board is schematically shown. DETAILED DESCRIPTION

[0058] Figure 1 a cross-sectional view of an electronic device DIS comprising an electronic integrated circuit chip PE integrated in a package BT is schematically shown.

[0059] The package BT comprises a support substrate SS having a mounting face FM opposite a connection face FC and a connector matrix MC.

[0060] The connector matrix MC is configured to be assembled with a printed circuit board. The connector matrix MC is for example a solder bead matrix.

[0061] The electronic chip PE is mounted on the mounting face FM of the substrate SS and the connector matrix MC is mounted on the connection face FC of the support substrate SS.

[0062] The package BT can further comprise a package cover (not shown) attached to the mounting face FM of the substrate to protect the electronic chip PE.

[0063] The support substrate SS comprises an interconnection structure ST_IT configured to electrically connect the electronic chip PC to the connector matrix MC.

[0064] The interconnection structure ST_IT is integrated in a stack of layers forming the support substrate SS.

[0065] In particular, the substrate SS comprises a dielectric layer CO, a first layer of pre- impregnated material PP1, a second layer of pre-impregnated material PP2, a lower layer CI and an upper layer CS.

[0066] Pre-impregnated material, commonly referred to as “PREimPREGnated” or more commonly as “PREPREG”.

[0067] The dielectric layer CO is for example a central layer formed of an insulating resin and provides rigidity to the substrate.

[0068] Alternatively, if the substrate does not specifically comprise a layer ensuring the rigidity of the substrate, the dielectric layer CO can comprise an insulating microfilm of the pre-impregnated material or "ABF" type (acronym of the designated product "Ajinomoto Build-up Film" from the company Ajinomoto) for example.

[0069] The dielectric layer CO has a thickness H CO.

[0070] The lower layer CI and the upper layer CS are insulating layers made of an insulating resin such as a pre-impregnated material, an insulating microfilm of the "ABF" type, or in the applicable case a resin similar to the resin of the central layer of the substrate.

[0071] The interconnection structure ST IT comprises differential pairs IT_2, IT_n. Each differential pair is configured to circulate a differential signal between the electronic chip PE and the connector matrix MC.

[0072] Each differential pair comprises two conductive tracks PP_IT_2, PN_IT_2, PP_IT_n, PN_IT_n, for example of metal, hereinafter referred to as "interconnection tracks".

[0073] The interconnection tracks are inserted between the insulating layers forming the substrate.

[0074] Each differential pair first comprises a first interconnection track PP_IT_2, PP_IT_n configured to circulate a first signal, for example of positive polarity, and secondly a second interconnection track PN_IT_2, PN_IT_n configured to circulate a second signal, for example of negative polarity.

[0075] The first signal and the second signal are differential signals.

[0076] For each differential pair, the first interconnection track is first connected to the electronic chip PE by a first via V1_IT_2, V1_IT_n and secondly to the connector matrix MC by a second via V2_IT_2, V2_IT_n.

[0077] Likewise, the second interconnection track is first connected to the electronic chip by a third via V3_IT_2, V3_IT_n and secondly to the connector matrix by a fourth via V4_IT_2, V4_IT_n.

[0078] Within each differential pair, the two interconnection tracks and their respective vias establish two electrical connection paths between the electronic chip PE and the connector matrix MC.

[0079] These two electrical connection paths between the electronic chip PE and the connector matrix MC are configured to have vias heights and interconnection tracks lengths that mutually compensate so that the two connection paths have an overall equal impedance and length.

[0080] Thus, the differential pair as described above can optimize the impedance matching.

[0081] The cross-sectional view of the present example shows only two differential pairs IT_2, IT_n. However, naturally, the substrate can comprise any number "n" of differential pairs, as the index "_n" in reference to "IT_n" implies.

[0082] Figure 2 A perspective view of a differential pair IT_2 in an interconnect structure ST_IT described in relation to Figure 1 a substrate SS is schematically shown.

[0083] In the differential pair IT_2, a first interconnect track PP_IT_2 is disposed on an upper surface of the dielectric layer CO, and a second interconnect track PN_IT_2 is disposed on a lower surface of the dielectric layer CO.

[0084] Each interconnect track PP_IT_2, PN_IT_2 is supported by one of the faces of the dielectric layer CO.

[0085] The two interconnect tracks PP_IT_2, PN_IT_2 of the differential pair IT_2 are vertically stacked in the thickness of the substrate, while being separated by the dielectric layer CO.

[0086] The two interconnect tracks PP_IT_2, PN_IT_2 of the differential pair IT_2 extend parallel to each other, while being separated by the thickness H_CO.

[0087] The thickness H_CO is chosen to optimize the impedance matching between the two interconnect tracks.

[0088] Advantageously, the thickness H_CO of the dielectric layer CO is between 25 micrometers and 840 micrometers, which are regular dimensions for a substrate dielectric layer.

[0089] A thickness between 25 micrometers and 840 micrometers allows an optimal impedance matching in the differential pair IT_2 for differential signal frequencies between one hundred megahertz and several hundred gigahertz.

[0090] The first interconnect track PP_IT_2 is disposed between the first layer of pre-impregnated material PP1 and the upper surface of the dielectric layer CO.

[0091] The second interconnect track PN_IT_2 is disposed between the second layer of pre-impregnated material PP2 and the lower surface of the dielectric layer CO.

[0092] Furthermore, the interconnect structure ST_IT is associated with a structure ST_IS for isolating electromagnetic fields, also referred to as electromagnetic shielding.

[0093] The isolation structure ST IS is configured for electromagnetically isolating the differential pair IT 2 from electromagnetic interferences, for example from other adjacent differential pairs, and more generally from surrounding electromagnetic sources.

[0094] For this purpose, the isolation structure ST IS is configured to be electrically connected to an electrical reference point, in particular to ground.

[0095] The reference point is typically at a mid voltage with respect to the voltage of the differential signals.

[0096] The isolation structure ST IS comprises at least two pairs of electrically conductive tracks PS IS 1, PI IS 1, PS IS 3, PI IS 3, hereinafter referred to as isolation tracks, for electrically connecting the reference point.

[0097] The isolation structure ST IS is formed such that the two pairs of isolation tracks are located on either side of the pair of interconnection tracks IT 2.

[0098] In particular, the two pairs of isolation tracks PS IS 1, PI IS 1, PS IS 3, PI IS 3 are spaced apart from the pair of interconnection tracks PP IT 2, PN IT 2 by a constant lateral distance DL. The isolation tracks and the interconnection tracks are parallel to each other.

[0099] Like the pair of interconnection tracks, each pair of isolation tracks comprises two isolation tracks, comprising an upper isolation track PS IS 1, PS IS 3 located on the upper surface of the dielectric layer CO and a lower isolation track PI IS 1, PI IS 3 located on the lower surface of the dielectric layer CO.

[0100] In each pair, the upper isolation track PS IS 1, PS IS 3 and the lower isolation track PI IS 1, PI IS 3 extend at least partially facing each other at different depths of the substrate.

[0101] The first interconnection track PP IT 2 and the upper isolation tracks PS IS 1, PS IS 3 are coplanar, they are supported by the upper surface of the dielectric layer CO.

[0102] Likewise, the second interconnection track PN IT 2 and the lower isolation tracks PI IS 1, PI IS 3 are also coplanar, they are supported by the lower surface of the dielectric layer CO.

[0103] In each pair, the isolation structure ST IS further comprises an electrically conductive via V IS 1, V IS 3 electrically connecting the upper isolation track PS IS 1, PS IS 3 and the lower isolation track PI IS 1, PI IS 3 through the dielectric layer.

[0104] The conductive vias V_IS_1, V_IS_3 are regularly arranged along the isolation tracks, in one arrangement configured for concentrating the electromagnetic field lines flowing between the two isolation tracks of each pair.

[0105] Figure 3 The elements described with respect to Figure 1 A cross-sectional view on a plane perpendicular to the cut plane of the substrate SS is schematically illustrated. Figure 1

[0106] The interconnect structure ST_IT comprises three pairs of interconnect tracks IT_2, IT_4, IT_6 and the isolation structure ST_IS comprises four pairs of isolation tracks IS_1, IS_3, IS_5, IS_7.

[0107] The pairs of interconnect tracks are arranged alternately with the pairs of isolation tracks, such that each pair of interconnect tracks is located between two pairs of isolation tracks.

[0108] The isolation structure ST_IS is configured for electromagnetically isolating the different pairs from each other.

[0109] Furthermore, the isolation structure ST_IS serves for isolating the interconnect structure ST_IT from surrounding electromagnetic sources.

[0110] Advantageously, each pair of isolation tracks comprises vias V_IS_1, V_IS_3, V_IS_5, V_IS_7 connecting the upper and lower isolation tracks to form a vertical isolation wall between each differential pair.

[0111] Each differential pair of the interconnect structure ST_IT is arranged vertically to have an optimized lateral space requirement, which is of the order of the width of a single interconnect track.

[0112] Thus, the alternating lateral space requirement of the pairs of interconnect tracks and pairs of isolation tracks in the substrate SS advantageously reduces compared to an interconnect structure having coplanar pairs of interconnect tracks.

[0113] Figure 4 The elements described with respect to Figure 2 are schematically illustrated and further comprise a perspective view of a first plate PL1_IS added to the isolation structure ST_IS.

[0114] The first plate PL1_IS is above the upper surface of the dielectric layer CO and on the same side as the mounting face of the substrate.

[0115] The first plate PL1_IS is configured to be electrically connected to the reference point.

[0116] The first plate PL1_IS extends parallel to the dielectric layer CO.

[0117] ​The first plate PL1 IS extends relative to the interconnect structure, in particular, the first plate PL1 IS extends laterally from the first pair of isolation tracks until the last pair of isolation tracks.

[0118] Figure 5 A perspective view of a third embodiment of an isolation structure is schematically shown, the isolation structure comprising a first plate PL1 and a second plate PL2 as described with respect to Figure 2 A perspective view of a third embodiment of an isolation structure is schematically shown, the isolation structure comprising a first plate PL1 and a second plate PL2 as described with respect to

[0119] The second plate PL2 IS is located below the lower surface of the dielectric layer CO and on the same side as the connection face of the substrate.

[0120] The second plate PL2 IS is configured to be electrically connected to the reference point.

[0121] The second plate PL2 IS extends parallel to the dielectric layer CO.

[0122] The second plate PL2 IS extends relative to the interconnect structure, in particular, the second plate PL2 IS extends laterally from the first pair of isolation tracks until the last pair of isolation tracks.

[0123] Figure 6 A perspective view of a third embodiment of an isolation structure is schematically shown, the isolation structure comprising a first plate PL1 and a second plate PL2 as described with respect to Figure 4 A perspective view of a third embodiment of an isolation structure is schematically shown, the isolation structure comprising a first plate PL1 and a second plate PL2 as described with respect to Figure 5 A perspective view of a third embodiment of an isolation structure is schematically shown, the isolation structure comprising a first plate PL1 and a second plate PL2 as described with respect to

[0124] The first plate PL1 IS is parallel to the second plate PL2 IS. The spatial extension of the first plate PL1 IS and the second plate PL2 IS is substantially symmetrical with respect to the dielectric layer CO.

Claims

1. An electronic device, comprising: A support substrate has a mounting surface and a connection surface opposite to the mounting surface; An electronic integrated circuit chip is mounted onto the mounting surface; and A connector matrix is ​​mounted to the connection surface; The supporting substrate includes: An interconnect structure includes a pair of conductive interconnect tracks connecting the electronic integrated circuit chip to the connector matrix, wherein the pair of conductive interconnect tracks are configured for cyclic differential signals, and wherein the pair of conductive interconnect tracks comprises two conductive interconnect tracks extending parallel to the mounting surface and the connection surface and facing each other at different depths on the support substrate, while the two conductive interconnect tracks are separated from each other by a dielectric layer of the support substrate; and An isolation structure for isolating electromagnetic fields is configured to be electrically connected to an electrical reference point. The structure includes at least two pairs of conductive isolation rails configured to be electrically connected to the reference point. Each pair of conductive isolation rails includes two isolation rails extending parallel to the mounting surface and the connection surface, facing each other at different depths on the substrate, while the two isolation rails are separated from each other by the dielectric layer. The pair of conductive interconnect tracks are located between the at least two pairs of conductive isolation tracks and extend parallel to the at least two pairs of conductive isolation tracks.

2. The device of claim 1, wherein two conductive isolation tracks of each pair of conductive isolation tracks are coplanar with a corresponding conductive interconnect track of the two conductive interconnect tracks of the pair of conductive interconnect tracks.

3. The device of claim 1, wherein the isolation structure further comprises a plurality of conductive vias, the plurality of conductive vias passing through the dielectric layer and electrically connecting the two conductive isolation tracks of each pair of conductive isolation tracks.

4. The device of claim 3, wherein the plurality of vias are regularly arranged along a pair of conductive isolation tracks and extend through the dielectric layer of the support substrate.

5. The device of claim 1, wherein the isolation structure further comprises a plate configured to be electrically connected to the reference point, the plate extending parallel to the dielectric layer and supported by the support substrate.

6. The device of claim 5, wherein the board is located between the interconnect structure and the mounting surface of the supporting substrate.

7. The device of claim 5, wherein the plate is located between the interconnect structure and the connection surface of the supporting substrate.

8. The device of claim 1, wherein the isolation structure further comprises: A first plate is configured to be electrically connected to the reference point, the first plate extending parallel to the dielectric layer and supported by the support substrate at a location between the interconnect structure and the mounting surface of the support substrate; and A second plate is configured to be electrically connected to the reference point, the second plate extending parallel to the dielectric layer and supported by the support substrate at a location between the interconnect structure and the connection surface of the substrate.

9. The device of claim 1, wherein the dielectric layer of the supporting substrate has a thickness between 40 micrometers and 200 micrometers.

10. The device of claim 1, wherein each pair of conductive isolation tracks is spaced apart from an adjacent pair of conductive interconnect tracks by a constant lateral distance.

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