Semiconductor device and manufacturing method thereof

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, which relate to the field of semiconductor technology and are used to reduce the manufacturing difficulty of the semiconductor device when the absolute values ​​of the threshold voltages of at least two transistors included in the semiconductor device are different. The semiconductor device includes: a semiconductor substrate, a first ring-gate transistor and a second ring-gate transistor. Along the width direction parallel to the first gate stack structure included in the first ring-gate transistor, the first channel region included in the first ring-gate transistor has at least two columns of first channel portions spaced apart. Along the width direction parallel to the second gate stack structure included in the second ring-gate transistor, the second channel region included in the second ring-gate transistor has at least two columns of second channel portions spaced apart. The spacing between two adjacent columns of second channel portions is different from the spacing between two adjacent columns of first channel portions. The width of at least one column of second channel portions in the second channel region is different from the width of at least one column of first channel portions in the first channel region.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In actual applications, a semiconductor device includes multiple transistors that often have different divisions of labor. When the divisions of labor of different transistors are different, the absolute values ​​of the threshold voltages of different transistors may be different.

[0003] However, when the absolute values ​​of the threshold voltages of at least two transistors included in the semiconductor device are different, it is difficult to manufacture the semiconductor device using existing manufacturing methods, resulting in a low yield of the semiconductor device. Summary of the Invention

[0004] An object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which are used to reduce the manufacturing difficulty of the semiconductor device and improve the yield of the semiconductor device when the absolute values ​​of the threshold voltages of at least two transistors included in the semiconductor device are different.

[0005] In order to achieve the above-mentioned objective, the present invention provides a semiconductor device, which includes: a semiconductor substrate, a first all-around gate transistor and a second all-around gate transistor.

[0006] Along a direction parallel to the surface of the semiconductor substrate, the semiconductor substrate includes a first region and a second region. The first ring-gate transistor is formed on the first region. Along a width direction parallel to the first gate stack structure included in the first ring-gate transistor, the first channel region included in the first ring-gate transistor has at least two columns of first channel portions spaced apart. The second ring-gate transistor is formed on the second region. Along a width direction parallel to the second gate stack structure included in the second ring-gate transistor, the second channel region included in the second ring-gate transistor has at least two columns of second channel portions spaced apart. The spacing between two adjacent columns of second channel portions is different from the spacing between two adjacent columns of first channel portions. The width of at least one column of second channel portions in the second channel region is different from the width of at least one column of first channel portions in the first channel region.

[0007] Compared to the prior art, in the semiconductor device provided by the present invention, the first channel region included in the first gate-all-around transistor has at least two rows of first channel portions spaced apart. The second channel region included in the second gate-all-around transistor has at least two rows of second channel portions spaced apart. Furthermore, the spacing between two adjacent rows of second channel portions is different from the spacing between two adjacent rows of first channel portions. Based on this, taking the example of the spacing between two adjacent rows of first transistors being smaller than the spacing between two adjacent rows of second channel portions as an example, in the process of manufacturing the semiconductor device provided by the present invention, if a first gate stack structure and a second gate stack structure are formed simultaneously, and a gate material having a thickness equal to the thickness of the second gate included in the second gate stack structure is formed on both the first gate dielectric layer included in the first gate stack structure and the second gate dielectric layer included in the second gate stack structure, then because the spacing between the two adjacent rows of second channel portions matches the specifications of the second gate stack structure, a second gate of a corresponding thickness can be formed normally on the second gate dielectric layer. However, because the spacing between the two adjacent rows of first channel portions is smaller, the thickness of the portion of the first gate filling between the adjacent first channel portions is smaller. Alternatively, when the first gate dielectric layer completely fills the gap between adjacent first channel portions, the first gate cannot be filled between adjacent first channel portions, so that the filling thicknesses of the first gate and the second gate at the corresponding gaps are different, which helps to make the absolute values ​​of the threshold voltages of the first ring-gate transistor and the second ring-gate transistor different.

[0008] In addition, when the spacing between two adjacent columns of second channel portions is different from the spacing between two adjacent columns of first channel portions, the width of at least one column of second channel portions in the second channel region is different from the width of at least one column of first channel portions in the first channel region, which is conducive to making the width of the first channel region and the width of the second channel region approximately the same, so that the width of the first fin structure used to manufacture the first channel region and the width of the second fin structure used to manufacture the second channel region are approximately the same, which is conducive to reducing the difficulty of forming the first fin structure and the second fin structure on the same semiconductor substrate through technologies such as self-aligned double imaging. At the same time, it can be seen from the above content that during the manufacturing process of the semiconductor device provided by the present invention, there is no need to adopt the more cumbersome operation process of multiple "deposition-etching-deposition" methods to form the first gate stack structure and the second gate stack structure, nor is there a need to adopt the dipole threshold control technology with a high degree of process complexity to form a dipole pair at the corresponding interface. Only by the width difference between the corresponding first channel portion and the corresponding second channel portion, and the difference between the interval between the two adjacent first channel portions and the interval between the two adjacent second channel portions, the absolute values ​​of the threshold voltages of the first ring-gate transistor and the second ring-gate transistor can be made different, thereby reducing the manufacturing difficulty of the semiconductor device and improving the yield of the semiconductor device.

[0009] The present invention provides a method for manufacturing a semiconductor device, the method comprising:

[0010] A semiconductor substrate is provided. Along a direction parallel to a surface of the semiconductor substrate, the semiconductor substrate includes a first region and a second region.

[0011] A first gate-all-around transistor is formed on the first region, and a second gate-all-around transistor is formed on the second region. Along a width direction parallel to the first gate stack structure included in the first gate-all-around transistor, the first channel region included in the first gate-all-around transistor has at least two columns of first channel portions spaced apart. Along a width direction parallel to the second gate stack structure included in the second gate-all-around transistor, the second channel region included in the second gate-all-around transistor has at least two columns of second channel portions spaced apart. The spacing between two adjacent columns of second channel portions is different from the spacing between two adjacent columns of first channel portions. The width of at least one column of second channel portions in the second channel region is different from the width of at least one column of first channel portions in the first channel region.

[0012] Compared with the prior art, the beneficial effects of the method for manufacturing a semiconductor device provided by the present invention can be referred to the beneficial effects of the semiconductor device described above and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0014] Figure 1 Parts (1) and (2) are two schematic diagrams of structures after alternately stacking sacrificial material layers and channel material layers on a semiconductor substrate in an embodiment of the present invention;

[0015] Figure 2 Schematic diagram of a longitudinal section of a structure after alternately stacking sacrificial material layers and channel material layers on a semiconductor substrate in an embodiment of the present invention;

[0016] Figure 3 This is a schematic longitudinal cross-sectional view of the structure after grooves of different widths are formed in the first region and the second region in an embodiment of the present invention;

[0017] Figure 4 Schematic diagram of a longitudinal cross-section of the structure after forming an isolation material covering the semiconductor substrate and the trench in an embodiment of the present invention;

[0018] Figure 5 This is a schematic longitudinal cross-sectional view of the structure after isolation layers of different widths are formed on the first region and the second region in an embodiment of the present invention;

[0019] Figure 6 is a schematic longitudinal cross-sectional view of a structure after a second patterning process is performed on alternately stacked sacrificial material layers and channel material layers, and a semiconductor substrate in an embodiment of the present invention;

[0020] Figure 7 is a schematic longitudinal cross-sectional view of another structure after a second patterning process is performed on the alternately stacked sacrificial material layers and channel material layers and the semiconductor substrate in an embodiment of the present invention;

[0021] Figure 8 Schematic diagram of the structure after the shallow trench isolation structure is formed in an embodiment of the present invention;

[0022] Figure 9 Schematic diagram of a longitudinal section of a structure after a shallow trench isolation structure is formed in an embodiment of the present invention;

[0023] Figure 10 A schematic diagram of the structure after forming a sacrificial gate in an embodiment of the present invention;

[0024] Figure 11 Schematic diagram of the structure after the gate sidewall is formed in an embodiment of the present invention;

[0025] Figure 12 Schematic diagram of the structure after removing portions of the first fin structure, the second fin structure, and the third fin structure located in the source formation region and the drain formation region in an embodiment of the present invention;

[0026] Figure 13 This is a schematic diagram of a first structure after forming the first inner side wall and the second inner side wall in an embodiment of the present invention;

[0027] Figure 14 This is a schematic diagram of a second structure after the first inner side wall and the second inner side wall are formed in an embodiment of the present invention;

[0028] Figure 15 This is a schematic diagram of a third structure after the first inner side wall and the second inner side wall are formed in an embodiment of the present invention;

[0029] Figure 16 Schematic diagram of the structure after forming the first source region, the first drain region, the second source region, the second drain region, the third source region and the third drain region in an embodiment of the present invention;

[0030] Figure 17 is a schematic longitudinal cross-sectional view of the structure after the dielectric layer is formed in an embodiment of the present invention;

[0031] Figure 18 This is a schematic longitudinal cross-sectional view of the structure after the sacrificial gate is removed according to an embodiment of the present invention;

[0032] Figure 19 1 is a schematic longitudinal cross-sectional view of a first structure after forming a first channel region, a second channel region, and a third channel region in an embodiment of the present invention;

[0033] Figure 201 is a schematic longitudinal cross-sectional view of a second structure after forming a first channel region, a second channel region, and a third channel region in an embodiment of the present invention;

[0034] Figure 21 is a schematic longitudinal cross-sectional view of the structure after forming the first transistor, the second transistor, and the third transistor in an embodiment of the present invention;

[0035] Figure 22 A schematic diagram of a method for manufacturing a semiconductor device provided by an embodiment of the present invention.

[0036] Reference numerals: 11 is a semiconductor substrate, 111 is a first region, 112 is a second region, 113 is a third region, 12 is a sacrificial material layer, 121 is a sacrificial layer, 13 is a channel material layer, 131 is a channel layer, 14 is a trench, 15 is an isolation material, 151 is an isolation layer, 16 is a first fin structure, 17 is a second fin structure, 18 is a third fin structure, 19 is a shallow trench isolation structure, 20 is a source formation region, 21 is a drain formation region, 22 is a transition region, 23 is a sacrificial gate, 24 is a gate spacer, 25 is a first inner spacer, 26 is a second inner spacer, 27 is a third inner spacer, 28 is a second inner spacer, 29 is a third inner spacer, 30 is a first inner spacer, 31 is a second inner spacer, 32 is a second inner spacer, 33 is a third inner spacer, 34 is a third inner spacer, 35 is a first inner spacer, 36 is a second inner spacer, 37 is a third inner spacer, 38 is a first inner spacer, 39 is a second inner spacer, 40 is a first inner spacer, 41 is a second inner spacer, 42 is a first inner spacer, 43 is a second inner spacer, 44 is a first inner spacer, 45 is a first inner spacer, 46 is a second inner spacer, 47 is a third inner spacer, 48 is a first inner spacer, 49 is a first inner spacer, 50 is a first inner spacer, 51 is a second inner spacer, 52 is a first inner spacer, 53 is a first inner spacer, 54 is a first inner spacer, 55 is a first inner spacer, 56 is a second inner space 8 is the first source region, 29 is the first drain region, 30 is the second source region, 31 is the second drain region, 32 is the third source region, 33 is the third drain region, 34 is the dielectric layer, 35 is the first channel region, 351 is the first channel portion, 36 is the second channel region, 361 is the second channel portion, 37 is the third channel region, 371 is the third channel portion, 38 is the first gate stack structure, 381 is the first gate dielectric layer, 382 is the first gate, 39 is the second gate stack structure, 391 is the second gate dielectric layer, 392 is the second gate, 40 is the third gate stack structure, 401 is the third gate dielectric layer, and 402 is the third gate. DETAILED DESCRIPTION

[0037] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely illustrative and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

[0038] The accompanying drawings illustrate various schematic diagrams of structures according to embodiments of the present disclosure. These figures are not drawn to scale, and for the purpose of clarity, certain details are exaggerated and certain details may be omitted. The shapes of the various regions and layers shown in the figures, as well as their relative sizes and positional relationships, are merely exemplary and may deviate in practice due to manufacturing tolerances or technical limitations. Those skilled in the art may design regions / layers with different shapes, sizes, and relative positions as needed.

[0039] In the context of this disclosure, when a layer / element is referred to as being "on" another layer / element, the layer / element may be directly on the other layer / element, or there may be an intervening layer / element between them. Furthermore, if a layer / element is "on" another layer / element in one orientation, it may be "below" the other layer / element when the orientation is reversed. To further clarify the technical problems, technical solutions, and beneficial effects to be solved by the present invention, the present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are intended solely to explain the present invention and are not intended to limit the present invention.

[0040] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be understood to indicate or imply relative importance or implicitly specify the number of the technical features indicated. Thus, a feature specified as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, "plurality" means two or more, unless otherwise specifically defined. "Several" means one or more, unless otherwise specifically defined.

[0041] In the description of the present invention, it should be noted that, unless otherwise expressly specified or limited, the terms "mounted," "connected," and "connected" should be understood in a broad sense. For example, they may refer to fixed, detachable, or integral connections; mechanical or electrical connections; direct or indirect connections through an intermediate medium; and may encompass internal communication between two components or interaction between two components. Those skilled in the art will understand the specific meanings of the above terms in the present invention based on specific circumstances.

[0042] In the actual manufacturing process of semiconductor devices, multiple "deposition-etching-deposition" methods are usually used to form a gate stack structure with different overall thickness and / or different materials on the channels included in different transistors in the semiconductor device, so that different transistors correspond to different threshold control parameters, thereby realizing the control of the threshold voltage of different transistors in the semiconductor device. With the development of semiconductor technology, integrated circuits with higher performance and stronger functions require greater component density, and the size, size and space between each component, or each component itself also need to be further reduced. For ring-gate transistors, the space between two adjacent layers of nanowires or sheets in the channel and between the nanowires or sheets and the semiconductor substrate is relatively small. It is difficult to form a gate stack structure with different overall thickness and / or different materials in a smaller space, resulting in reduced yield and performance of semiconductor devices.

[0043] In response to the above technical problems, those skilled in the art have developed two other technologies for achieving different threshold voltage control for different transistors in semiconductor devices. One of them is to use a dipole threshold control technology that does not take up space. Specifically, after forming the channel and gate dielectric layer of the corresponding ring-gate transistor on different types of regions, a dipole layer of corresponding thickness and corresponding material is formed on each gate dielectric layer, and the key elements in the dipole layer (for example, lanthanum in the lanthanum oxide dipole layer) are pushed to the interface through annealing, so that different types of regions correspond to different threshold control parameters. Finally, the remaining dipole layer is removed, and the threshold voltage control of different ring-gate transistors is achieved without reducing the formation space of the gate. The other is to use technologies such as self-aligned double patterning (SADP), which achieves different threshold control parameters for different types of regions by forming nanowires or sheets with different widths on different types of regions, and the lateral spacing between adjacent nanowires or sheets is different.

[0044] However, the process complexity of the above-mentioned dipole threshold control technology is relatively high, and it is difficult to form channels with nanowires or sheets of different widths and different lateral spacing between adjacent nanowires or sheets through technologies such as SADP. As a result, it is difficult to use existing manufacturing methods to make transistors on different types of areas correspond to different threshold control parameters.

[0045] In order to solve the above technical problems, an embodiment of the present invention provides a semiconductor device. Figures 19 to 21 As shown, the semiconductor device includes: a semiconductor substrate 11, a first all-around gate transistor and a second all-around gate transistor.

[0046] like Figures 19 to 21 As shown, along a direction parallel to the surface of the semiconductor substrate 11, the semiconductor substrate 11 includes a first region 111 and a second region 112. The first gate-all-around transistor is formed on the first region 111. Along a width direction parallel to the first gate stack structure 38 included in the first gate-all-around transistor, the first channel region 35 included in the first gate-all-around transistor has at least two rows of first channel portions 351 spaced apart. The second gate-all-around transistor is formed on the second region 112. Along a width direction parallel to the second gate stack structure 39 included in the second gate-all-around transistor, the second channel region 36 included in the second gate-all-around transistor has at least two rows of second channel portions 361 spaced apart. The spacing between two adjacent rows of second channel portions 361 is different from the spacing between two adjacent rows of first channel portions 351. The width of at least one row of second channel portions 361 in the second channel region 36 is different from the width of at least one row of first channel portions 351 in the first channel region 35.

[0047] Specifically, the specific structure of the above-mentioned semiconductor substrate can be set according to the actual application scenario. For example: the semiconductor substrate can be a silicon substrate, a silicon-germanium substrate, a germanium substrate, a silicon-on-insulator substrate, or other semiconductor substrates on which no other structures are formed. For another example: if the first ring-gate transistor and the second ring-gate transistor included in the semiconductor device provided in the embodiment of the present invention are applied to the second or higher layer of ring-gate transistors included in the integrated circuit, the semiconductor substrate can at least include a semiconductor substrate, a first layer device structure formed on the semiconductor substrate, and a dielectric layer covering the first layer device structure. In this case, the materials of the various parts included in the semiconductor substrate can be set according to actual needs, as long as they can be applied to the semiconductor device provided in the embodiment of the present invention.

[0048] As for the first region and the second region included in the semiconductor substrate, the boundary between the two is a virtual boundary. The first region and the second region can be adjacent or spaced apart. Specifically, the first region is the region where the first ring-gate transistor is formed on the semiconductor substrate. Therefore, the specific position and specifications of the first region on the semiconductor substrate can be determined based on information such as the formation position and specifications of the first ring-gate transistor in the actual application scenario. At the same time, the second region is the region where the second ring-gate transistor is formed on the semiconductor substrate. Therefore, the specific position and specifications of the second region on the semiconductor substrate can be determined based on information such as the formation position and specifications of the second ring-gate transistor in the actual application scenario.

[0049] As for the first and second gate-all-around transistors, in terms of conductivity type, the first and second gate-all-around transistors can be of the same conductivity type. In other words, the first and second gate-all-around transistors can both be N-type transistors or P-type transistors. Alternatively, the first and second gate-all-around transistors can be of different conductivity types. In this case, the first gate-all-around transistor can be an N-type transistor, while the second gate-all-around transistor is a P-type transistor. Alternatively, the first gate-all-around transistor can be a P-type transistor, while the second gate-all-around transistor is an N-type transistor.

[0050] From a structural perspective, the first channel region included in the first ring-gate transistor may have only two columns of first channel portions, or may have at least three columns. The specific number of columns of first channel portions in the first channel region, the specific width of each column of first channel portions, and the spacing between two adjacent columns of first channel portions may be set according to actual needs and are not specifically limited here. Specifically, Figure 19 As shown, the width of each column of the first channel portion 351 included in the first channel region 35 may be the same. Figure 20As shown, the width of at least one first channel portion 351 may be different from the widths of the remaining first channel portions 351 in the first channel region 35. In addition, each column of first channel portions may include only one layer of first nanowires or sheets, or may include at least two layers of first nanowires or sheets. Figure 19 and Figure 20 As shown, each layer of first nanowires or sheets included in the first channel portion 351 has a gap between it and the semiconductor substrate 11. Figure 19 and Figure 20 As shown, when the first channel portion 351 includes at least two layers of first nanowires or sheets, along a thickness direction parallel to the semiconductor substrate 11 , the at least two layers of first nanowires or sheets included in each column of the first channel portion 351 are spaced apart.

[0051] In addition, the first source region and the first drain region of the first gate-all-around transistor may each include at least two active portions connected only to the corresponding first channel portion and spaced apart. Figures 16 to 21 As shown, the first gate-all-around transistor includes a first source region 28 and a first drain region 29. The first channel region 35 is located between the first source region 28 and the first drain region 29, and each column of first channel portions 351 contacts the first source region 28 and the first drain region 29, respectively.

[0052] like Figure 21 As shown, the first gate-all-around transistor includes a first gate stack structure 38 including a first gate dielectric layer 381 surrounding at least the periphery of each first nanowire or sheet, and a first gate 382 formed on the first gate dielectric layer 381. In some cases, the first gate dielectric layer 381 may also be formed between the semiconductor substrate 11 and the first gate 382.

[0053] In terms of materials, the materials of the first channel region, the first source region, and the first drain region can be semiconductor materials such as silicon, silicon-germanium, germanium, or Group III-V compounds. The materials of the first source region and the first drain region can be the same or different. Specifically, when the materials of the first source region and the first drain region are the same, the first source region and the first drain region can be formed simultaneously in a unified operation step, simplifying the manufacturing process of the first ring-gate transistor. In addition, the material of the first channel region can be the same as or different from the materials of the first source region and the first drain region, respectively. The material of the first gate dielectric layer can be an insulating material with a low dielectric constant such as silicon oxide or silicon nitride, or an insulating material with a high dielectric constant such as HfO2, ZrO2, TiO2, or Al2O3. The material of the first gate can be a conductive material such as polysilicon, TiN, TaN, or TiSiN.

[0054] As for the above-mentioned second ring-gate transistor, the second channel region included in the second ring-gate transistor may have only two columns of second channel portions, or at least three columns. The specific number of columns of second channel portions in the second channel region, the specific width of each column of second channel portions, and the spacing between two adjacent columns of second channel portions can be set according to actual needs and are not specifically limited here. Specifically, the number of columns of second channel portions included in the second channel region may be the same as or different from the number of columns of first channel portions included in the first channel region. In addition, if Figure 19 As shown, the width of each column of second channel portions 361 included in the second channel region 36 may be the same. Of course, the width of at least one second channel portion may be different from the width of the remaining second channel portions in the second channel region. Furthermore, each column of second channel portions may include only one layer of second nanowires or sheets, or may include at least two layers of second nanowires or sheets. Figure 19 and Figure 20 As shown, each layer of second nanowires or sheets included in the second channel portion 361 has a gap between it and the semiconductor substrate 11. Figure 19 and Figure 20 As shown, when the second channel portion 361 includes at least two layers of second nanowires or sheets, along a thickness direction parallel to the semiconductor substrate 11 , the at least two layers of second nanowires or sheets included in each column of the second channel portion 361 are spaced apart.

[0055] In addition, the second source region and the second drain region of the second all-around gate transistor may each include at least two active portions connected only to the corresponding second channel portion and spaced apart. Figures 16 to 21 As shown, the second all-around gate transistor includes a second source region 30 and a second drain region 31. The second channel region 36 is located between the second source region 30 and the second drain region 31, and each column of second channel portions 361 contacts the second source region 30 and the second drain region 31, respectively.

[0056] like Figure 21 As shown, the second all-around gate transistor includes a second gate stack structure 39, which may include a second gate dielectric layer 391 surrounding at least the periphery of each layer of second nanowires or sheets, and a second gate 392 formed on the second gate dielectric layer 391. In some cases, the second gate dielectric layer 391 may also be formed between the semiconductor substrate 11 and the second gate 392.

[0057] Specifically, the materials of the various structures included in the second all-around gate transistor can refer to the materials of the various structures included in the first all-around gate transistor described above, and will not be repeated here.

[0058] From the above content, we can see that if Figures 19 to 21As shown, in the semiconductor device provided by an embodiment of the present invention, the first all-around gate transistor includes a first channel region 35 having at least two rows of first channel portions 351 spaced apart. The second all-around gate transistor includes a second channel region 36 having at least two rows of second channel portions 361 spaced apart. Furthermore, the spacing between two adjacent rows of second channel portions 361 is different from the spacing between two adjacent rows of first channel portions 351. In actual applications, the first gate stack structure 38 needs to surround the periphery of each first nanowire or sheet through the gap between each first nanowire or sheet and the adjacent structure, and the second gate stack structure 39 needs to surround the periphery of each second nanowire or sheet through the gap between each second nanowire or sheet and the adjacent structure. In this case, based on the threshold voltage requirements of the first and second all-around gate transistors in actual application scenarios, the larger of the spacing between the two adjacent rows of second channel portions 361 and the spacing between the two adjacent rows of first channel portions 351 can be set based on the thickness of the first gate stack structure 38 or the second gate stack structure 39. At this time, the gate stack structure corresponding to the one with the larger spacing can be normally filled, while the gate stack structure corresponding to the one with the smaller spacing cannot be normally filled between two adjacent columns of channel portions.

[0059] Specifically, such as Figures 19 to 21 As shown, taking the example of a case where the spacing between two adjacent columns of first transistors is smaller than the spacing between two adjacent columns of second channel portions 361, in the process of manufacturing the semiconductor device provided by the embodiment of the present invention, if the first gate stack structure 38 and the second gate stack structure 39 are formed simultaneously, and a gate material having a thickness equal to the thickness of the second gate electrode 392 included in the second gate stack structure 39 is formed on both the first gate dielectric layer 381 included in the first gate stack structure 38 and the second gate dielectric layer 391 included in the second gate stack structure 39, then because the spacing between the two adjacent columns of second channel portions 361 matches the specifications of the second gate stack structure 39, a second gate electrode 392 of a corresponding thickness can be normally formed on the second gate dielectric layer 391. However, because the spacing between the two adjacent columns of first channel portions 351 is smaller, the thickness of the portion of the first gate electrode 382 filling the space between the two adjacent columns of first channel portions 351 is smaller. Alternatively, when the first gate dielectric layer 381 fills the gap between two adjacent columns of first channel portions 351, the first gate 382 cannot be filled between adjacent first channel portions 351, so that the filling thicknesses of the first gate 382 and the second gate 392 at the corresponding gaps are different, which is conducive to making the absolute values ​​of the threshold voltages of the first ring-gate transistor and the second ring-gate transistor different.

[0060] In addition, if Figures 9 to 21As shown, when the spacing between two adjacent columns of second channel portions 361 is different from the spacing between two adjacent columns of first channel portions 351, the width of at least one column of second channel portions 361 in the second channel region 36 is different from the width of at least one column of first channel portions 351 in the first channel region 35, which is conducive to making the width of the first channel region 35 and the width of the second channel region 36 approximately the same, so that the widths of the first fin structure 16 used to manufacture the first channel region 35 and the second fin structure 17 used to manufacture the second channel region 36 are approximately the same, which is conducive to reducing the difficulty of forming the first fin structure 16 and the second fin structure 17 on the same semiconductor substrate 11 through technologies such as self-aligned double imaging. At the same time, it can be seen from the above content that during the manufacturing process of the semiconductor device provided by the embodiment of the present invention, there is no need to adopt the more cumbersome operation process of multiple "deposition-etching-deposition" methods to form the first gate stack structure 38 and the second gate stack structure 39, nor is there any need to adopt the dipole threshold control technology with high process complexity to form a dipole pair at the corresponding interface. Only by the width difference between the corresponding first channel portion 351 and the corresponding second channel portion 361, and the difference between the interval between the two adjacent first channel portions 351 and the interval between the two adjacent second channel portions 361, the absolute values ​​of the threshold voltages of the first ring-gate transistor and the second ring-gate transistor can be made different, thereby reducing the manufacturing difficulty of the semiconductor device and improving the yield of the semiconductor device.

[0061] In actual application, Figures 19 to 21 As shown, the width of the first channel region 35 is equal to the sum of the total width of all first channel portions 351 and the total width of the interval between two adjacent first channel portions 351. Figure 19 and Figure 20 As shown, when the first channel region 35 includes two columns of first channel portions 351, the width of the first channel region 35 is equal to the sum of the total width of the two columns of first channel portions 351 and the width of the interval between the two columns of first channel portions 351. Similarly, the width of the second channel region 36 is equal to the sum of the total width of all second channel portions 361 and the total width of the interval between two adjacent second channel portions 361. Based on this, the width of the first channel region 35 can be the same as the width of the second channel region 36. In this case, when the widths of the first channel region 35 and the second channel region 36 are the same, self-aligned dual imaging and other technologies can be used to simultaneously form the first fin structure 16 and the second fin structure 17 under the mask of the same mask layer, which can further reduce the difficulty of manufacturing the semiconductor device and simplify the manufacturing process of the semiconductor device.

[0062] In one example, Figures 13 to 15As shown, the first all-around gate transistor may further include a first inner sidewall 25. The first inner sidewall 25 is formed between the first gate stack structure 38 and the first source region 28, and between the first gate stack structure 38 and the first drain region 29, so as to isolate at least a portion of the first gate stack structure 38 from the first source region 28 and the first drain region 29, respectively, thereby improving the electrical characteristics of the first all-around gate transistor.

[0063] Among them, such as Figure 13 and Figure 14 As shown, the first inner sidewall 25 may be formed only between the first gate stack structure 38 and a portion of the first source region 28, and between the first gate stack structure 38 and a portion of the first drain region 29. Alternatively, as shown in FIG. Figure 15 As shown, there is a first intermediate area between the first gate stack structure 38 and the first source region 28, and between the first gate stack structure 38 and the first drain region 29. The first inner sidewall 25 can also fill the first intermediate area. Specifically, the specific formation position of the first inner sidewall 25 between the first gate stack structure 38 and the first source region 28, and between the first gate stack structure 38 and the first drain region 29 can be set according to the actual manufacturing process and actual needs. The actual manufacturing process of the first inner sidewall 25 can be referred to below and will not be repeated here. As for the material of the first inner sidewall, it can be an insulating material such as silicon oxide or silicon nitride.

[0064] like Figures 13 to 15 As shown, the second all-around gate transistor may further include a second inner sidewall 26. The second inner sidewall 26 is formed between the second gate stack and the second source region 30, and between the second gate stack structure 39 and the second drain region 31, so as to isolate at least a portion of the second gate stack structure 39 from the second source region 30 and the second drain region 31, respectively, thereby improving the electrical characteristics of the second all-around gate transistor.

[0065] Among them, such as Figure 13 and Figure 14 As shown, the second inner sidewall 26 may be formed only between the second gate stack structure 39 and a portion of the second source region 30, and between the second gate stack structure 39 and a portion of the second drain region 31. Alternatively, as shown in FIG. Figure 15 As shown, there is a second intermediate area between the second gate stack structure 39 and the second source region 30, and between the second gate stack structure 39 and the second drain region 31. The second inner sidewall 26 can also fill the second intermediate area. Specifically, the specific formation position of the second inner sidewall 26 between the second gate stack structure 39 and the second source region 30, and between the second gate stack structure 39 and the second drain region 31 can be set according to the actual manufacturing process and actual needs. The actual manufacturing process of the second inner sidewall 26 can be referred to below and will not be repeated here. As for the material of the second inner sidewall 26, reference can be made to the material of the first inner sidewall.

[0066] In one example, Figures 17 to 21 As shown, the semiconductor device may further include a shallow trench isolation structure 19, a gate sidewall 24 and a dielectric layer 34. The shallow trench isolation structure 19 is formed on the semiconductor substrate 11 to isolate the different active areas of the semiconductor substrate 11 to prevent leakage. The thickness of the shallow trench isolation structure 19 can be set according to actual conditions. The material of the shallow trench isolation structure 19 may be an insulating material such as SiN, Si3N4, SiO2 or SiCO. The gate sidewall 24 is formed at least on both sides of the first gate stack structure 38 and the second gate stack structure 39 along the length direction to at least isolate the first gate stack structure 38 and the second gate stack structure 39 from other conductive structures formed subsequently, thereby improving the electrical stability of the semiconductor device. The material of the gate sidewall 24 may be an insulating material such as silicon oxide or silicon nitride. The dielectric layer 34 covers the semiconductor substrate 11, and its top is flush with the top of the first gate stack structure 38 and the second gate stack structure 39. During the actual manufacturing process, the presence of the dielectric layer 34 can at least protect the first source region 28, the first drain region 29, the second source region 30, and the second drain region 31 from being affected by subsequent operations, further improving the yield of the semiconductor device. The dielectric layer 34 can be made of an insulating material such as silicon oxide or silicon nitride.

[0067] In actual application, since the semiconductor device provided by the embodiment of the present invention is prepared in a process compatible with the manufacturing process of conventional gate-all-around transistors, the first gate-all-around transistor, the second gate-all-around transistor, and the third gate-all-around transistor can be formed simultaneously on the same semiconductor substrate. The third gate-all-around transistor is a conventional gate-all-around transistor. In this case, Figure 21 As shown, the semiconductor substrate 11 also includes a third region 113. The aforementioned third all-around gate transistor is formed on the third region 113. The third all-around gate transistor includes a third channel region 37 having a row of third channel portions 371. The third region can be located between the first and second regions, on the side of the first region facing away from the second region, or on the side of the second region 112 facing away from the first region 111. The specific location and specifications of the third region 113 can be determined based on the actual application scenario and other information about the formation location and specifications of the third all-around gate transistor, and are not specifically limited here.

[0068] like Figures 16 to 21As shown, the third channel portion 371 included in the third all-around gate transistor may include only one layer of third nanowires or sheets, or may include at least two layers of third nanowires or sheets spaced apart along the thickness direction of the semiconductor substrate 11. The third nanowire or sheet located at the bottom layer has a gap with the semiconductor substrate 11. In addition, the third channel portion 371 is located between the third source region 32 and the third drain region 33. The third all-around gate transistor includes a third gate stack structure 40, which includes at least a third gate dielectric layer 401 surrounding the periphery of each layer of third nanowires or sheets, and a third gate 402 formed on the third gate dielectric layer 401. The materials of the various structures included in the third all-around gate transistor can refer to the materials of the various structures included in the first all-around gate transistor described above, and will not be repeated here.

[0069] like Figure 14 and Figure 15 As shown, the third all-around gate transistor may further include a third inner spacer 27. The third inner spacer 27 is formed between the third gate stack structure 40 and the third source region 32, and between the third gate stack structure 40 and the third drain region 33. The beneficial effects and materials of the third inner spacer can refer to the beneficial effects and materials of the first inner spacer 25 described above, respectively.

[0070] like Figure 22 As shown, the embodiment of the present invention provides a method for manufacturing a semiconductor device. Figures 1 to 21 The manufacturing process is described by referring to a cross-sectional view or a perspective view of the operation shown. Specifically, the manufacturing method of the semiconductor device includes:

[0071] First, a semiconductor substrate is provided. Figure 2 As shown, along a direction parallel to the surface of the semiconductor substrate 11, the semiconductor substrate 11 includes a first region 111 and a second region 112. Specific information on the structure and material of the semiconductor substrate 11 can be found in the above text.

[0072] like Figure 21 As shown, a first gate-all-around transistor is formed on the first region 111, and a second gate-all-around transistor is formed on the second region 112. Along a width direction parallel to the first gate stack structure 38 included in the first gate-all-around transistor, the first channel region 35 included in the first gate-all-around transistor has at least two columns of first channel portions 351 spaced apart. Along a width direction parallel to the second gate stack structure 39 included in the second gate-all-around transistor, the second channel region 36 included in the second gate-all-around transistor has at least two columns of second channel portions 361 spaced apart. The spacing between two adjacent columns of second channel portions 361 is different from the spacing between two adjacent columns of first channel portions 351. The width of at least one column of second channel portions 361 in the second channel region 36 is different from the width of at least one column of first channel portions 351 in the first channel region 35.

[0073] Specifically, information such as the structures of the first all-around gate transistor and the second all-around gate transistor, the relative positional relationship of each structure, the specifications of each structure, and the materials of each structure can be referred to above.

[0074] In actual application, the above-mentioned steps of forming the first gate-all-around transistor on the first region and forming the second gate-all-around transistor on the second region may include the following steps:

[0075] like Figure 8 and Figure 9 As shown, a first fin structure 16 is formed on the first region 111, and a second fin structure 17 having the same width as the first fin structure 16 is formed on the second region 112. Both the first fin structure 16 and the second fin structure 17 include sacrificial layers 121 and channel layers 131 alternately stacked along the thickness direction of the semiconductor substrate 11, and an isolation layer 151 that penetrates the alternately stacked sacrificial layers 121 and channel layers 131. The sacrificial layer 121 is the bottommost layer of the alternately stacked sacrificial layers 121 and channel layers 131. The isolation layer 151 included in the first fin structure 16 and the isolation layer 151 included in the second fin structure 17 have different widths.

[0076] Specifically, the channel layer included in the first fin structure is a film layer used to manufacture the corresponding first nanowire or sheet, so the material, thickness, number of layers and other information of the channel layer included in the first fin structure can be set with reference to the material, thickness of the first nanowire or sheet, and the number of layers of the first nanowire or sheet included in each column of the first channel portion. The position of the isolation layer included in the first fin structure will form a gap between two adjacent columns of the first channel portion, so the number of isolation layers included in the first fin structure, the width of each isolation layer, and the position of each isolation layer in the first fin structure can be determined according to the number of columns of the first channel portion included in the first channel region, the spacing between two adjacent columns of the first channel portion, and the width of each column of the first channel portion. For example: Figure 6 As shown, when the first channel region includes two first channel portions, and the width of each first channel portion is the same, the first fin structure includes an isolation layer 151, and the geometric center line of the isolation layer 151 coincides with the geometric center line of the first fin structure. Or, Figure 7 As shown, when the first channel region includes two first channel portions and each first channel portion has a different width, the first fin structure includes an isolation layer 151 , and the geometric center line of the isolation layer 151 is not on the same straight line as the geometric center line of the first fin structure.

[0077] Correspondingly, the channel layer included in the second fin structure is a film layer used to manufacture the corresponding second nanowire or sheet, so the material, thickness, number of layers and other information of the channel layer included in the second fin structure can be set with reference to the material, thickness, and number of layers of the second nanowire or sheet included in each column of the second channel portion. The position of the isolation layer included in the second fin structure will form a gap between two adjacent columns of second channel portions, so the number of isolation layers included in the second fin structure, the width of each isolation layer, and the position of each isolation layer in the second fin structure can be determined according to the number of columns of second channel portions included in the second channel region, the spacing between two adjacent columns of second channel portions, and the width of each column of second channel portions. For example: Figure 6 As shown, when the second channel region includes two second channel portions, and each second channel portion has the same width, the second fin structure includes an isolation layer 151, and the geometric centerline of the isolation layer 151 coincides with the geometric centerline of the second fin structure. Alternatively, when the second channel region includes two second channel portions, and each second channel portion has a different width, the second fin structure includes an isolation layer 151, and the geometric centerline of the isolation layer 151 is not collinear with the geometric centerline of the second fin structure.

[0078] In addition, in the above-mentioned alternating stacked sacrificial layers and channel layers, the topmost film layer can be a sacrificial layer or a channel layer. In the case where the topmost film layer is a sacrificial layer, the presence of the sacrificial layer can protect the channel layer located thereunder from being affected by operations such as etching during the formation of the first fin structure and the second fin structure, thereby improving the formation quality of the first channel region and the second channel region. As for the material of the above-mentioned sacrificial layer, it can be any semiconductor material different from the material of the channel layer. For example, when the material of the channel layer is Si, the material of the sacrificial layer can be Si. 0.5 Ge 0.5 .

[0079] In the actual manufacturing process, the first fin structure and the second fin structure can be formed simultaneously or in different steps. The specific order of forming the first fin structure and the second fin structure can be set according to the actual application scenario and is not specifically limited here.

[0080] When the first fin structure and the second fin structure are formed simultaneously, forming the first fin structure and the second fin structure may include the following steps:

[0081] like Figure 1 Part (1) and (2), and Figure 2 As shown, sacrificial material layers 12 and channel material layers 13 are alternately stacked on the semiconductor substrate 11 along the thickness direction of the semiconductor substrate 11 .

[0082] For example, the above-mentioned sacrificial material layer and channel material layer can be formed by epitaxial growth or other processes. The sacrificial material layer is a film layer used to form the above-mentioned sacrificial layer, and the channel material layer is a film layer used to form the above-mentioned channel layer. Therefore, the formation of the sacrificial material layer and the channel material layer formed on the semiconductor substrate can be determined based on the distribution of the sacrificial layer and the channel layer in the first fin structure and the second fin structure described above. For example: Figure 6 As shown, in the case where both the first fin structure and the second fin structure include two sacrificial layers 121 and two channel layers 131, as shown in FIG. Figure 1 As shown in part (1) of FIG. 1 , two sacrificial material layers 12 and two channel material layers 13 need to be formed on the semiconductor substrate 11. Alternatively, as shown in FIG. Figure 1 As shown in part (2), three sacrificial material layers 12 and two channel material layers 13 need to be formed on the semiconductor substrate 11. Among them, the topmost and bottommost film layers are both sacrificial material layers 12.

[0083] like Figure 3 As shown, a first patterning process is performed on the alternately stacked sacrificial material layers 12 and channel material layers 13 to form at least two trenches 14 with different widths penetrating the alternately stacked sacrificial material layers 12 and channel material layers 13 .

[0084] For example, processes such as photolithography and etching can be used to form the at least two trenches. Each trench will subsequently be filled with a corresponding isolation layer. Therefore, the number and width of the trenches to be formed can be determined based on information such as the number and width of the isolation layers included in the first and second fin structures. This is not detailed here.

[0085] like Figure 5 As shown, an isolation layer 151 is formed to fill each trench.

[0086] For example, Figure 4 As shown, an atomic layer deposition process can be used to form an isolation material 15 covering the alternately stacked sacrificial material layer 12 and the channel material layer 13 and filling the trench. Figure 5 As shown, the isolation material may then be planarized using a process such as chemical mechanical polishing to remove the portion of the isolation material outside the trench, so that the remaining isolation material forms an isolation layer 151 .

[0087] like Figure 6 and Figure 7 As shown, the alternately stacked sacrificial material layers and channel material layers, and the semiconductor substrate 11 are subjected to a second patterning process to form a first fin structure 16 and a second fin structure 17. Figure 8As shown, the first fin structure 16 and the second fin structure 17 each have a source formation region 20 , a drain formation region 21 , and a transition region 22 located between the source formation region 20 and the drain formation region 21 .

[0088] For example, a mask layer covering the alternately stacked sacrificial material layer and channel material layer, and the isolation layer may be formed using a technique such as SADP. Figure 6 and Figure 7 As shown, the second patterning process is then performed under the masking effect of the mask layer. Whether the geometric centerline of the sub-pattern covered by the mask layer on each isolation layer 151 coincides with the geometric centerline of the isolation layer 151 can be determined based on the position of the isolation layer 151 within the first fin structure or the second fin structure. Furthermore, the depth of the etching of the semiconductor substrate 11 can be determined based on the thickness of the subsequently formed shallow trench isolation structure.

[0089] like Figure 8 and Figure 9 As shown, chemical vapor deposition and etching processes can be used to form a shallow trench isolation structure 19 on the semiconductor substrate 11. The material and other information of the shallow trench isolation structure 19 can be found in the above text and will not be repeated here.

[0090] like Figure 21 As shown, after obtaining the first fin structure and the second fin structure, a first all-around gate transistor is formed based on the first fin structure, and a second all-around gate transistor is formed based on the second fin structure.

[0091] In actual applications, a replacement gate process is typically used to form the first gate stack structure included in the first gate-all-around transistor and the second gate stack structure included in the second gate-all-around transistor to improve the quality of the first gate stack structure and the second gate stack structure. In this case, forming the first gate-all-around transistor based on the first fin structure and forming the second gate-all-around transistor based on the second fin structure may include the following steps:

[0092] like Figure 10 As shown, chemical vapor deposition and etching processes can be used to first form a sacrificial gate 23 across the transition region of the first fin structure 16 and the transition region of the second fin structure 17. The sacrificial gate 23 can be made of a material that is easy to remove, such as polysilicon.

[0093] For example, Figure 11As shown, after forming the sacrificial gate 23, chemical vapor deposition and etching processes can be used to form gate sidewalls 24 located at least on both sides of the sacrificial gate 23 along the length direction, so as to at least isolate the subsequently formed first gate stack structure and second gate stack structure from other conductive structures, thereby improving the electrical characteristics of the semiconductor device. The length direction of the sacrificial gate 23 is parallel to the length direction of the first fin structure 16 and the second fin structure 17. The thickness of the gate sidewall 24 can be set according to actual needs and is not specifically limited here. The material of the gate sidewall 24 can be an insulating material such as silicon oxide or silicon nitride.

[0094] like Figure 16 As shown, the portion of the first fin structure located in the source formation region and the drain formation region is processed to form a first source region 28 and a first drain region 29 included in the first all-around gate transistor; and the portion of the second fin structure located in the source formation region and the drain formation region is processed to form a second source region 30 and a second drain region 31 included in the second all-around gate transistor.

[0095] For example, taking the formation of the first source region and the first drain region as an example, a first mask layer is first formed to cover at least the second region. Then, under the masking effect of the first mask layer, an ion implantation process is performed on the source and drain regions included in the first fin structure to form the first source and drain regions. After the first mask layer is removed, the first mask layer is removed. A second mask layer is then formed to cover at least the region. Under the masking effect of the second mask layer, an ion implantation process is performed on the source and drain regions included in the second fin structure to form the second source and drain regions. Finally, the second mask layer is removed.

[0096] Alternatively, the first source region, the first drain region, the second source region and the second drain region may be formed by source-drain epitaxy. In this case, the above-mentioned formation of the first source region and the first drain region may include the following steps: Figure 12 As shown, the portion of the first fin structure located in the source formation region and the drain formation region is removed. Figure 16 As shown, an epitaxial growth process is used to form a first source region 28 and a first drain region 29 on both sides of the portion of the first fin structure located in the transition region along the length direction.

[0097] In addition, the above-mentioned formation of the second source region and the second drain region may include the following steps: Figure 12 As shown, the portion of the second fin structure 17 located in the source formation region and the drain formation region is removed. Figure 16 As shown, an epitaxial growth process is used to form a second source region 30 and a second drain region 31 on both sides of the portion of the second fin structure 17 located in the transition region along the length direction.

[0098] Specifically, such as Figure 12As shown, dry or wet etching processes can be used to simultaneously remove the portions of the first fin structure located within the source and drain regions, as well as the portions of the second fin structure located within the source and drain regions. Then, under the masking of the corresponding mask layer, the first source region and the first drain region are formed first, or the second source region and the second drain region are formed first.

[0099] It should be noted that the formation process of the first source region and the first drain region can be the same as or different from the formation process of the second source region and the second drain region. For example, the first source region and the first drain region can be formed using an ion implantation process, while the second source region and the second drain region can be formed using a source-drain epitaxy process. Furthermore, when the first gate-all-around transistor and the second gate-all-around transistor have the same conductivity type and utilize the same manufacturing process, the first source region, the first drain region, the second source region, and the second drain region can be formed simultaneously without forming the corresponding mask layers.

[0100] In one example, when forming the first source region and the first drain region by using a process such as epitaxial growth, after removing the portion of the first fin structure located in the source formation region and the drain formation region, and before forming the first source region and the first drain region on both sides of the portion of the first fin structure located in the transition region along the length direction by using an epitaxial growth process, the manufacturing method of the semiconductor device may include the steps of: etching the edge regions on both sides of the portion of the sacrificial layer and / or isolation layer included in the first fin structure located in the transition region along the length direction of the sacrificial gate, so that the sidewalls of the remaining portion of the sacrificial layer and / or isolation layer included in the first fin structure are concave inward relative to the sidewalls of the sacrificial gate, forming a first notch. Figures 13 to 15 As shown, a first inner sidewall 25 is formed to fill the first recess.

[0101] Specifically, such as Figure 13 As shown, when the first inner sidewall spacer 25 of the manufactured semiconductor device is formed between two adjacent columns of first channel portions, etching can be performed only on the edge regions on both sides of the portion of the isolation layer included in the first fin structure located in the transition region. In this case, only the sidewalls of the remaining portion of the isolation layer included in the first fin structure are recessed inwardly relative to the sidewalls of the sacrificial gate 23.

[0102] like Figure 14 As shown, when the first inner sidewall spacer 25 included in the manufactured semiconductor device is formed between adjacent first nanowires or sheets included in the same first channel portion, and between the first nanowires or sheets and the semiconductor substrate 11, only the edge regions on both sides of the portion of the sacrificial layer included in the first fin structure located in the transition region can be etched. In this case, only the sidewalls of the remaining portion of the sacrificial layer included in the first fin structure are recessed inwardly relative to the sidewalls of the sacrificial gate 23.

[0103] like Figure 15As shown, when the first inner sidewall spacer 25 of the manufactured semiconductor device fully fills the first intermediate region between the first gate stack structure and the first source region, and between the first gate stack structure and the first drain region, the edge regions on both sides of the portion of the sacrificial layer and the isolation layer included in the first fin structure located in the transition region can be etched. At this time, the sidewalls of the remaining portions of the sacrificial layer and the isolation layer included in the first fin structure are recessed inward relative to the sidewalls of the sacrificial gate 23.

[0104] After forming a first recess with a desired morphology based on the requirements of the actual application scenario, a chemical vapor deposition and etching process can be used to completely fill the first recess with a first inner sidewall. The material of the first inner sidewall must have a certain etching selectivity with the material of the isolation layer to prevent the first inner sidewall from being affected during the subsequent removal of the isolation layer, thereby improving the quality of the first inner sidewall. For example, if the isolation layer is made of silicon nitride, the material of the first inner sidewall can be silicon oxide.

[0105] In one example, when forming the second source region and the second drain region by using a process such as epitaxial growth, after removing the portion of the second fin structure located in the source formation region and the drain formation region, before forming the second source region and the second drain region on both sides of the portion of the second fin structure located in the transition region along the length direction by using an epitaxial growth process, the manufacturing method of the above-mentioned semiconductor device may further include the steps of: etching the edge regions on both sides of the portion of the sacrificial layer and / or isolation layer included in the second fin structure located in the transition region along the length direction of the sacrificial gate, so that the sidewalls of the remaining portion of the sacrificial layer and / or isolation layer included in the second fin structure are concave inward relative to the sidewalls of the sacrificial gate, forming a second notch. Figures 13 to 15 As shown, a second inner sidewall 26 is formed to fill the second recess.

[0106] Specifically, the specific objects to be etched when forming the second notch can refer to the analysis process of the objects to be etched when forming the first notch described above, and will not be repeated here. In addition, the material of the second inner sidewall needs to have a certain etching selectivity with the material of the isolation layer.

[0107] like Figure 17 As shown, after at least the first source region 28, the first drain region, the second source region 30, and the second drain region are formed, chemical vapor deposition and chemical mechanical polishing processes can be used to form a dielectric layer 34 covering at least the first region 111 and the second region 112. The top of the dielectric layer 34 is flush with the top of the sacrificial gate 23.

[0108] like Figure 18 As shown, a dry etching process or a wet etching process may be used to remove the sacrificial gate, so that the portion of the first fin structure located in the transition region and the portion of the second fin structure located in the transition region are exposed.

[0109] like Figure 19 and Figure 20 As shown, a dry etching process or a wet etching process can be used to selectively remove the portion of the sacrificial layer included in the first fin structure located in the transition region, so that the channel layer included in the first fin structure forms a first channel region 35; and selectively remove the portion of the sacrificial layer included in the second fin structure located in the transition region, so that the channel layer included in the second fin structure forms a second channel region 36.

[0110] like Figure 19 and Figure 20 As shown, a dry etching process or a wet etching process may be used to remove the portion of the isolation layer included in the first fin structure and the portion of the isolation layer included in the second fin structure and the portion of the isolation layer included in the transition region.

[0111] It should be noted that the removal order of the portion of the sacrificial layer located in the transition region and the portion of the isolation layer located in the transition region can be interchanged, and the removal order of the two is not specifically limited in the embodiment of the present invention.

[0112] like Figure 21 As shown, atomic layer deposition and other processes can be used to form a first gate stack structure 38 surrounding the first channel region 35 to obtain a first ring-gate transistor; and to form a second gate stack structure 39 surrounding the second channel region 36 to obtain a second ring-gate transistor.

[0113] In one example, as described above, the method for manufacturing a semiconductor device provided by an embodiment of the present invention is compatible with the manufacturing process of a conventional gate-all-around transistor. Based on this, when the manufactured semiconductor device further includes a third gate-all-around transistor, as Figure 2 As shown, the semiconductor substrate 11 further has a third region 113. Moreover, after providing the semiconductor substrate 11, the manufacturing method of the semiconductor device further includes: Figure 21 As shown, a third gate-all-around transistor is formed on the third region 113. The third gate-all-around transistor includes a third channel region 37 having a column of third channel portions 371.

[0114] The manufacturing method provided in the embodiment of the present invention does not specifically limit the specific formation process of the third ring-gate transistor. Figures 6 to 9 As shown, a third fin structure 18 can be formed on the third region 113 during the process of forming the first fin structure 16 and the second fin structure 17. The width of the third fin structure 18 can be the same as the width of the first fin structure 16 and the second fin structure 17. In addition, the third fin structure 18 also includes a sacrificial layer 121 and a channel layer 131 alternately stacked. However, the third fin structure 18 does not include an isolation layer 151. Figure 10 and Figure 11As shown, when the third gate stack structure is manufactured using a replacement gate process, the sacrificial gate 23 and the gate spacer 24 also span the portion of the third fin structure 18 located in the transition region. Figure 16 As shown, the third source region 32 and the third drain region 33 can be formed by ion implantation or source-drain epitaxy. The order of forming the third source region 32 and the third drain region 33 and the order of forming the first source region, the first drain region, the second source region and the second drain region can be set according to actual needs and are not specifically limited here. Figures 17 to 20 As shown, after forming the dielectric layer 34 and removing the sacrificial gate 23, the portions of the sacrificial layer 121 included in the first fin structure, the second fin structure, and the third fin structure located in the transition region can be removed simultaneously, and the first channel region 35, the second channel region 36, and the third channel region 37 can be formed simultaneously. Figure 21 As shown, finally, a third gate stack structure 40 is formed by using processes such as atomic layer deposition.

[0115] While the above description does not provide detailed technical details regarding patterning and etching of each layer, those skilled in the art will appreciate that various technical means can be employed to form layers, regions, and the like in desired shapes. Furthermore, those skilled in the art may devise methods that differ from those described above to form the same structure. Furthermore, while each embodiment has been described separately, this does not mean that the measures in each embodiment cannot be advantageously combined.

[0116] The above describes the embodiments of the present disclosure. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make various substitutions and modifications, which are intended to fall within the scope of the present disclosure.

Claims

1. A semiconductor device, characterized in that: include: semiconductor substrates; Along a direction parallel to a surface of the semiconductor substrate, the semiconductor substrate includes a first region and a second region; A first gate-all-around transistor is formed on the first region; along a width direction parallel to a first gate stack structure included in the first gate-all-around transistor, the first channel region included in the first gate-all-around transistor has at least two columns of first channel portions spaced apart; A second ring-gate transistor is formed on the second region; along a width direction parallel to the second gate stack structure included in the second ring-gate transistor, the second channel region included in the second ring-gate transistor has at least two columns of second channel portions spaced apart; the spacing between two adjacent columns of the second channel portions is different from the spacing between two adjacent columns of the first channel portions; the width of at least one column of the second channel portions in the second channel region is different from the width of at least one column of the first channel portions in the first channel region.

2. The semiconductor device according to claim 1, wherein The width of the first channel region is equal to the sum of the total width of all the first channel portions and the total width of the interval between two adjacent first channel portions; The width of the second channel region is equal to the sum of the total width of all the second channel portions and the total width of the interval between two adjacent second channel portions; The width of the first channel region is the same as the width of the second channel region.

3. The semiconductor device according to claim 1, wherein The width of each column of first channel portions included in the first channel region is the same; and / or, The width of each column of second channel portions included in the second channel region is the same.

4. The semiconductor device according to claim 1, wherein The first all-around gate transistor includes a first source region and a first drain region; the first channel region is located between the first source region and the first drain region, and each column of the first channel portion is in contact with the first source region and the first drain region respectively; The second all-around gate transistor includes a second source region and a second drain region; the second channel region is located between the second source region and the second drain region, and each column of the second channel portion is in contact with the second source region and the second drain region respectively.

5. The semiconductor device according to claim 4, wherein The first all-around gate transistor further includes a first inner sidewall, wherein the first inner sidewall is formed between the first gate stack structure and the first source region, and between the first gate stack structure and the first drain region; The second ring-gate transistor further includes a second inner sidewall formed between the second gate stack and the second source region, and between the second gate stack structure and the second drain region.

6. The semiconductor device according to claim 5, wherein A first intermediate region is provided between the first gate stack structure and the first source region, and between the first gate stack structure and the first drain region; the first gate stack structure includes a first portion located between the first channel portions, and between the first channel portion and the semiconductor substrate; the first intermediate region is a region between the first source region and the first drain region, respectively, and the first portion; The first inner wall fills the first middle area; and / or, There is a second intermediate region between the second gate stack structure and the second source region, and between the second gate stack structure and the second drain region; the second gate stack structure includes a second part located between the second channel portions, and between the second channel portion and the semiconductor substrate; the second intermediate region is the region between the second source region and the second drain region and the second parts respectively; the second inner sidewall fills the second intermediate region.

7. The semiconductor device according to claim 1, wherein Along a thickness direction parallel to the semiconductor substrate, each column of the first channel portions includes at least two layers of first nanowires or sheets spaced apart from each other; and / or, Along a thickness direction parallel to the semiconductor substrate, each column of the second channel portions includes at least two layers of second nanowires or sheets spaced apart from each other.

8. The semiconductor device according to claim 1, wherein The first gate-all-around transistor and the second gate-all-around transistor have different conductivity types.

9. The semiconductor device according to any one of claims 1 to 8, wherein: The semiconductor substrate further includes a third region; The semiconductor device further includes a third gate-all-around transistor formed on the third region, wherein the third gate-all-around transistor includes a third channel region having a column of third channel portions.

10. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor substrate; Along a direction parallel to a surface of the semiconductor substrate, the semiconductor substrate includes a first region and a second region; A first ring-gate transistor is formed on the first area, and a second ring-gate transistor is formed on the second area; along a width direction parallel to the first gate stack structure included in the first ring-gate transistor, the first channel region included in the first ring-gate transistor has at least two columns of first channel portions spaced apart; along a width direction parallel to the second gate stack structure included in the second ring-gate transistor, the second channel region included in the second ring-gate transistor has at least two columns of second channel portions spaced apart; the spacing between two adjacent columns of the second channel portions is different from the spacing between two adjacent columns of the first channel portions; the width of at least one column of the second channel portions in the second channel region is different from the width of at least one column of the first channel portions in the first channel region.

11. The method for manufacturing a semiconductor device according to claim 10, wherein: The forming of a first gate-all-around transistor on the first region and a second gate-all-around transistor on the second region comprises: A first fin structure is formed on the first region, and a second fin structure having the same width as the first fin structure is formed on the second region; the first fin structure and the second fin structure both include sacrificial layers and channel layers alternately stacked along the thickness direction of the semiconductor substrate, and an isolation layer penetrating the alternately stacked sacrificial layers and channel layers; the sacrificial layer is the bottommost layer of the alternately stacked sacrificial layers and channel layers; the isolation layer included in the first fin structure and the isolation layer included in the second fin structure have different widths; The first gate-all-around transistor is formed based on the first fin structure, and the second gate-all-around transistor is formed based on the second fin structure.

12. The method for manufacturing a semiconductor device according to claim 11, wherein: The forming of a first fin structure on the first region and a second fin structure having the same width as the first fin structure on the second region includes: forming alternatingly stacked sacrificial material layers and channel material layers on the semiconductor substrate along a thickness direction of the semiconductor substrate; performing a first patterning process on the alternately stacked sacrificial material layers and channel material layers to form at least two grooves with different widths penetrating the alternately stacked sacrificial material layers and channel material layers; forming the isolation layer to fill each of the trenches; A second patterning process is performed on the alternately stacked sacrificial material layers and channel material layers and the semiconductor substrate to form the first fin structure and the second fin structure.

13. The method for manufacturing a semiconductor device according to claim 11, wherein: The geometric center line of the isolation layer included in the first fin structure coincides with the geometric center line of the first fin structure; and / or, A geometric center line of the isolation layer included in the second fin structure coincides with a geometric center line of the second fin structure.

14. The method for manufacturing a semiconductor device according to claim 11, wherein: The first fin structure and the second fin structure each have a source formation region, a drain formation region, and a transition region between the source formation region and the drain formation region; The forming of the first gate-all-around transistor based on the first fin structure and the forming of the second gate-all-around transistor based on the second fin structure includes: forming a sacrificial gate spanning a transition region included in the first fin structure and a transition region included in the second fin structure; Processing a portion of the first fin structure located within the source formation region and the drain formation region to form a first source region and a first drain region included in the first all-around gate transistor; and processing a portion of the second fin structure located within the source formation region and the drain formation region to form a second source region and a second drain region included in the second all-around gate transistor; removing the sacrificial grid; selectively removing a portion of the sacrificial layer included in the first fin structure located in the transition region, so that the channel layer included in the first fin structure forms the first channel region; and selectively removing a portion of the sacrificial layer included in the second fin structure located in the transition region, so that the channel layer included in the second fin structure forms the second channel region; removing a portion of the isolation layer included in the first fin structure and located in the transition region, and a portion of the isolation layer included in the second fin structure and located in the transition region; The first gate stack structure is formed around the periphery of the first channel region to obtain the first ring-gate transistor; and the second gate stack structure is formed around the periphery of the second channel region to obtain the second ring-gate transistor.

15. The method for manufacturing a semiconductor device according to claim 14, wherein: The processing of the portion of the first fin structure located in the source formation region and the drain formation region to form the first source region and the first drain region of the first all-around gate transistor includes: removing the portion of the first fin structure located in the source formation region and the drain formation region; and forming the first source region and the first drain region on both sides of the portion of the first fin structure located in the transition region along the length direction by using an epitaxial growth process; The processing of the portion of the second fin structure located in the source formation region and the drain formation region to form the second source region and the second drain region included in the second ring-gate transistor includes: removing the portion of the second fin structure located in the source formation region and the drain formation region; and using an epitaxial growth process to form the second source region and the second drain region on both sides of the portion of the second fin structure located in the transition region along the length direction.

16. The method for manufacturing a semiconductor device according to claim 15, wherein: After removing the portion of the first fin structure located in the source formation region and the drain formation region, and before forming the first source region and the first drain region on both sides of the portion of the first fin structure located in the transition region along the length direction using an epitaxial growth process, the method for manufacturing the semiconductor device includes: Etching edge regions on both sides of a portion of the sacrificial layer and / or isolation layer included in the first fin structure located in the transition region along a length direction of the sacrificial gate, so that sidewalls of a remaining portion of the sacrificial layer and / or isolation layer included in the first fin structure are recessed inwardly relative to sidewalls of the sacrificial gate, forming a first notch; forming a first inner sidewall that fills the first recess; and / or, After removing the portion of the second fin structure located in the source formation region and the drain formation region, and before forming the second source region and the second drain region on both sides of the portion of the second fin structure located in the transition region along the length direction using an epitaxial growth process, the method for manufacturing the semiconductor device includes: Etching edge regions on both sides of a portion of the sacrificial layer and / or isolation layer included in the second fin structure located in the transition region along the length direction of the sacrificial gate, so that sidewalls of the remaining portion of the sacrificial layer and / or isolation layer included in the second fin structure are recessed inwardly relative to the sidewalls of the sacrificial gate, forming a second notch; A second inner sidewall is formed to fill the second recess.

17. The method for manufacturing a semiconductor device according to any one of claims 10 to 16, wherein: The semiconductor substrate further comprises a third region; After providing a semiconductor substrate, the method for manufacturing a semiconductor device further includes: forming a third all-around gate transistor on the third region; the third all-around gate transistor includes a third channel region having a row of third channel portions.

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