Semiconductor device with enhanced reverse avalanche capability and method of fabrication

Abstract

Semiconductor device with enhanced reverse avalanche capability and method of manufacture, relates to power devices. It comprises: an N-layer; an active region, which is located at the end of the N-layer and extends downward from the top surface of the N-layer; a voltage division ring, which is spaced apart from the active region and extends downward from the top surface of the N-layer; an oxide layer, which is arranged above the N-layer; a trench region, which passes through the voltage division ring from the top surface of the oxide layer and extends into the N-layer; and a trench dielectric layer, which is attached to the trench region and extends downward from the top surface of the N-layer. The invention limits the trench region to the voltage division ring, adjusts the distance between the voltage division ring and the active region, ensures that the strongest electric field is on the voltage division ring, and in reverse, the current flows from the main junction (active region) and is separated from the strongest electric field, while not in contact with the dielectric layer in the trench, thereby improving the reverse avalanche capability of the product.

Description

Technical Field

[0001] This invention relates to power devices, and more particularly to semiconductor devices and methods for fabricating them that enhance reverse avalanche capability. Background Technology

[0002] With the sustained and rapid development of my country's economy, energy consumption has increased year by year, and demand has become increasingly tight. Energy conservation has become a fundamental national policy in my country. Therefore, vigorously developing the design, manufacturing, and application of new power electronic devices is an important measure for energy conservation.

[0003] Power semiconductor devices, which process electrical energy, have breakdown voltage as one of their most critical electrical parameters. The breakdown voltage a power semiconductor device can withstand depends on the electric field distribution during avalanche breakdown. Trench termination technology removes the curved junction portion of the main junction by etching trenches, thus eliminating the semiconductor region with concentrated electric field strength—the area of ​​strongest electric field. By filling the trench with dielectric material, the high electric field is transferred to a dielectric region with a lower dielectric constant but a higher critical breakdown electric field, thereby improving the breakdown voltage and reducing the termination width.

[0004] Trench termination structures offer advantages such as small size and high efficiency. However, they rely solely on the trench dielectric, which has a higher critical breakdown electric field, to withstand the high field strength. They do not completely eliminate field concentration, particularly near the PN junction in direct contact with the dielectric layer within the trench. This high field strength leads to a large avalanche current during reverse avalanche due to the chip's edge effect. Regions with concentrated field strength and high current density experience higher power, resulting in higher localized temperatures. This, in turn, reduces the device's reverse avalanche capability. Summary of the Invention

[0005] To address the above problems, this invention provides a novel terminal that combines the high efficiency of a trench terminal with reduced heat generation caused by the superposition of current field strength after avalanche, thereby enhancing the avalanche capability and reverse avalanche capability of the semiconductor device and its fabrication method.

[0006] The technical solution of this invention is: a semiconductor device that enhances reverse avalanche capability, comprising: N-layer; An active region is located at the end of the N-layer and extends downward from the top surface of the N-layer; The voltage dividing ring is spaced apart from the active region and extends downward from the top surface of the N-layer; An oxide layer is disposed above the N-layer; The trench region extends downward from the top surface of the oxide layer through the pressure dividing ring and into the N-layer; and A trench medium layer is attached to the trench region and extends downward from the top surface of the N-layer.

[0007] Furthermore, the depth of the active region is 5-25 μm.

[0008] Furthermore, the depth of the pressure dividing ring is 5-25 μm.

[0009] Furthermore, the thickness of the trench medium layer is 10-100 μm.

[0010] Furthermore, the depth of the trench area is 30-100 μm.

[0011] Furthermore, the height of the oxide layer is 0.5-2.5 μm.

[0012] Furthermore, a method for fabricating a semiconductor device with enhanced reverse avalanche capability includes the following steps: 100), N substrate selection; 200) An oxide layer is prepared on an N substrate, and the oxide layer on the active region and the voltage divider ring to be prepared is removed to form the active region and the voltage divider ring. 300) Expose the trench area to be prepared, and cover the rest with an oxide layer. Then, etch the trench area by an etching process. 400) Fill the trench area with a trench medium layer, and then melt the glass and attach it to the trench through an annealing process.

[0013] Furthermore, in step 300), the oxide layer is grown by a thermal oxidation process, and its thickness is 0.5-2.5 μm.

[0014] Further, in step 300), the trench area is etched using a silicon etching solution to form a trench morphology.

[0015] This invention confines the trench region to the voltage divider ring and adjusts the distance between the voltage divider ring and the active region to ensure that the strongest electric field is on the voltage divider ring. In the reverse direction, the current flows from the main junction (active region), separating from the strongest electric field, and does not contact the dielectric layer inside the trench, thereby improving the reverse avalanche capability of the product. Attached Figure Description

[0016] Figure 1 This is a schematic diagram of the structure after the active region and pressure dividing ring have been fabricated. Figure 2 This is a schematic diagram of the structure when the trench area is to be prepared. Figure 3 This is a schematic diagram of the structure after the trench region has been fabricated. Figure 4 This is a schematic diagram of the structure of the device of the present invention; In the figure, 1 is the N-layer, 2 is the oxide layer, 3 is the active region, 4 is the voltage divider ring, 5 is the trench dielectric layer, and 6 is the trench region. Detailed Implementation

[0017] Embodiments of the present invention are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and should not be construed as limiting the present invention.

[0018] In the description of this invention, it should be understood that the terms "upper," "lower," "left," "right," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings, and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. In the description of this invention, unless otherwise stated, "a plurality of" means two or more.

[0019] The present invention is as follows Figure 1-4 As shown; semiconductor devices that enhance reverse avalanche capability include: N-layer 1; Active region 3, which is located at the end of N-layer 1 and extends downward from the top surface of N-layer 1; The voltage dividing ring 4 is disposed at an interval from the active region 3 and extends downward from the top surface of the N-layer 1; Oxide layer 2, wherein the oxide layer 2 is disposed above the N-layer; Trench region 6, which extends downward from the top surface of the oxide layer 2 through the pressure dividing ring 4 and into the N-layer 1; and A trench dielectric layer 5 is attached to the trench region 6 and extends downward from the top surface of the N-layer 1. The trench dielectric layer 5 is a glass passivation layer, providing good PN junction protection. The depth of the trench region 6 is generally 30µm deeper than the PN junction depth to ensure good PN junction protection and improve product reliability.

[0020] Further specified, the depth of the active region 3 is 5-25 μm.

[0021] Further specified, the depth of the pressure dividing ring 4 is 5-25 μm.

[0022] Further specified, the thickness of the trench medium layer 5 is 10-100 μm.

[0023] Further specified, the depth of the trench region 6 is 30-100um.

[0024] Further specified, the height of the oxide layer is 0.5-2.5 μm.

[0025] A method for fabricating a semiconductor device with enhanced reverse avalanche capability includes the following steps: 100), N substrate selection; 200) An oxide layer 2 is prepared on an N substrate, and the oxide layer 2 on the active region 3 and the voltage divider ring 4 to be prepared is removed to form the active region 3 and the voltage divider ring 4. 300) Expose the trench region 6 to be prepared, and cover the rest with oxide layer 2. Then, etch the trench region 6 by etching process. 400) Fill the groove medium layer 5 in the groove area 6, and melt the glass and attach it to the groove through an annealing process with an annealing temperature range of 800-900℃.

[0026] Further specified, in step 300), the oxide layer (2) is grown by thermal oxidation process and has a thickness of 0.5-2.5 μm.

[0027] Further defining step 300), the trench area (6) is etched using silicon etching solution to form a trench morphology.

[0028] When a device withstands reverse breakdown voltage, the electric field strength at the PN junction of the device increases with the increase of the breakdown voltage. When the electric field strength increases to the critical breakdown field strength of silicon, carrier avalanche multiplication occurs, at which point the reverse current increases sharply. Avalanche itself is not a damage process. During this process, due to the high electric field strength and large reverse leakage current, local power consumption increases, leading to a rise in the local temperature of the silicon wafer. When the temperature exceeds the critical value allowed by the silicon's inherent characteristics, failure occurs. In this case, we separated the location of the highest electric field strength from the location of the maximum leakage current, reducing local power and delaying the temperature rise time, thereby improving the reverse avalanche energy of the device.

[0029] Regarding the information disclosed in this case, the following points need to be clarified: (1) The accompanying drawings of the embodiments disclosed in this case only involve the structures involved in the embodiments disclosed in this case. Other structures can refer to the general design. (2) Where there is no conflict, the embodiments and features disclosed in this case can be combined with each other to obtain new embodiments; The above are merely specific embodiments disclosed in this case, but the scope of protection of this disclosure is not limited thereto. The scope of protection disclosed in this case shall be determined by the scope of protection of the claims.

Claims

1. A semiconductor device for enhancing reverse avalanche capability, characterized in that, include: N-layer (1); The active region (3) is located at the end of the N-layer (1) and extends downward from the top surface of the N-layer (1); The voltage dividing ring (4) is spaced apart from the active region (3) and extends downward from the top surface of the N-layer (1); Oxide layer (2), the oxide layer (2) being disposed above the N-layer; The trench region (6) extends downward from the top surface of the oxide layer (2) through the pressure dividing ring (4) and into the N-layer (1); The trench region (6) is confined on the voltage divider ring (4). By adjusting the distance between the voltage divider ring (4) and the active region (3), the strongest electric field is ensured to be located on the voltage divider ring (4). In the reverse direction, the current flows through the active region (3), which is spatially separated from the strongest electric field, and the PN junction does not directly contact the dielectric layer in the trench. And a trench medium layer (5), the trench medium layer (5) is attached to the trench area (6) and extends downward from the top surface of the N-layer (1); The trench area (6) is deeper than the PN junction to ensure good protection of the PN junction.

2. The semiconductor device for enhancing reverse avalanche capability according to claim 1, characterized in that, The depth of the active region (3) is 5-25 μm.

3. The semiconductor device for enhancing reverse avalanche capability according to claim 1, characterized in that, The depth of the pressure dividing ring (4) is 5-25 μm.

4. The semiconductor device for enhancing reverse avalanche capability according to claim 1, characterized in that, The thickness of the trench medium layer (5) is 10-100 μm.

5. The semiconductor device for enhancing reverse avalanche capability according to claim 1, characterized in that, The depth of the trench area (6) is 30-100um.

6. The semiconductor device for enhancing reverse avalanche capability according to claim 1, characterized in that, The height of the oxide layer is 0.5-2.5 μm.

7. A method for fabricating a semiconductor device with enhanced reverse avalanche capability, characterized in that, Includes the following steps: 100), N substrate selection; 200) An oxide layer (2) is prepared on an N substrate. The oxide layer (2) on the active region (3) to be prepared and the voltage divider ring (4) are removed to prepare the active region (3) and the voltage divider ring (4). 300) Expose the trench area (6) to be prepared, and cover the rest with an oxide layer (2). Then, etch the trench area (6) by etching process. 400) Fill the trench medium layer (5) in the trench area (6) and melt the glass and attach it to the trench through the annealing process; The trench region (6) is confined on the voltage divider ring (4). By adjusting the distance between the voltage divider ring (4) and the active region (3), the strongest electric field is ensured to be located on the voltage divider ring (4). In the reverse direction, the current flows through the active region (3), which is spatially separated from the strongest electric field, and the PN junction does not directly contact the dielectric layer in the trench. The trench area (6) is deeper than the PN junction to ensure good protection of the PN junction.

8. The method for fabricating a semiconductor device with enhanced reverse avalanche capability according to claim 7, characterized in that, In step 300), the oxide layer (2) is grown by thermal oxidation process and has a thickness of 0.5-2.5 μm.

9. The method for fabricating a semiconductor device with enhanced reverse avalanche capability according to claim 7, characterized in that, In step 300), the trench area (6) is etched using silicon etching solution to form a trench morphology.

Images