An enhanced MIS gate controlled power device with P-type gate

Abstract

The application belongs to the technical field of power semiconductors, and relates to a high-voltage semiconductor device, and particularly provides an enhancement mode MIS gate-controlled power device with a P-type gate to overcome the defects of a Fin-gate device, such as a narrow Fin width, high process difficulty, and low threshold voltage. In a wide-bandgap or super-wide-bandgap power semiconductor device with a Fin-gate structure, the application first uses a P-type wide-bandgap semiconductor region as a gate conductor, uses the characteristic that the work function of the P-type wide-bandgap semiconductor is much higher than that of metal, deeply depletes the semiconductor region between two gates, and improves the electron potential barrier of the channel region, so that a high threshold voltage is obtained. Moreover, based on the structure, the width of the Fin can be wider than that of a traditional structure, so that the process difficulty is reduced and the manufacturing cost is reduced. Finally, the enhancement mode MIS gate-controlled power device with the P-type gate has the advantages of high threshold voltage, high breakdown voltage, large Fin width, simple preparation process, and low cost.

Description

Technical Field

[0001] This invention belongs to the field of power semiconductor technology and relates to high voltage semiconductor devices. Specifically, it provides an enhanced wide-bandgap or ultra-wide-bandgap semiconductor power device with a P-type gate. Background Technology

[0002] Wide and ultra-wide bandgap semiconductor devices are well-suited for high-frequency and high-power applications due to their inherent physical properties. Enhanced MIS gate-controlled devices have extremely low gate leakage current and can eliminate the need for protection circuits and improve system reliability in power electronics applications, making them a key area of ​​research.

[0003] However, traditional enhancement-mode MIS devices require a P-type base region to achieve reverse blocking and provide an inversion layer for the channel. For common SiC devices, the fabrication of the P-type base region is relatively mature, but the electron mobility of the SiC inversion layer is low, resulting in a higher specific on-resistance. For wide-bandgap and ultra-wide-bandgap semiconductors such as GaN, Ga2O3, and diamond, it remains difficult to fabricate P-type doping, or the P-type doping concentration is uncontrollable, thus preventing the fabrication of conventional inversion-channel conductive MIS gate-controlled devices. To address this issue, one existing solution is to use a Fin-gate structure. This structure makes the distance between the two gates (the width of the Fin) very small, typically on the order of 100 nm (otherwise, the threshold voltage and breakdown voltage would be very low). It utilizes the work function difference between the metal gate and the semiconductor to deplete the semiconductor between the gates to achieve enhancement-mode functionality. However, limited by the metal work function, the threshold voltage of this type of device is low, making it unsuitable for power electronic systems. Furthermore, because the Fin width is on the order of 100 nm, etching and metal via creation are difficult, leading to high fabrication costs. Summary of the Invention

[0004] The purpose of this invention is to address the shortcomings of existing Fin-gate devices, such as narrow Fin width, high manufacturing difficulty, and low threshold voltage, by providing an enhanced MIS gate-controlled power device with a P-type gate. Specifically, it is a Fin-gate wide-bandgap or ultra-wide-bandgap power semiconductor device with a gate conductor made of P-type wide-bandgap semiconductor, which has advantages such as high threshold voltage, large Fin width, and simple manufacturing process.

[0005] To achieve the above objectives, the technical solution adopted by the present invention is as follows:

[0006] An enhancement-mode MIS gate-controlled power device with a P-type gate includes: an N-type heavily doped substrate 1 made of a first-type semiconductor, an N-type buffer layer 2 made of a first-type semiconductor, an N-type withstand voltage layer 3 made of a first-type semiconductor, an N-type heavily doped region 4 made of a first-type semiconductor, a gate dielectric layer 5, a P-type wide bandgap semiconductor region 6, a source metal electrode 7, an N-type channel region 8 made of a first-type semiconductor, a gate metal electrode 9, and a drain metal electrode 12.

[0007] The feature is that the drain metal 12 electrode is disposed under an N-type heavily doped substrate, the N-type buffer layer 2 is disposed on the N-type heavily doped substrate, the N-type withstand voltage layer 3 is disposed on the N-type buffer layer, the N-type channel region 8 is disposed on the N-type withstand voltage layer, the N-type heavily doped source region 4 is disposed on the N-type channel region, and the source metal electrode 7 is disposed on the N-type heavily doped source region; two deep trenches are symmetrically disposed in the N-type channel region and the N-type heavily doped source region, respectively located on both sides of the source metal electrode 7; the gate dielectric layer 5 is disposed on the trench wall of the deep trench; the P-type wide bandgap semiconductor region 6 is filled in the deep trench, and the gate metal electrode 9 is disposed on the P-type wide bandgap semiconductor region.

[0008] Furthermore, the deep trench penetrates the N-type channel region 8, causing the lower surface of the gate dielectric layer 5 to come into contact with the N-type pressure-resistant layer 3.

[0009] Furthermore, the enhanced MIS gate-controlled power device with a P-type gate further includes: two P-type semiconductor regions 10 and an N-type semiconductor region 11 made of a first type semiconductor disposed between the two P-type semiconductor regions. The P-type semiconductor regions 10 and N-type semiconductor regions 11 are disposed in the N-type withstand voltage layer 3. The P-type semiconductor region 10 is located under the gate dielectric layer 5 and is electrically connected to the source metal electrode 7.

[0010] Furthermore, the doping concentration of the N-type semiconductor region 11 is greater than that of the N-type withstand voltage layer 3;

[0011] Furthermore, the P-type semiconductor region 10 is made of the same material as the first type of semiconductor.

[0012] Furthermore, the P-type semiconductor region 10 is made of a different material from the first type of semiconductor, such as p-NiO, p-CuO, p-GaN, p-AlGaN, or p-PolySilicon. In addition, the P-type semiconductor region and the N-type withstand voltage layer 3 form a heterojunction diode with a low turn-on voltage.

[0013] Furthermore, the P-type wide bandgap semiconductor region is made of a semiconductor material with a work function greater than 6 eV, such as the common p-GaN or p-AlGaN.

[0014] Furthermore, the first type of semiconductor is a wide-bandgap or ultra-wide-bandgap semiconductor such as SiC, GaN, AlGaN, AlN, Ga2O3, or diamond.

[0015] Furthermore, the doping concentration of the N-type channel region 8 is not higher than that of the N-type breakdown voltage region 3.

[0016] The effective effects of this invention are as follows:

[0017] This invention provides an enhancement-mode MIS gate-controlled power device with a P-type gate. In the Fin-gate structure, the gate conductor is fabricated for the first time using a P-type wide bandgap semiconductor. Taking advantage of the fact that the work function of the P-type wide bandgap semiconductor is much higher than that of metal, the semiconductor region between the two gates is deeply depleted, increasing the electron barrier in the channel region, thereby obtaining a high threshold voltage and a high breakdown voltage. Furthermore, based on the above structure, the width of the Fin is wider than that of the conventional structure, thereby reducing the process difficulty and manufacturing cost. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a cell of an enhanced MIS gate-controlled power device with a P-type gate in Embodiment 1 of the present invention.

[0019] Figure 2 This is the transfer characteristic curve of the enhanced MIS gate-controlled power device with a P-type gate in Embodiment 1 of the present invention.

[0020] Figure 3 This is a schematic diagram of a cell of an enhanced MIS gate-controlled power device with a P-type gate in Embodiment 2 of the present invention.

[0021] Figure 4 This is a schematic diagram of a cell of an enhanced MIS gate-controlled power device with a P-type gate in Embodiment 3 of the present invention. Detailed Implementation

[0022] To make the objectives, technical solutions, and technical effects of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are some embodiments of the present invention, but not all embodiments.

[0023] Example 1

[0024] This embodiment provides an enhanced MIS gate-controlled power device with a P-type gate, the structure of which is as follows: Figure 1 As shown, it includes: an N-type heavily doped substrate 1, an N-type buffer layer 2, an N-type withstand voltage layer 3, an N-type heavily doped region 4, a gate dielectric layer 5, a P-type wide bandgap semiconductor region 6, a source metal electrode 7, an N-type channel region 8, a gate metal electrode 9, and a drain metal electrode 12; wherein,

[0025] The drain metal 12 electrode is disposed under an N-type heavily doped substrate, the N-type buffer layer 2 is disposed on the N-type heavily doped substrate, the N-type withstand voltage layer 3 is disposed on the N-type buffer layer, the N-type channel region 8 is disposed on the N-type withstand voltage layer, the N-type heavily doped source region 4 is disposed on the N-type channel region, and the source metal electrode 7 is disposed on the N-type heavily doped source region. Two deep trenches are symmetrically disposed in the N-type channel region and the N-type heavily doped source region, respectively located on both sides of the source metal electrode 7. The gate dielectric layer 5 is disposed on the trench wall of the deep trench. The P-type wide bandgap semiconductor region 6 is filled in the deep trench, and the gate metal electrode 9 is disposed on the P-type wide bandgap semiconductor region.

[0026] In terms of working principle: Since the Fermi level of a P-type wide bandgap semiconductor is located in the valence band, by selecting a wide bandgap semiconductor, its work function is much higher than that of metals (a P-type semiconductor work function ≥6eV is preferred); for example, the p-GaN used in the embodiment has a work function of about 7.4eV, which is 2.3eV higher than the 5.1eV of the common high work function metal Ni / Au; therefore, the gate conductor made using such a P-type wide bandgap semiconductor can form a larger work function difference with the channel semiconductor, thereby forming a higher electronic barrier in the channel region, obtaining a higher threshold voltage, significantly suppressing the (leakage) barrier reduction effect, changing the device from traditional soft breakdown to avalanche breakdown, and significantly improving its breakdown voltage.

[0027] Furthermore, in this embodiment, in the enhancement-mode MIS gate-controlled power device with a P-type gate, the N-type heavily doped substrate is doped with 1e19cm. -3 The Ga2O3, wherein the N-type buffer layer is 0.5 μm doped with 5e18 cm⁻¹ -3 The Ga2O3, wherein the N-type withstand layer is a 9.5 μm thick doped 2e16cm⁻¹ layer. -3 The Ga2O3, wherein the N-type channel layer is a doped 1e16cm layer with a thickness of 2μm and a width of 0.5μm. -3 The Ga2O3 contains an N-type channel layer located below the deep trench with a thickness of 0.5 μm, and the heavily doped N-type region is a 0.5 μm thick doped 1e19cm layer. -3 The gate dielectric layer is 30 nm Al2O3, and the p-type wide bandgap semiconductor region is doped with 8e19 cm⁻¹. -3 The negative charge at the interface between p-GaN, Al2O3 (gate dielectric layer), and channel layer is 1e11cm. -2 .

[0028] like Figure 2The figure shows the simulated transfer characteristic curves of the Fin-gate devices constructed by this embodiment and the conventional metal gate at the same size. As can be seen from the figure, the present invention achieves a threshold voltage of 2.7V with a Fin width of 0.5μm, while the conventional structure only has a threshold voltage of ~0.6V. More importantly, with a Fin width of 0.5μm, the conventional structure experiences soft breakdown due to the low electronic barrier in the channel region and severe drain-induced barrier reduction effect, with a breakdown voltage of only 46V. However, the present invention can significantly increase the electronic barrier height in the channel, and even with a Fin width of 0.5μm, the drain-induced barrier reduction is not significant, thus ensuring the occurrence of avalanche breakdown, with a breakdown voltage as high as about 4500V (breakdown electric field of 8MV / cm).

[0029] It should be noted that the materials, doping concentration, length, and thickness exemplified in this embodiment do not limit the scope of protection of this invention. These parameters can be adaptively optimized according to the needs of the application.

[0030] Example 2

[0031] Based on the gate structure of Embodiment 1, this embodiment provides an enhanced MIS gate-controlled power device with a P-type gate, the structure of which is as follows: Figure 3 As shown, the only difference between it and Example 1 is that the deep trench penetrates the N-type channel region 8, that is, the lower surface of the gate dielectric layer 5 is in contact with the N-type pressure-resistant layer 3.

[0032] In terms of working principle: the MIS gate section in this embodiment is the same as that in embodiment 1, the gate control principle is similar to that in embodiment 1, and its transfer characteristic curve is also similar to that in embodiment 1, with the same characteristics and beneficial effects.

[0033] Example 3

[0034] Based on the gate structure of Embodiment 1, this embodiment provides an enhanced MIS gate-controlled power device with a P-type gate, the structure of which is as follows: Figure 4 As shown, based on Embodiment 2, in order to prevent the gate dielectric layer from breaking down prematurely or generating large leakage current under high electric field, two P-type semiconductor regions 10 are respectively set below the gate dielectric layer. The P-type semiconductor regions form a good electric field shielding effect on the gate dielectric, reducing the electric field of the dielectric layer and thus preventing premature breakdown of the dielectric. In actual fabrication, the P-type semiconductor region needs to be electrically connected to the source metal electrode 7 through three-dimensional design, so as to replenish the holes drained when the P-type semiconductor region is depleted and avoid a significant increase in dynamic resistance during switching. At the same time, in order to reduce the JFET resistance introduced by the P-type semiconductor region (electric field shielding region), an N-type semiconductor region 11 is set between the two P-type semiconductor regions 10. The N-type semiconductor region 11 and the N-type withstand voltage region 3 are made of the same material, and the doping concentration is greater than that of the N-type withstand voltage region.

[0035] Furthermore, the structure and materials of this embodiment are the same as those of Embodiment 1. The P-type electric field shielding region 10 can be made of the same material as the withstand voltage layer 3 (i.e., Ga2O3), or other semiconductor materials such as p-NiO, p-CuO, p-GaN, p-AlGaN, p-PolySilicon, etc., to form a heterojunction diode with a low turn-on voltage, which is beneficial to reduce conduction loss during reverse conduction.

[0036] In terms of working principle: the MIS gate section in this embodiment is the same as that in embodiment 1, the gate control principle is similar to that in embodiment 1, and its transfer characteristic curve is also similar to that in embodiment 1, with the same characteristics and beneficial effects.

[0037] The above description is merely a specific embodiment of the present invention. Any feature disclosed in this specification may be replaced by other equivalent or similar features unless otherwise specified. All disclosed features, or steps in all methods or processes, may be combined in any way except for mutually exclusive features and / or steps.

Claims

1. An enhancement-mode MIS gate-controlled power device with a P-type gate, comprising: The structure comprises an N-type heavily doped substrate (1), an N-type buffer layer (2), an N-type withstand voltage layer (3), an N-type heavily doped region (4), an N-type channel region (8), a gate dielectric layer (5), a P-type wide bandgap semiconductor region (6), a source metal electrode (7), a gate metal electrode (9), and a drain metal electrode (12). The N-type heavily doped substrate, N-type buffer layer, N-type withstand voltage layer, N-type heavily doped region, and N-type channel region are made of type I semiconductors. The features are as follows: the drain metal (12) electrode is disposed under an N-type heavily doped substrate; the N-type buffer layer (2) is disposed on an N-type heavily doped substrate; the N-type withstand voltage layer (3) is disposed on an N-type buffer layer; the N-type channel region (8) is disposed on an N-type withstand voltage layer; the N-type heavily doped region (4) is disposed on an N-type channel region; and the source metal electrode (7) is disposed on an N-type heavily doped region. Two deep trenches are symmetrically disposed in the N-type channel region and the N-type heavily doped region, and are respectively located on both sides of the source metal electrode (7). The gate dielectric layer (5) is disposed on the trench wall of the deep trench. The P-type wide bandgap semiconductor region (6) is filled in the deep trench, and a gate metal electrode (9) is disposed on the P-type wide bandgap semiconductor region. The deep trench penetrates the N-type channel region (8), so that the lower surface of the gate dielectric layer (5) comes into contact with the N-type pressure-resistant layer (3); The enhanced MIS gate-controlled power device with a P-type gate further includes: two P-type semiconductor regions (10) and an N-type semiconductor region (11) disposed between the two P-type semiconductor regions. The P-type semiconductor region and the N-type semiconductor region are disposed in an N-type withstand voltage layer (3). The P-type semiconductor region is located under the gate dielectric layer (5) and is electrically connected to the source metal electrode (7). The N-type semiconductor region is made of a first type of semiconductor.

2. The enhancement-mode MIS gate-controlled power device with a P-type gate according to claim 1, characterized in that, The P-type semiconductor region (10) is made of the same material as the first type of semiconductor.

3. The enhancement-mode MIS gate-controlled power device with a P-type gate according to claim 1, characterized in that, The P-type semiconductor region (10) is p-NiO, p-CuO, p-GaN, p-AlGaN or p-PolySilicon, and the P-type semiconductor region and the N-type withstand voltage layer (3) form a heterojunction diode with a low turn-on voltage.

4. The enhancement-mode MIS gate-controlled power device with a P-type gate according to claim 1, characterized in that, The doping concentration of the N-type semiconductor region (11) is greater than that of the N-type withstand layer (3).

5. The enhanced MIS gate-controlled power device with a P-type gate according to claim 1, characterized in that, The P-type wide bandgap semiconductor region is made of semiconductor material with a work function greater than 6 eV.

6. The enhancement-mode MIS gate-controlled power device with a P-type gate according to claim 1, characterized in that, The first type of semiconductor is SiC, GaN, AlGaN, AlN, Ga2O3, or diamond.

7. The enhancement-mode MIS gate-controlled power device with a P-type gate according to claim 1, characterized in that, The doping concentration of the N-type channel region (8) is not higher than that of the N-type breakdown voltage region (3).

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