Highly reliable power device and method of making the same

Abstract

The application relates to a high-reliability power device and a preparation method thereof. The device comprises a substrate, a second-conductivity-type base region prepared on both sides of each cell trench and a source contact hole connecting structure based on a ballast structure for any cell, the source contact hole connecting structure comprising a first-conductivity-type source region, a contact hole and a second-conductivity-type contact region, the second-conductivity-type contact region being located in the second-conductivity-type base region, a second-conductivity-type contact compensation part being arranged on the side wall of the contact hole corresponding to the joint part of the second-conductivity-type contact region and the first-conductivity-type source region, and the compensation part compensating the ohmic contact area of the source metal and the second-conductivity-type contact region in the ballast structure after the source metal is filled in the contact hole in the source contact hole connecting structure. The application can improve the reliability of the formed ballast structure under reverse voltage.

Description

Technical Field

[0001] The present invention relates to a power device and a preparation method thereof, in particular to a high-reliability power device and a preparation method thereof. Background Art

[0002] At present, commonly used power devices include MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) devices and IGBT (Insulated Gate Bipolar Transistor) devices. Among them, MOSFET devices have become the mainstream in the field of medium and low voltage power applications. They are mainly used in high-end fields such as industrial electronics, automotive electronics and high-performance computing. As a key component of DC brushless motor drive, UPS (Uninterruptible Power Supply), power battery, CPU (central processing unit) / GPU (graphics processing unit) / MCU (Microcontroller Unit) drive, its reliability is particularly important.

[0003] like Figure 1 As shown in the figure, a typical structure of a traditional N-type trench MOSFET device is shown. The trench MOSFET device includes a gate electrode, a source electrode, and a drain electrode. A voltage is applied to the gate electrode and the source electrode. When this voltage is greater than the threshold voltage, an inversion layer is formed along the P-well region of the cell trench, and the N++ source region and the N-drift region form a conductive channel. When a bias voltage is applied between the drain electrode and the source electrode, current flows through the source electrode and the drain electrode.

[0004] Figure 2 A typical structure of cell arrangement in a trench MOSFET device is shown in FIG. Figure 2 In the diagram, TRH is used to indicate a cell trench in a cell, and a contact hole is set on each side of the cell trench. The contact holes are parallel to the cell trench and arranged in a straight line.

[0005] When preparing the contact hole, the insulating dielectric layer (ILD) is used as an etch mask to perform trench etching, etching through the N++ source region (etching depth is approximately 0.5μm). At this point, the contact hole is formed. To form the contact area, boron ion implantation and annealing are performed after etching the contact hole to form a P+ contact region directly corresponding to the contact hole.

[0006] In order to form a ballast structure and improve the short-circuit current capability of power devices, Figure 3 An example of contact hole arrangement on both sides of a cell trench is shown. Figure 3As can be seen from the arrangement of the contact holes shown, compared with the conventional arrangement, the contact hole on one side of the cell trench is divided into two parts by the N++ source region.

[0007] right Figure 3 The contact hole arrangement example shown in Figure 4 Middle along Figure 3 The schematic diagram of the cross section is shown in the dotted line. Figure 4 It can be seen from the figure that after the contact hole on one side of the cell trench is separated by the N++ source region, the area of ​​the P+ contact region is reduced. That is, the contact area between the P+ contact region and the source metal used to form the source electrode is reduced, resulting in a decrease in the contact reliability between the source metal and the P+ contact region, which will eventually affect the reliability of the power device. Summary of the Invention

[0008] The purpose of the present invention is to overcome the deficiencies in the prior art and provide a high-reliability power device and a preparation method thereof, which can improve the reliability of the formed ballast structure during reverse withstand voltage.

[0009] According to the technical solution provided by the present invention, the high-reliability power device includes:

[0010] A substrate of a first conductivity type, wherein an active region is formed in a central region of a front surface of the substrate;

[0011] An active area includes a plurality of cells distributed in parallel, wherein the cells adopt a trench structure. For each cell, the cell includes at least one cell trench. A second conductive type base region and a source contact hole connection structure based on a ballast structure are prepared on both sides of each cell trench. The second conductive type base region contacts the outer sidewall of the cell trench.

[0012] A source contact hole connection structure, comprising a first conductivity type source region adapted to a second conductivity type base region, a plurality of contact holes spaced apart by the first conductivity type source region, and a second conductivity type contact region corresponding one-to-one to the contact holes, wherein the second conductivity type contact region is located within the second conductivity type base region, and a second conductivity type contact compensation portion is provided on a sidewall of the contact hole corresponding to a junction between the second conductivity type contact region and the first conductivity type source region;

[0013] After the source metal is filled in the contact hole in the source contact hole connection structure, the ohmic contact between the source metal and the second conductive type contact compensation portion in the filled contact hole is utilized to compensate for the ohmic contact area between the source metal and the second conductive type contact region in the ballast structure.

[0014] The cell groove is in the shape of an elongated strip;

[0015] In the source contact hole connection structure based on the ballast structure, the first conductive type source region includes a first conductive type contact region and a first conductive type separation region interconnected with the first conductive type contact region, wherein:

[0016] The first conductive type contact region contacts the outer sidewall of the adjacent cell trench, and the first conductive type contact region is distributed along the length of the cell trench;

[0017] The first conductive type separation region is located outside the first conductive type contact region, and the contact holes are separated by the first conductive type separation region.

[0018] The second conductive type contact compensation portion and the second conductive type contact region correspond to the junction portion of the first conductive type separation region;

[0019] The second conductive type contact compensation portion includes a second conductive type vertical compensation area or a second conductive type compensation step area, wherein:

[0020] The second conductive type vertical compensation region is located below the first conductive type separation region;

[0021] The second conductive type compensation step region includes a plurality of compensation steps, and the compensation steps are located outside the first conductive type separation region.

[0022] When the second conductive type contact compensation portion is a second conductive type vertical compensation region, the second conductive type vertical compensation region and the second conductive type contact region are formed by the same ion implantation process step, wherein:

[0023] During ion implantation, an inclined implantation method is adopted to prepare a required second conductive type vertical compensation region at the junction of the second conductive type contact region and the first conductive type separation region.

[0024] When the second conductive type contact compensation portion is a second conductive type compensation step region, a required compensation step is prepared, and after the compensation step is prepared, ion implantation is performed to simultaneously form the second conductive type contact region and the second conductive type compensation step region.

[0025] When preparing the compensation step, the first conductive type separation region body forming the first conductive type separation region and the insulating dielectric layer body forming the insulating dielectric layer are selectively etched, and the contact hole is etched using the etched insulating dielectric layer body as a mask to form a contact hole having a compensation step after etching; and

[0026] A first conductive type separation region and an insulating dielectric layer located above the first conductive type separation region are formed.

[0027] For any cellular trench, the cellular trench penetrates the second conductive type base region, and the bottom of the cellular trench is located below the second conductive type base region;

[0028] The cell trench is filled with gate conductive polysilicon, which is insulated and isolated from the cell trench by an insulating oxide layer covering the inner sidewalls and bottom wall of the cell trench, and the gate conductive polysilicon is insulated and isolated from the source metal.

[0029] A back electrode structure is provided on the back side of the substrate, and the back electrode structure cooperates with the active area of ​​the substrate so that the power device is a MOSFET type device or an IGBT type device.

[0030] A method for preparing a high-reliability power device, used for preparing the power device, the method comprising:

[0031] Providing a substrate of a first conductivity type, and preparing an active region in a central region of a front surface of the substrate;

[0032] The prepared active area includes a plurality of cells distributed in parallel, wherein the cells adopt a trench structure. For any cell, the cell includes at least one cell trench. A second conductive type base region and a source contact hole connection structure based on a ballast structure are prepared on both sides of each cell trench. The second conductive type base region contacts the outer sidewall of the cell trench.

[0033] A source contact hole connection structure includes a first conductivity type source region adapted to a second conductivity type base region, a plurality of contact holes separated by the first conductivity type source region, and a second conductivity type contact region corresponding one-to-one to the contact holes, wherein the second conductivity type contact region is located within the second conductivity type base region, and a second conductivity type contact compensation portion is provided on a sidewall of the contact hole corresponding to a junction between the second conductivity type contact region and the first conductivity type source region;

[0034] After the source metal is filled in the contact hole in the source contact hole connection structure, the ohmic contact between the source metal and the second conductive type contact compensation portion in the filled contact hole is utilized to compensate for the ohmic contact area between the source metal and the second conductive type contact region in the ballast structure.

[0035] The doping concentration of the second conductive type contact compensation portion is consistent with the doping concentration of the second conductive type contact region, and the doping concentration of the second conductive type contact compensation portion is greater than the doping concentration of the second conductive type base region.

[0036] Among the “first conductivity type” and “second conductivity type”, for N-type power semiconductor devices, the first conductivity type refers to N-type and the second conductivity type is P-type; for P-type power semiconductor devices, the types referred to by the first conductivity type and the second conductivity type are exactly opposite to those of N-type power semiconductor devices.

[0037] The advantages of the present invention are as follows: the cells in the active area adopt a trench structure, a second conductive type base region and a source contact hole connection structure based on a ballast structure are prepared on both sides of each cell trench, and a second conductive type contact compensation portion is provided on the side wall of the contact hole corresponding to the junction of the second conductive type contact region and the first conductive type source region; after the source metal is filled in the contact hole in the source contact hole connection structure, the ohmic contact between the source metal and the second conductive type contact compensation portion in the filled contact hole is utilized to compensate for the ohmic contact area between the source metal and the second conductive type contact region in the ballast structure, thereby effectively improving the reliability during reverse withstand voltage, being compatible with existing processes, and being safe and reliable. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 Schematic diagram of an existing N-type trench MOSFET device.

[0039] Figure 2 Schematic diagram of the relationship between the existing cell trench, P+ contact area and contact hole.

[0040] Figure 3 Schematic diagram of the relationship between cell trenches, P+ contact areas, and contact holes based on the ballast structure.

[0041] Figure 4 Schematic diagram of forming P+ contact region and contact hole by ion implantation.

[0042] Figure 5 This is a schematic diagram of forming a P+ vertical compensation region using tilted implantation in the present invention.

[0043] Figure 6 Schematic diagram of a P+ compensation step region in a contact hole of the present invention.

[0044] Figures 7 to 13 This is a process step diagram of an embodiment of the present invention for forming a P+ compensation step region, wherein:

[0045] Figure 7 This is a cross-sectional view of the insulating dielectric base layer obtained in the present invention.

[0046] Figure 8 This is a cross-sectional view of the first base layer of the insulating medium obtained in the present invention.

[0047] Figure 9This is a cross-sectional view of the second base layer of the insulating medium obtained in the present invention.

[0048] Figure 10 This is a cross-sectional view of the present invention after etching the second base layer of the insulating medium.

[0049] Figure 11 This is a cross-sectional view of the third base layer of the insulating medium obtained in the present invention.

[0050] Figure 12 This is a schematic diagram of an embodiment of the present invention in which a compensation step is obtained by etching the third base layer of the insulating medium.

[0051] Figure 13 This is a schematic diagram of the P+ contact area and the P+ compensation step area prepared in the present invention.

[0052] Explanation of the accompanying symbols: 1-N-type epitaxial layer, 2-N+ substrate, 3-back metal layer, 4-P-type base region, 5-cell trench, 6-gate conductive polysilicon, 7-insulating oxide layer, 8-P+ contact region, 9-source metal, 10-insulating dielectric layer, 11-N++ source region, 12-contact hole, 13-P+ vertical compensation region, 14-P+ compensation step region, 15-N++ separation region body, 16-insulating dielectric body layer, 17-contact hole first window, 18-insulating dielectric first base layer, 19-N++ separation first base layer, 20-insulating dielectric second base layer, 21-N++ separation second base layer, 22-insulating dielectric third base layer, 23-N++ contact region, 24-N++ separation region. DETAILED DESCRIPTION

[0053] The present invention will be further described below with reference to specific drawings and embodiments.

[0054] The formed ballast structure can improve the reliability of reverse withstand voltage. For high-reliability power devices, in one embodiment of the present invention, taking an N-type power device as an example, the present invention includes:

[0055] A substrate of N conductive type, wherein an active region is formed in a central region of a front surface of the substrate;

[0056] The active area includes a plurality of cells distributed in parallel, wherein the cells adopt a trench structure. For each cell, the cell includes at least one cell trench 5. A P-type base region 4 and a source contact hole connection structure based on a ballast structure are prepared on both sides of each cell trench 5. The P-type base region 4 contacts the outer sidewall of the cell trench 5.

[0057] A source contact hole connection structure includes an N++ source region 11 adapted to the P-type base region 4, a plurality of contact holes 12 separated by the N++ source regions 11, and a P+ contact region 8 corresponding one-to-one with the contact holes 12, wherein the P+ contact region 8 is located within the P-type base region 4, and a P+ contact compensation portion is provided on the sidewall of the contact hole 12 corresponding to the junction of the P+ contact region 8 and the N++ source region 11;

[0058] After the source metal 9 is filled in the contact hole 12 in the source contact hole connection structure, the ohmic contact between the source metal 9 and the P+ contact compensation portion in the filled contact hole 12 is utilized to compensate for the ohmic contact area between the source metal 9 and the P+ contact region 8 in the ballast structure.

[0059] For power devices, the substrate can be made of commonly used existing substrate materials, such as silicon. The substrate material can be selected based on actual needs and is determined by meeting actual requirements. Generally, the substrate has a front side and a back side corresponding to the front side. The active area is prepared in the center of the front side of the substrate. A terminal protection zone is generally also prepared on the front side of the substrate to match the active area. The terminal protection zone can protect the active area and surrounds the active area. The coordination relationship between the terminal protection zone and the active area is consistent with existing ones.

[0060] Figure 1 , a typical structure of the substrate is shown, that is, the substrate generally includes an N+ substrate 2 and an N-type epitaxial layer 1 located on the N+ substrate 2. The doping concentration of the N-type epitaxial layer 1 is generally lower than the doping concentration of the N+ substrate 2. The surface of the N-type epitaxial layer 1 forms the front side of the substrate, and the corresponding surface of the N+ substrate 2 forms the back side of the substrate.

[0061] The active area of ​​the power device specifically includes several cells distributed in parallel. In one embodiment of the present invention, the cell adopts a groove structure. Therefore, a cell includes at least one cell groove 5. The number of cell grooves 5 can be selected according to actual needs to meet the actual scenario. Figure 1 FIG. 3 shows a case where a cell includes a cell groove 5 .

[0062] For cells with a trench structure, a P-type base region 4 and a ballast-structured source contact hole connection structure are prepared on both sides of each cell trench 5. The P-type base region 4 is prepared in the N-type epitaxial layer 1 and needs to contact the outer sidewalls of the cell trench 5. The ballast-structured source contact hole connection structure mainly realizes ohmic contact between the source metal 9 and the P+ contact region 8 in the P-type base region 4.

[0063] Based on the characteristics of the ballast structure, it can be seen that the source contact hole connection structure generally includes an N++ source region 11 that is compatible with the P-type base region 4, a plurality of contact holes 12 separated by the N++ source region 11, and a P+ contact region 8 that corresponds one-to-one with the contact holes 12. Among them, the N++ source region 11 is compatible with the P-type base region 4, specifically referring to the N++ source region 11 being prepared within the P-type base region 4. On one side of the cell trench 5, based on the ballast structure, multiple contact holes 12 are separated by the N++ source region 11. The specific spacing is based on the formation of the ballast structure. At the bottom of each contact hole 12, there is a corresponding P+ contact region 8, so that when the source metal 9 is filled in the contact hole 12, the source metal 9 can make ohmic contact with the P+ contact region 8 and the N++ source region 11.

[0064] Depend on Figure 2 、 Figure 3 As can be seen from the above description, in the ballasted structure, since the N++ source region 11 separates the contact hole 12 , the contact area between the source metal 9 and the P+ contact region 8 is reduced, and the reliability during reverse withstand voltage is reduced.

[0065] In one embodiment of the present invention, a P+ contact compensation portion is provided on the sidewall of a contact hole 12 corresponding to the junction of a P+ contact region 8 and an N++ source region 11. For a contact hole 12 having a P+ contact compensation portion, after source metal 9 is filled into the contact hole 12 within the source contact hole connection structure, ohmic contact is established between the source metal 9 and the P+ contact compensation portion within the filled contact hole 12 to compensate for the ohmic contact area between the source metal 9 and the P+ contact region 8 in the ballast structure. Specifically, compensating for the ohmic contact area between the source metal 9 and the P+ contact region 8 in the ballast structure refers to increasing the ohmic contact area between the source metal 9 and the P+ conductive region relative to existing ballast structures, thereby improving reliability during reverse withstand voltage.

[0066] In addition, the contact area compensated by the P+ contact compensation portion can be specifically set or selected according to the configuration of the P+ contact compensation portion and actual needs, so as to meet actual application needs.

[0067] In one embodiment of the present invention, the cell groove 5 is in the shape of an elongated strip;

[0068] In the source contact hole connection structure based on the ballast structure, the N++ source region 11 includes an N++ contact region 23 and an N++ separation region 24 interconnected with the N++ contact region 23, wherein:

[0069] The N++ contact region 23 contacts the outer sidewall of the adjacent cell trench 5 , and the N++ contact region 23 is distributed along the length of the cell trench 5 ;

[0070] The N++ separation region 24 is located outside the N++ contact region 23 , and the contact hole 12 is separated by the N++ separation region 24 .

[0071] Figure 2 and Figure 3 FIG. 1 shows an embodiment in which the cell trench 5 is in the shape of a long strip. As can be seen from the figure, contact holes 12 and P+ contact regions 8 are provided on both sides of the cell trench 5. Figure 2 and Figure 3 In the figure, the P+ contact region 8 corresponds to the contact hole 12 . Figure 3 FIG. 2 shows an embodiment of the N++ source region 11 based on the ballast structure. In this case, the N++ source region 11 includes an N++ contact region 23 and an N++ separation region 24. Generally, the N++ contact region 23 and the N++ separation region 24 can be prepared by a one-step process.

[0072] The N++ contact region 23 is in contact with the outer sidewall of the cell trench 5 , and the N++ separation region 24 is used to separate the contact hole 12 . Figure 3 In the embodiment, when the cell trench 5 is elongated, the N++ contact region 23 located on one side of the cell trench 5 contacts the adjacent outer sidewall. In this case, the N++ contact region 23 needs to be distributed along the length of the cell trench 5. The N++ separation region 24 is located on either side of the cell trench 5, specifically to separate the contact hole 5 on the outer side of the cell trench 5. In a specific implementation, the number of N++ separation regions 24 can be selected according to actual needs.

[0073] Figure 2 In the embodiment, since it is not based on the ballast structure, a contact hole 12 is provided on one side of the cell trench 5. Figure 3 In the ballast structure, there are multiple contact holes 12. Figure 2 compared to, Figure 3 In the embodiment, due to the presence of the N++ separation region 24, the reduction in the contact area between the source metal 9 and the P+ contact region 8 is related to the number of the existing N++ separation regions 24. In one embodiment of the present invention, the reduced contact area can be compensated by using a P+ contact compensation portion.

[0074] In one embodiment of the present invention, for any cell trench 5 , the cell trench 5 penetrates the P-type base region 4 , and the bottom of the cell trench 5 is located below the P-type base region 4 ;

[0075] The cell trench 5 is filled with gate conductive polysilicon 6 , which is insulated from the cell trench 5 by an insulating oxide layer 7 covering the inner sidewalls and bottom wall of the cell trench 5 . The gate conductive polysilicon 6 is also insulated from the source metal 9 .

[0076] Typically, the cell trench 5 penetrates the P-type base region 4, and the bottom of the cell trench 5 is located within the N-type epitaxial layer 1. A gate conductive polysilicon 6 is filled within the cell trench 5, and an insulating oxide layer 7 is provided on the inner sidewalls and bottom wall of the cell trench 5. After the gate conductive polysilicon 6 is filled, the insulating oxide layer 7 provides insulation isolation from the inner sidewalls and bottom wall of the cell trench 5. The gate conductive polysilicon 6 is connected to the gate metal to form the gate electrode of the power device. The gate conductive polysilicon 6 is insulated and isolated from the source metal 9. Typically, the source metal 9 is used to form the source electrode of the power device. Figure 1 In the embodiment, the insulating dielectric layer 10 is used to cover the notch of the cell trench 5 . At this time, the gate conductive polysilicon 6 can be insulated and isolated from the source metal 9 by the insulating dielectric layer 10 .

[0077] In one embodiment of the present invention, the P+ contact compensation portion corresponds to the junction of the P+ contact region 8 and the N++ separation region 24;

[0078] The P+ contact compensation portion includes a P+ vertical compensation area 13 or a P+ compensation step area 14, wherein:

[0079] The P+ vertical compensation region 13 is located below the N++ separation region 24;

[0080] The P+ compensation step region 14 includes a plurality of compensation steps, which are located outside the N++ separation region 24 .

[0081] In the above description, a P+ contact compensation portion is provided on the sidewall of the contact hole 12 corresponding to the junction of the P+ contact region 8 and the N++ source region 11. When the N++ source region 11 includes the N++ contact region 23 and the N++ separation region 24, in one embodiment of the present invention, the P+ contact compensation portion corresponds to the junction of the P+ contact region 8 and the N++ separation region 24. Figure 5 and Figure 6 shown.

[0082] In specific implementation, the P+ contact compensation part can be a P+ vertical compensation area 13 or a P+ compensation step area 14. Of course, the P+ contact compensation part can also adopt other forms that can achieve contact surface compensation. It can be selected according to needs to meet the ohmic contact area compensation of the source metal 9.

[0083] Figure 5 FIG. 1 shows an embodiment in which the P+ contact compensation portion adopts a P+ vertical compensation region 13. Figure 5 In the embodiment, the P+ vertical compensation region 13 is located below the N++ separation region 24, and the P+ vertical compensation region 13 is connected to the N++ separation region 24 and the P+ contact region 8 respectively. At this time, the P+ vertical compensation region 13 is part of the sidewall of the contact hole 12. Figure 4Compared with the implementation in , the ohmic contact area of ​​the source metal 9 includes the ohmic contact area with the P+ contact area 8 and the ohmic contact area with the P+ vertical compensation area 13. At this time, the contact area between the source metal 9 and the P+ conductive area can be compensated by the P+ vertical compensation area 13.

[0084] In one embodiment of the present invention, when the P+ contact compensation portion is the P+ vertical compensation region 13, the P+ vertical compensation region 13 and the P+ contact region 8 are formed by the same ion implantation process step, wherein:

[0085] During ion implantation, an inclined implantation method is adopted to prepare the required P+ vertical compensation region 13 at the junction of the P+ contact region 8 and the N++ separation region 24 .

[0086] The P+ contact region 8 is generally formed by ion implantation. The specific type of implanted ions and process conditions can be selected according to the needs, so as to prepare the required P+ contact region 8. In order to reduce the process cost, when preparing the P+ contact region 8, the ion tilt implantation method can be used, so as to prepare the required P+ vertical compensation region 13 below the N++ separation region 24. The tilt implantation method is as follows: Figure 5 In specific implementation, the tilted implantation can be implemented by conventional technical means, specifically based on the ability to simultaneously prepare the P+ contact region 8 and the P+ vertical compensation region 13 .

[0087] Figure 6 FIG. 1 shows an embodiment in which the P+ contact compensation portion adopts a P+ compensation step region 14. Figure 6 In the embodiment, the P+ compensation step region 14 includes a plurality of compensation steps, which are located outside the N++ separation region 24. Specifically, the compensation steps are located outside the N++ separation region 24, which means that the compensation steps are located on the side of the N++ separation region 24 corresponding to the contact hole 24, so that a portion of the inner wall of the contact hole 24 can be formed by the compensation steps.

[0088] In one embodiment of the present invention, when the P+ contact compensation portion is a P+ compensation step region 14 , a required compensation step is prepared, and after the compensation step is prepared, ion implantation is performed to simultaneously form the P+ contact region 8 and the P+ compensation step region 14 .

[0089] For the P+ compensation step region 14, a compensation step is first prepared. After the desired compensation step is prepared, ion implantation is performed to simultaneously form the P+ contact region 8 and the P+ compensation step region 14. Figure 6 shown. Figure 6 During ion implantation, a non-tilted implantation method may be used. The specific implantation conditions and process may be selected as needed to form the desired P+ contact region 8 and P+ compensation step region 14.

[0090] As can be seen from the above description, the doping concentration of the P+ contact compensation portion is consistent with the doping concentration of the P+ contact region 8, and the doping concentration of the P+ contact compensation portion is greater than the doping concentration of the P-type base region 4. The corresponding doping concentration between the P+ contact region 8 and the P-type base region 4 can be selected according to actual needs.

[0091] In one embodiment of the present invention, when preparing the compensation step, the N++ partition region body 15 forming the N++ partition region 24 and the insulating dielectric layer body 16 forming the insulating dielectric layer 10 are selectively etched, and the etched insulating dielectric layer body is used as a mask to perform contact hole etching, so as to form the contact hole 12 having the compensation step after etching; and

[0092] An N++ separation region 24 and an insulating dielectric layer 10 located above the N++ separation region 24 are formed.

[0093] Figures 7 to 12 In FIG. , a process for preparing a compensation step is shown. Specifically,

[0094] Figure 7 In the embodiment, an N++ separation region 15 is formed on the P-type base region 4 by an ion implantation process; after the N++ separation region 15 is obtained, an insulating dielectric layer 16 is formed by PECVD (Plasma Enhanced Chemical Vapor Deposition) deposition.

[0095] Figure 8 In the process, the insulating dielectric layer 16 is selectively masked and etched to obtain an insulating dielectric first base layer 18. The obtained insulating dielectric first base layer 18 is used as a mask layer for etching the N++ separation region 15. The N++ separation region 15 is etched using a contact hole etching process to obtain an N++ separation first base layer 19 corresponding to the insulating dielectric first base layer 18.

[0096] The etched portion of the N++ separation region 15 forms a first contact hole window 17 . During etching, the etching depth is 100 nm to 150 nm, which is consistent with or slightly greater than the thickness of the N++ separation region 15 .

[0097] Figure 9 In the embodiment, the insulating dielectric first base layer 18 is selectively masked and etched so that after etching, the end of the insulating dielectric first base layer 18 adjacent to the first contact hole window 17 is retracted inward to form the insulating dielectric second base layer 20. The width of the inward retraction of the edge of the insulating dielectric layer first base layer 18 is about 200 nm.

[0098] Figure 10In the process, the insulating dielectric second base layer 20 is used as a mask, and the contact hole first window 17 is used for a second contact hole etching process. The etching depth is 100nm to 150nm, forming a first step. At this time, the N++ separation first base layer 19 is etched to become the N++ separation second base layer 21.

[0099] Figure 11 In the process, the insulating dielectric second base layer 20 is selectively masked and etched to form an insulating dielectric third base layer 22 . Compared with the insulating dielectric second base layer 20 , the side edges of the insulating dielectric second base layer 20 are further shrunk inward by a width of 200 nm.

[0100] Figure 12 In the process, the third contact hole etching process is performed with the third insulating dielectric base layer 22 as a mask. The etching depth can be 100 nm to 150 nm. After etching, a second step is formed.

[0101] When it comes to specific processes, Figure 6 and Figure 12 In FIG. , an embodiment in which the compensation step is two steps is shown. Therefore, Figure 12 After the process, the insulating dielectric third base layer 22 is used to form an insulating dielectric layer, and the N++ separation second base layer 21 is used to form an N++ separation region 24.

[0102] When the compensation step is a step of another desired number, the above process steps can be referred to for details, and the specific steps are subject to the preparation of the desired compensation step. After the compensation step is prepared, the P+ contact area 8 and the P+ compensation step area 14 can be formed by ion implantation. Figure 13 shown.

[0103] In one embodiment of the present invention, a back electrode structure is provided on the back side of the substrate, and the back electrode structure cooperates with the active area of ​​the substrate so that the power device is a MOSFET type device or an IGBT type device.

[0104] Figure 1 , an embodiment of a back electrode structure is shown, wherein the back electrode structure is a drain metal 3, which is in ohmic contact with the N++ substrate 2. In this case, the power device is a MOSFET. When an IGBT device is to be manufactured, only the corresponding back electrode structure needs to be prepared. The specific back electrode structure required to form an IGBT device shall prevail.

[0105] The above-mentioned power device can be prepared by the following process. Specifically, the preparation method includes:

[0106] Providing an N-type substrate and preparing an active area in the central area of ​​the front side of the substrate;

[0107] The prepared active area includes a plurality of cells distributed in parallel, wherein the cells adopt a trench structure. For any cell, the cell includes at least one cell trench 5. A P-type base region 4 and a source contact hole connection structure based on a ballast structure are prepared on both sides of each cell trench 5. The P-type base region 4 contacts the outer sidewall of the cell trench 5.

[0108] The source contact hole connection structure includes an N++ source region 11 adapted to the P-type base region 4, a plurality of contact holes 12 separated by the N++ source regions 11, and a P+ contact region 8 corresponding one to one with the contact holes 12, wherein the P+ contact region 8 is located within the P-type base region 4, and a P+ contact compensation portion is provided on the sidewall of the contact hole 12 corresponding to the junction of the P+ contact region 8 and the N++ source region 11;

[0109] After the source metal 9 is filled in the contact hole 12 in the source contact hole connection structure, the ohmic contact between the source metal 9 and the P+ contact compensation portion in the filled contact hole 12 is utilized to compensate for the ohmic contact area between the source metal 9 and the P+ contact region 8 in the ballast structure.

[0110] During fabrication, a substrate is required. For details on the substrate, refer to the above description. Generally, front-side processing is performed on the front side of the substrate, followed by back-side processing. During the front-side processing, the active area is fabricated in the center of the substrate; during the back-side processing, the back-side electrode structure is formed.

[0111] When preparing the active area, a P-type base region 4 and a cell trench 5 are generally prepared. An insulating oxide layer 7 is grown in the cell trench 5, and gate conductive polysilicon 6 is filled in. Thereafter, a process for forming a source contact hole connection structure based on a ballast structure is performed, during which a P+ contact compensation portion is formed. Depending on the method used for the P+ contact compensation portion, the above-mentioned specific process description can be referred to, with the formation of a P+ contact region 8 and a P+ contact compensation portion being the standard.

[0112] The above only describes a common process of power devices. In the above process, existing commonly used process conditions can be adopted, that is, the preparation process of the power device is compatible with the existing process. The specific process can be selected according to actual needs, so as to form the required cells in the active area and the P+ contact compensation part.

[0113] The cells in the active area of ​​the present invention adopt a trench structure, and a P-type base region 4 and a source contact hole connection structure based on a ballast structure are prepared on both sides of each cell trench 5. A P+ contact compensation portion is provided on the sidewall of the contact hole 12 corresponding to the junction of the P+ contact region 8 and the N++ source region 11; after the source metal 9 is filled in the contact hole 12 in the source contact hole connection structure, the ohmic contact between the source metal 9 and the P+ contact compensation portion in the filled contact hole 12 is utilized to compensate for the ohmic contact area between the source metal 9 and the P+ contact region 8 in the ballast structure, thereby effectively improving the reliability during reverse withstand voltage, being compatible with existing processes, and being safe and reliable.

Claims

1. A high reliability power device, characterized in that: include: A substrate of a first conductivity type, wherein an active region is formed in a central region of a front surface of the substrate; An active area includes a plurality of cells distributed in parallel, wherein the cells adopt a trench structure. For any cell, the cell includes at least one cell trench. A second conductive type base region and a source contact hole connection structure based on a ballast structure are prepared on both sides of each cell trench. The second conductive type base region contacts the outer sidewalls of the cell trench. The short-circuit current capability of the power device is improved based on the ballast structure. A source contact hole connection structure, comprising a first conductivity type source region adapted to a second conductivity type base region, a plurality of contact holes spaced by the first conductivity type source region, and a second conductivity type contact region corresponding one-to-one to the contact holes, wherein the first conductivity type source region includes a first conductivity type separation region, the contact holes are separated by the first conductivity type separation region, the second conductivity type contact region is located within the second conductivity type base region, a distance is provided between the second conductivity type contact region and the first conductivity type separation region in a depth direction of a cell trench, and a second conductivity type contact compensation portion is provided on a sidewall of the contact hole corresponding to a junction between the second conductivity type contact region and the first conductivity type separation region; After the source metal is filled in the contact hole in the source contact hole connection structure, the ohmic contact between the source metal and the second conductive type contact compensation portion in the filled contact hole is utilized to compensate for the ohmic contact area between the source metal and the second conductive type contact region in the ballast structure.

2. The high-reliability power device according to claim 1, wherein: The cell groove is in the shape of an elongated strip; In the source contact hole connection structure based on the ballast structure, the first conductive type source region further includes a first conductive type contact region, and the first conductive type contact region is connected to the first conductive type separation region, wherein: The first conductive type contact region contacts the outer sidewall of the adjacent cell trench and is distributed along the length of the cell trench; the first conductive type separation region is located outside the first conductive type contact region.

3. The high-reliability power device according to claim 2, wherein: The second conductive type contact compensation portion includes a second conductive type vertical compensation area or a second conductive type compensation step area, wherein: The second conductive type vertical compensation region is located below the first conductive type separation region; The second conductive type compensation step region includes a plurality of compensation steps, and the compensation steps are located outside the first conductive type separation region.

4. The high-reliability power device according to claim 3, wherein: When the second conductive type contact compensation portion is a second conductive type vertical compensation region, the second conductive type vertical compensation region and the second conductive type contact region are formed by the same ion implantation process step, wherein: During ion implantation, an inclined implantation method is adopted to prepare a required second conductive type vertical compensation region at the junction of the second conductive type contact region and the first conductive type separation region.

5. The high-reliability power device according to claim 3, wherein: When the second conductive type contact compensation portion is a second conductive type compensation step region, a required compensation step is prepared, and after the compensation step is prepared, ion implantation is performed to simultaneously form the second conductive type contact region and the second conductive type compensation step region.

6. The high-reliability power device according to claim 5, wherein: When preparing the compensation step, the first conductive type separation region body forming the first conductive type separation region and the insulating dielectric layer body forming the insulating dielectric layer are selectively etched, and the contact hole is etched using the etched insulating dielectric layer body as a mask to form a contact hole with a compensation step after etching; as well as, A first conductive type separation region and an insulating dielectric layer located above the first conductive type separation region are formed.

7. The high-reliability power device according to any one of claims 1 to 6, characterized in that: For any cellular trench, the cellular trench penetrates the second conductive type base region, and the bottom of the cellular trench is located below the second conductive type base region; The cell trench is filled with gate conductive polysilicon, which is insulated and isolated from the cell trench by an insulating oxide layer covering the inner sidewalls and bottom wall of the cell trench, and the gate conductive polysilicon is insulated and isolated from the source metal.

8. The high-reliability power device according to any one of claims 1 to 6, characterized in that: A back electrode structure is provided on the back side of the substrate, and the back electrode structure cooperates with the active area of ​​the substrate so that the power device is a MOSFET type device or an IGBT type device.

9. A method for preparing a high-reliability power device, characterized in that: For preparing the power device according to claim 1, the preparation method comprises: Providing a substrate of a first conductivity type, and preparing an active region in a central region of a front surface of the substrate; The prepared active area includes a plurality of cells distributed in parallel, wherein the cells adopt a trench structure. For any cell, the cell includes at least one cell trench. A second conductive type base region and a source contact hole connection structure based on a ballast structure are prepared on both sides of each cell trench. The second conductive type base region contacts the outer sidewalls of the cell trench. The short-circuit current capability of the power device is improved based on the ballast structure. A source contact hole connection structure, comprising a first conductivity type source region adapted to a second conductivity type base region, a plurality of contact holes spaced by the first conductivity type source region, and a second conductivity type contact region corresponding one-to-one to the contact holes, wherein the first conductivity type source region includes a first conductivity type separation region, the contact holes are separated by the first conductivity type separation region, the second conductivity type contact region is located within the second conductivity type base region, a distance is provided between the second conductivity type contact region and the first conductivity type separation region in a depth direction of a cell trench, and a second conductivity type contact compensation portion is provided on a sidewall of the contact hole corresponding to a junction between the second conductivity type contact region and the first conductivity type separation region; After the source metal is filled in the contact hole in the source contact hole connection structure, the ohmic contact between the source metal and the second conductive type contact compensation portion in the filled contact hole is utilized to compensate for the ohmic contact area between the source metal and the second conductive type contact region in the ballast structure.

10. The method for preparing a high-reliability power device according to claim 9, wherein: The doping concentration of the second conductive type contact compensation portion is consistent with the doping concentration of the second conductive type contact region, and the doping concentration of the second conductive type contact compensation portion is greater than the doping concentration of the second conductive type base region.

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