Clock reception circuit and electronic device

Abstract

The present disclosure provides a clock receiving circuit, which comprises a common-mode voltage adjusting module, an amplitude amplifying module and a level converting module. The common-mode voltage adjusting module comprises an n-type signal converting unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal converting unit, a high-level p-type signal output end and a low-level p-type signal output end. The amplitude amplifying module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit. Two second ends of the p-type transistor differential pair are electrically connected with two first ends of the n-type transistor differential pair respectively. Two second ends of the n-type transistor differential pair are electrically connected with a first pole of the n-type current source transistor. The level converting module is used for converting a CML level signal output by the amplitude amplifying circuit into a CMOS level signal. The present disclosure also provides an electronic device.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of integrated circuits, and in particular, to a clock receiving circuit and an electronic device comprising the same. BACKGROUND

[0002] With the evolution of CMOS manufacturing process and the improvement of design level, the working frequency of integrated circuits is getting higher and higher, and the high-speed clock attenuates more seriously in the transmission process and is more susceptible to noise, mismatch and other non-ideal factors, causing the clock performance to decline. Therefore, in high-speed circuits, the clock receiving circuit is particularly important.

[0003] Figure 1 As shown in the related art, a clock receiving circuit adopts a current mode logic (CML) structure to receive and amplify an input clock. The clock receiving circuit has large phase noise and large power consumption. SUMMARY

[0004] The present disclosure provides a clock receiving circuit and an electronic device comprising the same.

[0005] As a first aspect of the present disclosure, a clock receiving circuit is provided, wherein the clock receiving circuit comprises a common-mode voltage adjusting module, an amplitude amplifying module and a level converting module,

[0006] The common-mode voltage adjusting module comprises an n-type signal converting unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal converting unit, a high-level p-type signal output end and a low-level p-type signal output end. The n-type signal converting unit is configured to convert an input n-type signal into a high-level n-type signal and output the high-level n-type signal through the high-level n-type signal output end. The n-type signal converting unit is also configured to convert the input n-type signal into a low-level n-type signal and output the low-level n-type signal. The p-type signal converting unit is configured to convert an input p-type signal into a high-level p-type signal and output the high-level p-type signal through the high-level p-type signal output end. The p-type signal converting unit is also configured to convert the input p-type signal into a low-level p-type signal and output the low-level p-type signal through the low-level p-type signal output end.

[0007] The amplitude amplifying module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit.

[0008] The bias control unit is configured to control the p-type current source transistor and the n-type current source transistor to work in a saturation region.

[0009] The first pole of the p-type current source transistor is electrically connected with a high level signal end, and the second pole of the p-type current source transistor is electrically connected with two first poles of the p-type transistor differential pair;

[0010] Two second poles of the p-type transistor differential pair are respectively electrically connected with two first poles of the n-type transistor differential pair, and two input poles of the p-type transistor differential pair are respectively electrically connected with a low level p-type signal output end and a low level n-type signal output end, so that two p-type transistors in the p-type transistor differential pair both work in an amplification zone.

[0011] Two second poles of the n-type transistor differential pair are electrically connected with the first pole of the n-type current source transistor, and two input poles of the n-type transistor differential pair are respectively electrically connected with a high level p-type signal output end and a high level n-type signal output end, so that two n-type transistors in the n-type transistor differential pair both work in an amplification zone.

[0012] The level conversion module is used for converting a CML level signal output by the amplitude amplification circuit into a CMOS level signal.

[0013] Optionally, the p-type transistor differential pair includes a first p-type transistor and a second p-type transistor, the first pole of the first p-type transistor is electrically connected with the first pole of the second p-type transistor, the first pole of the first p-type transistor and the first pole of the second p-type transistor are respectively formed into two first poles of the p-type differential pair, the second pole of the first p-type transistor and the second pole of the second p-type transistor are respectively formed into two second poles of the p-type differential pair, the gate of the first p-type transistor and the gate of the second p-type transistor are respectively formed into two input poles of the p-type transistor differential pair, the gate of the first p-type transistor is electrically connected with the low level n-type signal output end, and the gate of the second p-type transistor is electrically connected with the low level p-type signal output end.

[0014] Optionally, the n-type transistor differential pair includes a first n-type transistor and a second n-type transistor, the first pole of the first n-type transistor and the first pole of the second n-type transistor are respectively formed into two first poles of the n-type transistor differential pair, the first pole of the first n-type transistor is electrically connected with the second pole of the first p-type transistor, and the first pole of the second n-type transistor is electrically connected with the second pole of the second p-type transistor.

[0015] The second pole of the first n-type transistor and the second pole of the second n-type transistor are respectively formed into two second poles of the n-type differential pair, and the second pole of the first n-type transistor is electrically connected with the second pole of the second n-type transistor.

[0016] The gate of the first n-type transistor and the gate of the second n-type transistor are formed as two input terminals of the n-type transistor differential pair, the gate of the first n-type transistor is electrically connected with the high-level n-type signal output terminal, and the gate of the second n-type transistor is electrically connected with the high-level p-type signal output terminal.

[0017] Optionally, the bias control unit comprises a first n-type current mirror transistor, a second n-type current mirror transistor, a third n-type current mirror transistor, a fourth n-type current mirror transistor, a first p-type current mirror transistor and a second p-type current mirror transistor.

[0018] The first electrode of the first n-type current mirror transistor is used for being electrically connected with a current source, the first electrode of the first n-type current mirror transistor is electrically connected with the gate of the first n-type current mirror transistor, the second electrode of the first n-type current mirror transistor is electrically connected with the first electrode of the second n-type current mirror transistor, the second electrode of the second n-type current mirror transistor is grounded, and the gate of the second n-type current mirror transistor is electrically connected with the gate of the third n-type current mirror transistor and the gate of the n-type current source transistor.

[0019] The first electrode of the third n-type current mirror transistor is grounded, and the second electrode of the third n-type current mirror transistor is electrically connected with the first electrode of the fourth n-type current mirror transistor.

[0020] The second electrode of the fourth n-type current mirror transistor is electrically connected with the first electrode of the first p-type current mirror transistor, and the gate of the fourth n-type current mirror transistor is electrically connected with the gate of the first n-type current mirror transistor.

[0021] The gate of the first p-type current mirror transistor is electrically connected with the first electrode of the first p-type current mirror transistor, and the second electrode of the first p-type current mirror transistor is electrically connected with the first electrode of the second p-type current mirror transistor.

[0022] The second electrode of the second p-type current mirror transistor is used for being electrically connected with a high-level signal terminal, and the gate of the second p-type current mirror transistor is electrically connected with the gate of the p-type current source transistor.

[0023] Optionally, the common-mode voltage adjustment module further comprises an impedance matching resistor, a first voltage dividing resistor and a second voltage dividing resistor, the impedance matching resistor is connected between the p port and the n port of the common-mode voltage adjustment module, one end of the first voltage dividing resistor is electrically connected with a high-level signal terminal.

[0024] The p-type signal conversion unit comprises a first coupling capacitor, a third coupling capacitor, and a third resistor, a fifth resistor, a seventh resistor and a ninth resistor connected in series, one end of the third coupling capacitor is electrically connected with the other end of the first voltage dividing resistor, the ninth resistor is electrically connected with one end of the second voltage dividing resistor, the second end of the second voltage dividing resistor is grounded, the first coupling capacitor is connected in parallel with the fifth resistor, and the high-level p-type signal output end is electrically connected with the connection point of the third resistor and the fifth resistor, the third coupling capacitor is connected in parallel with the seventh resistor, and the low-level p-type signal output end is electrically connected with the connection point of the seventh resistor and the ninth resistor, and the p port is electrically connected with the connection point of the fifth resistor and the seventh resistor;

[0025] The n-type signal conversion unit comprises a second coupling capacitor, a fourth coupling capacitor, and a fourth resistor, a sixth resistor, an eighth resistor and a tenth resistor connected in series, one end of the fourth coupling capacitor is electrically connected with the other end of the first voltage dividing resistor, the tenth resistor is electrically connected with one end of the second voltage dividing resistor, the second coupling capacitor is connected in parallel with the sixth resistor, and the high-level n-type signal output end is electrically connected with the connection point of the fourth resistor and the sixth resistor, the fourth coupling capacitor is connected in parallel with the eighth resistor, and the low-level n-type signal output end is electrically connected with the connection point of the eighth resistor and the tenth resistor, and the n port is electrically connected with the connection point of the sixth resistor and the eighth resistor.

[0026] Optionally, the level conversion module comprises a first inverter, a second inverter, a first feedback component, and a second feedback component.

[0027] The input end of the first inverter is electrically connected with the p-type signal output end of the amplitude amplification module, and the output end of the first inverter forms an n-type signal output end of the clock receiving circuit.

[0028] The first feedback component is used for collecting the current output by the first inverter and feeding back the collected current to the input end of the first inverter.

[0029] The input end of the second inverter is electrically connected with the n-type signal output end of the amplitude amplification module, and the output end of the second inverter forms a p-type signal output end of the clock receiving circuit.

[0030] The second feedback component is used for collecting the current output by the second inverter and feeding back the collected current to the input end of the second inverter.

[0031] Optionally, the first feedback component comprises a first n-type feedback transistor and a first p-type feedback transistor,

[0032] The gate of the first n-type feedback transistor is electrically connected with the output end of the first inverter, the first pole of the first n-type feedback transistor is electrically connected with the high-level signal end, and the second pole of the first n-type feedback transistor is electrically connected with the input end of the first inverter.

[0033] The gate of the first p-type feedback transistor is electrically connected with the output end of the first inverter, the first pole of the first p-type feedback transistor is grounded, and the second pole of the first p-type feedback transistor is electrically connected with the input end of the first inverter.

[0034] Optionally, the second feedback component includes a second n-type feedback transistor and a second p-type feedback transistor,

[0035] The gate of the second n-type feedback transistor is electrically connected with the output end of the second inverter, the first pole of the second n-type feedback transistor is electrically connected with the high-level signal end, and the second pole of the second n-type feedback transistor is electrically connected with the input end of the second inverter.

[0036] The gate of the second p-type feedback transistor is electrically connected with the output end of the second inverter, the first pole of the second p-type feedback transistor is grounded, and the second pole of the second p-type feedback transistor is electrically connected with the input end of the second inverter.

[0037] As a second aspect of the present disclosure, an electronic device is provided, which includes a clock receiving circuit and a core module, the clock signal input end of the core module is electrically connected with the output end of the clock receiving circuit, and the clock receiving circuit is the clock receiving circuit provided in the first aspect of the present disclosure.

[0038] Optionally, the core module is any one of the following devices:

[0039] Analog-to-digital converter, digital-to-analog converter, phase-locked loop module.

[0040] The core component of the clock receiving circuit provided in the present disclosure is an amplitude amplification module, the p-type transistor differential pair and the n-type transistor differential pair of the amplitude amplification module are input and load to each other, forming a push-pull structure, increasing the equivalent transconductance of the entire amplitude amplification module, and the amplitude amplification module can provide a relatively large clock output swing under a low power supply voltage.

[0041] Since the clock receiving circuit can provide sufficient gain under a low power supply voltage to obtain a large output swing, the output clock establishment process of the core module in the rear stage is also relatively fast, the influence of noise during the establishment of the clock is alleviated or even avoided, the output phase noise of the electronic device is small, the power consumption of the electronic device is reduced, and the performance of the electronic device is improved. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 is a circuit schematic diagram of a clock signal receiving circuit in the related art;

[0043] Figure 2 is a module schematic diagram of an embodiment of the clock receiving circuit provided by the present disclosure;

[0044] Figure 3 is a schematic diagram of an embodiment of the common-mode voltage adjustment module in the clock receiving circuit provided by the present disclosure;

[0045] Figure 4 is a schematic diagram of an embodiment of the amplitude amplification module in the clock receiving circuit provided by the present disclosure;

[0046] Figure 5 is a schematic diagram of an embodiment of the level conversion module in the clock receiving circuit provided by the present disclosure;

[0047] Figure 6 is a schematic diagram of an electronic device whose core module is a digital-to-analog converter or an analog-to-digital converter;

[0048] Figure 7 is a schematic diagram of an electronic device whose core module is a phase-locked loop circuit. DETAILED DESCRIPTION

[0049] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the clock receiving circuit and the electronic device provided by the present disclosure are described in detail below with reference to the accompanying drawings.

[0050] The example embodiments will be described more fully hereinafter with reference to the accompanying drawings, in which example embodiments can be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0051] In the case of no conflict, each embodiment of the present disclosure and each feature in the embodiments can be combined with each other.

[0052] As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0053] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded.

[0054] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0055] As one aspect of this disclosure, a clock receiving circuit is provided, such as Figure 2 As shown, the clock receiving circuit includes a common-mode voltage adjustment module 100, an amplitude amplification module 200, and a level conversion module 300.

[0056] like Figure 3 As shown, the common-mode voltage adjustment module 100 includes an n-type signal conversion unit 110, a high-level n-type signal output terminal von_n, a low-level n-type signal output terminal vop_n, a p-type signal conversion unit 120, a high-level p-type signal output terminal von_p, and a low-level p-type signal output terminal vop_p.

[0057] The n-type signal conversion unit 110 is used to convert the input n-type signal into a high-level n-type signal and output it through the high-level n-type signal output terminal von_n. The n-type signal conversion unit 110 is also used to convert the input n-type signal into a low-level n-type signal and output it through the low-level n-type signal terminal vop_n.

[0058] The p-type signal conversion unit 120 is used to convert the input p-type signal into a high-level p-type signal and output it through the high-level p-type signal von_p output terminal. The p-type signal conversion unit 120 is also used to convert the input p-type signal into a low-level p-type signal and output it through the low-level p-type signal output terminal vop_p.

[0059] The amplitude amplification module 200 includes a p-type current source transistor M6, an n-type current source transistor M5, a p-type transistor differential pair 210, an n-type transistor differential pair 220, and a bias control unit 230.

[0060] The bias control unit 230 is configured to control the p-type current source transistor M6 and the n-type current source transistor M5 to work in the saturation region.

[0061] The first pole of the p-type current source transistor M6 is electrically connected with the high-level signal terminal, and the second pole of the p-type current source transistor M6 is electrically connected with the two first poles of the p-type transistor differential pair 210.

[0062] The two second poles of the p-type transistor differential pair 210 are respectively electrically connected with the two first poles of the n-type transistor differential pair 220, and the two input poles of the p-type transistor differential pair 210 are respectively electrically connected with the low-level p-type signal output terminal vop_p and the low-level n-type signal output terminal vop_n, so that the two p-type transistors in the p-type transistor differential pair work in the amplification region.

[0063] The two second poles of the n-type transistor differential pair 220 are electrically connected with the first pole of the n-type current source transistor M5, and the two input poles of the n-type transistor differential pair 220 are respectively electrically connected with the high-level p-type signal output terminal von_p and the high-level n-type signal output terminal von_n, so that the two n-type transistors in the n-type transistor differential pair work in the amplification region.

[0064] The level conversion module 300 is configured to convert the CML level signal output by the amplitude amplification circuit into a CMOS level signal.

[0065] The core component of the clock receiving circuit provided by the present disclosure is the amplitude amplification module 200, the p-type transistor differential pair 210 and the n-type transistor differential pair 220 of the amplitude amplification module 200 are input and load to each other, forming a push-pull structure, increasing the equivalent transconductance of the entire amplitude amplification module 200, and the amplitude amplification module 200 can provide a relatively large clock output swing under a low power voltage. It should be noted that the p-type transistor differential pair 210 and the n-type transistor differential pair 220 have two connection nodes, which are formed into the n-type signal output terminal voutn and the p-type signal output terminal voup of the amplitude amplification module 200, respectively.

[0066] The main function of the common-mode voltage adjustment module 100 is to adjust the differential signal received by the clock receiving circuit, and output a signal that can make the transistors of the p-type transistor differential pair 210 and the n-type transistor differential pair 220 of the amplitude amplification module 200 work in the amplification region.

[0067] The functions of the p-type current source transistor M6 and the n-type current source transistor M5 are to provide driving current for the amplitude amplification module under the control of the bias control unit.

[0068] In the present disclosure, the specific structure of the p-type transistor differential pair is not specially limited, and the p-type transistor differential pair can be a common-source type or a common-drain type. Figure 4In the illustrated embodiment, the p-type transistor differential pair includes a first p-type transistor M4 and a second p-type transistor M3. The first terminal of the first p-type transistor M4 is electrically connected to the first terminal of the second p-type transistor M3. The first terminals of the first p-type transistor M4 and the second p-type transistor M3 are respectively formed as the two first terminals of the p-type differential pair. The second terminals of the first p-type transistor M4 and the second p-type transistor M3 are respectively formed as the two second terminals of the p-type differential pair. The gates of the first p-type transistor M4 and the second p-type transistor M3 are respectively formed as the two input terminals of the p-type transistor differential pair. The gate of the first p-type transistor M4 (in...) Figure 4 The middle part (vin_p) is electrically connected to the low-level n-type signal output terminal vop_p, and the gate of the second p-type transistor M3 (in) Figure 4 The middle part (vip_p) is electrically connected to the low-level p-type signal output terminal.

[0069] It should be noted that the second terminal of the first p-type transistor M4 is formed as the n-type signal output terminal of the amplitude amplification module 200, and the second terminal of the second p-type transistor M3 is formed as the p-type signal output terminal of the amplitude amplification module 200.

[0070] In this disclosure, no special limitations are placed on the specific structure of the n-type transistor differential pair, such as Figure 4 As shown, the n-type transistor differential pair includes a first n-type transistor M2 and a second n-type transistor M1. The first terminal of the first n-type transistor M2 and the first terminal of the second n-type transistor M1 are respectively formed as the two first terminals of the n-type transistor differential pair. The first terminal of the first n-type transistor M2 is electrically connected to the second terminal of the first p-type transistor M4, and the first terminal of the second n-type transistor M1 is electrically connected to the second terminal of the second p-type transistor M3.

[0071] The second terminals of the first n-type transistor M2 and the second n-type transistor M1 are respectively formed as the two second terminals of the n-type differential pair. The second terminals of the first n-type transistor M2 and the second n-type transistor M1 are electrically connected, and both are electrically connected to the first terminal of the n-type current transistor M5.

[0072] The gate of the first n-type transistor M2 and the gate of the second n-type transistor M1 are respectively formed as the two input terminals of the n-type transistor differential pair (in Figure 4 In the above, vin_n and vip_n are respectively, the gate of the first n-type transistor M2 is electrically connected to the high-level n-type signal output terminal, and the gate of the second n-type transistor M1 is electrically connected to the high-level p-type signal output terminal.

[0073] In the present disclosure, the specific structure of the bias control unit 230 is not particularly limited, as long as it can provide bias for the gates of the p-type current transistor M6 and the n-type current transistor M5, so that the p-type current transistor M6 and the n-type current transistor M5 work in the saturation region.

[0074] In the embodiment shown in the present disclosure, the bias control unit includes a first n-type current mirror transistor M9, a second n-type current mirror transistor M7, a third n-type current mirror transistor M8, a fourth n-type current mirror transistor M10, a first p-type current mirror transistor M11, and a second p-type current mirror transistor M12. Figure 4

[0075] The first electrode of the first n-type current mirror transistor M9 is electrically connected with a current source (which provides a reference circuit I REF ), the first electrode of the first n-type current mirror transistor M9 is electrically connected with the gate of the first n-type current mirror transistor M9, the second electrode of the first n-type current mirror transistor M9 is electrically connected with the first electrode of the second n-type current mirror transistor M7, the second electrode of the second n-type current mirror transistor M7 is grounded, and the gate of the second n-type current mirror transistor M7 is electrically connected with the gate of the third n-type current mirror transistor M8 and the gate of the n-type current source transistor M5.

[0076] The first electrode of the third n-type current mirror transistor M8 is grounded, and the second electrode of the third n-type current mirror transistor M8 is electrically connected with the first electrode of the fourth n-type current mirror transistor M10.

[0077] The second electrode of the fourth n-type current mirror transistor M10 is electrically connected with the first electrode of the first p-type current mirror transistor M11, and the gate of the fourth n-type current mirror transistor M10 is electrically connected with the gate of the first p-type current mirror transistor M11.

[0078] The gate of the first p-type current mirror transistor M11 is electrically connected with the first electrode of the first p-type current mirror transistor M11, and the second electrode of the first p-type current mirror transistor M11 is electrically connected with the first electrode of the second p-type current mirror transistor M12.

[0079] The second electrode of the second p-type current mirror transistor M12 is electrically connected with a high-level signal terminal, and the gate of the second p-type current mirror transistor M12 is electrically connected with the gate of the p-type current source transistor M6.

[0080] In the present disclosure, the gate of the n-type current source transistor M5 is electrically connected with the gate of the second n-type current mirror transistor M7, so that the gate voltage of the n-type current source transistor M5 is the same as the gate voltage of the second n-type current mirror transistor M7. By controlling the sizes of the first n-type current mirror transistor M5 and the second n-type current mirror transistor M7, the gate voltage that makes the n-type current source transistor M5 work in the saturation region can be obtained.​

[0081] Similarly, the gate of the p-type current source transistor M6 is electrically connected with the gate of the second p-type current mirror transistor M12, so that the gate voltage of the p-type current source transistor M6 is the same as the gate voltage of the second p-type current mirror transistor M12. In the present disclosure, the first n-type current mirror transistor M9, the second n-type current mirror transistor M7, the third n-type current mirror transistor M8, and the fourth n-type current mirror transistor M10 constitute a current mirror, so that the current of the fourth n-type current mirror transistor M10 is proportional to the current of the first n-type current mirror transistor M9, the current received by the first p-type current mirror transistor M11 is the same as the current of the fourth n-type current mirror transistor M10 and is proportional to the current received by the first electrode of the first n-type current mirror transistor M9. By controlling the size of the first p-type current mirror transistor M11 and the second p-type current mirror transistor M12, the gate voltage that makes the p-type current source transistor M6 work in the saturation region can be obtained.

[0082] In the present disclosure, the specific structure of the common-mode voltage adjustment module 100 is not specially limited. As shown in FIG. 1, the common-mode voltage adjustment module further includes an impedance matching resistor R11, a first voltage dividing resistor R1, and a second voltage dividing resistor R2. The impedance matching resistor R11 is connected between the p port vip and the n port vin of the common-mode voltage adjustment module. One end of the first voltage dividing resistor R1 is electrically connected with the high-level signal end. Figure 3

[0083] The p-type signal conversion unit 120 includes a first coupling capacitor C1, a third coupling capacitor C3, and a third resistor R3, a fifth resistor R5, a seventh resistor R7, and a ninth resistor R9 connected in series. One end of the third coupling capacitor C3 is electrically connected with the other end of the first voltage dividing resistor R1. The ninth resistor R9 is electrically connected with one end of the second voltage dividing resistor R2. The second end of the second voltage dividing resistor R2 is grounded. The first coupling capacitor C1 is connected in parallel with the fifth resistor R5. The high-level p-type signal output end von_p is electrically connected with the connection point of the third resistor R3 and the fifth resistor R5. The third coupling capacitor C3 is connected in parallel with the seventh resistor R7. The low-level p-type signal output end vop_p is electrically connected with the connection point of the seventh resistor R7 and the ninth resistor R9. The p port vip is electrically connected with the connection point of the fifth resistor R5 and the seventh resistor R7.

[0084] ​The n-type signal conversion unit 110 includes a second coupling capacitor C2, a fourth coupling capacitor C4, and a fourth resistor R4, a sixth resistor R6, an eighth resistor R8, and a tenth resistor R10 connected in series, one end of the fourth coupling capacitor C4 is electrically connected with the other end of the first voltage dividing resistor R1, the tenth resistor R10 is electrically connected with one end of the second voltage dividing resistor R2, the second coupling capacitor C2 is connected in parallel with the sixth resistor R6, and a high-level n-type signal output end von_n is electrically connected with the connection point of the fourth resistor R4 and the sixth resistor R6, the fourth coupling capacitor C4 is connected in parallel with the eighth resistor R8, and a low-level n-type signal output end vop_n is electrically connected with the connection point of the eighth resistor R8 and the tenth resistor R10, and an n-port vin is electrically connected with the connection point of the sixth resistor R6 and the eighth resistor R8.

[0085] In the present disclosure, the common-mode voltage is adjusted by using a resistance chain, and the resistance value can be flexibly adjusted according to the application scenario, thereby changing the common-mode voltage and improving the flexibility of the circuit.

[0086] In the present disclosure, the specific structure of the level conversion module 300 is not specially limited, for example, as shown in FIG. 3, the level conversion module includes a first inverter 310, a second inverter 320, a first feedback component 330, and a second feedback component 340. Figure 5

[0087] The input end vip1 of the first inverter 310 is electrically connected with the p-type signal output end of the amplitude amplification module 200, and the output end of the first inverter 310 forms an n-type signal output end voutn1 of the clock receiving circuit.

[0088] The first feedback component 330 is used to collect the output signal of the first inverter 310 and feed back the collected signal to the input end of the first inverter 310, so as to perform a rough calibration on the output of the first inverter 310.

[0089] The input end vin1 of the second inverter 320 is electrically connected with the n-type signal output end of the amplitude amplification module 200, and the output end of the second inverter 320 forms a p-type signal output end voutn2 of the clock receiving circuit.

[0090] The second feedback component 340 is used to collect the output signal of the second inverter 320 and feed back the collected signal to the input end of the second inverter 320, so as to perform a rough calibration on the output of the second inverter 320.

[0091] In the present disclosure, the clock receiving circuit is not specially limited, for example, as shown in FIG. 2, the clock receiving circuit includes an amplitude amplification module 200 and a level conversion module 300. Figure 5 ​In the embodiment shown in FIG. 3, the first inverter 310 includes a first p-type transistor M13 and a first n-type transistor M14, the first p-type transistor M13 has a first electrode electrically connected to the high-level signal terminal, the first p-type transistor M13 has a gate electrically connected to an input terminal vip1 of the first inverter 310, the first p-type transistor M13 has a second electrode electrically connected to a first electrode of the first n-type transistor M14 and an output terminal of the first inverter 310, the second electrode of the first n-type transistor is grounded, and the gate of the first n-type transistor is electrically connected to the input terminal vip1 of the first inverter 310.

[0092] In Figure 5 In the embodiment shown in FIG. 3, the second inverter 320 includes a second p-type transistor M15 and a second n-type transistor M16, the second p-type transistor M15 has a first electrode electrically connected to the high-level signal terminal, the second p-type transistor M15 has a gate electrically connected to an input terminal vin1 of the second inverter 320, the second p-type transistor M15 has a second electrode electrically connected to a first electrode of the second n-type transistor M16 and an output terminal of the second inverter 320, the second electrode of the second n-type transistor M16 is grounded, and the gate of the second n-type transistor M16 is electrically connected to the input terminal vin1 of the second inverter 320.

[0093] In the present disclosure, the specific structure of the first feedback component 330 is not specially limited, as shown in Figure 5 The first feedback component 330 includes a first n-type feedback transistor M17 and a first p-type feedback transistor M18.

[0094] The gate of the first n-type feedback transistor M17 is electrically connected to the output terminal of the first inverter 310, the first electrode of the first n-type feedback transistor M17 is electrically connected to the high-level signal terminal, and the second electrode of the first n-type transistor M17 is electrically connected to the input terminal of the first inverter 330.

[0095] The gate of the first p-type feedback transistor M18 is electrically connected to the output terminal of the first inverter 310, the first electrode of the first p-type feedback transistor M18 is grounded, and the second electrode of the first p-type transistor M18 is electrically connected to the input terminal of the first inverter 330.

[0096] The first n-type feedback transistor M17 and the first p-type feedback transistor M18 are both voltage-controlled components, and will not generate power consumption in the case of not meeting the conduction condition. Therefore, the first feedback component including the first n-type feedback transistor M17 and the first p-type feedback transistor M18 can reduce the overall power consumption of the clock receiving circuit.

[0097] In the present disclosure, the specific structure of the second feedback component 340 is not specially limited, as shown in Figure 5As shown, the second feedback component 340 can optionally include a second n-type feedback transistor M19 and a second p-type feedback transistor M20.

[0098] The gate of the second n-type feedback transistor M19 is electrically connected to the output of the second inverter 320, the first pole of the second n-type feedback transistor M19 is electrically connected to the high-level signal terminal, and the second pole of the second n-type feedback transistor M19 is electrically connected to the input of the second inverter.

[0099] The gate of the second p-type feedback transistor M20 is electrically connected to the output of the second inverter 320, the first pole of the second p-type feedback transistor M20 is grounded, and the second pole of the second p-type feedback transistor M20 is electrically connected to the input of the second inverter 320.

[0100] The second n-type feedback transistor M19 and the second p-type feedback transistor M20 are voltage-controlled on elements, and will not generate power consumption in the case of not meeting the on condition, so the first feedback component including the second n-type feedback transistor M19 and the second p-type feedback transistor M20 can reduce the overall power consumption of the clock receiving circuit.

[0101] The first feedback component 330 including the first n-type feedback transistor M17 and the first p-type feedback transistor M18 and the second feedback component 340 including the second n-type feedback transistor M19 and the second p-type feedback transistor M20 not only can reduce the overall power consumption, but also have simpler layout wiring and smaller occupied area, and can improve the overall integration of the clock receiving circuit.

[0102] As a second aspect of the present disclosure, an electronic device is provided, which includes a clock receiving circuit and a core module, and the clock signal input terminal of the core module is electrically connected to the output terminal of the clock receiving circuit.

[0103] Since the clock receiving circuit can provide sufficient gain under low power supply voltage, obtain a larger output swing, and the output clock establishment process of the core module in the later stage is also relatively fast, the influence of noise during the clock establishment process is alleviated or even avoided, so that the output phase noise of the electronic device is smaller, the power consumption of the electronic device is reduced, and the performance of the electronic device is improved.

[0104] In the present disclosure, the core module is not specially limited, and can optionally be any one of the following devices:

[0105] Analog-to-digital converter, digital-to-analog converter, phase-locked loop module.

[0106] Figure 6 As shown in FIG. 1, the core module is a digital-to-analog converter or an analog-to-digital converter, Figure 7It is shown that the core module is a phase-locked loop module.

[0107] Example embodiments have been disclosed herein and, although the specific terms are employed, they are used in a generic sense only and should not be construed to be limited to the specific embodiments described herein. In some instances, those skilled in the art will appreciate that, unless otherwise indicated herein, the features, characteristics or elements described in connection with a particular embodiment can be used singly or in any combination with the features, characteristics or elements described in connection with other embodiments. As such, those skilled in the art will appreciate that, unless otherwise indicated herein, various changes in form and detail can be made without departing from the scope of the disclosure as set forth in the accompanying claims.

Claims

1. A clock receiving circuit, characterized by comprising: The clock receiving circuit comprises a common-mode voltage adjusting module, an amplitude amplifying module and a level converting module, The common-mode voltage adjusting module comprises an n-type signal converting unit, a high-level n-type signal output end, a low-level n-type signal output end, a p-type signal converting unit, a high-level p-type signal output end and a low-level p-type signal output end; the n-type signal converting unit is configured to convert an input n-type signal into a high-level n-type signal and output the high-level n-type signal through the high-level n-type signal output end; the n-type signal converting unit is also configured to convert the input n-type signal into a low-level n-type signal and output the low-level n-type signal; the p-type signal converting unit is configured to convert an input p-type signal into a high-level p-type signal and output the high-level p-type signal through the high-level p-type signal output end; and the p-type signal converting unit is also configured to convert the input p-type signal into a low-level p-type signal and output the low-level p-type signal through the low-level p-type signal output end; The amplitude amplifying module comprises a p-type current source transistor, an n-type current source transistor, a p-type transistor differential pair, an n-type transistor differential pair and a bias control unit; The bias control unit is configured to control the p-type current source transistor and the n-type current source transistor to work in a saturation region; a first pole of the p-type current source transistor is electrically connected with a high-level signal end; and a second pole of the p-type current source transistor is electrically connected with two first ends of the p-type transistor differential pair; two second ends of the p-type transistor differential pair are respectively electrically connected with two first ends of the n-type transistor differential pair; two input ends of the p-type transistor differential pair are respectively electrically connected with the low-level p-type signal output end and the low-level n-type signal output end, so that two p-type transistors in the p-type transistor differential pair both work in an amplification region; two second ends of the n-type transistor differential pair are electrically connected with a first pole of the n-type current source transistor; and two input ends of the n-type transistor differential pair are respectively electrically connected with the high-level p-type signal output end and the high-level n-type signal output end, so that two n-type transistors in the n-type transistor differential pair both work in an amplification region; The level converting module is configured to convert a CML level signal output by the amplitude amplifying circuit into a CMOS level signal; The bias control unit comprises a first n-type current mirror transistor, a second n-type current mirror transistor, a third n-type current mirror transistor, a fourth n-type current mirror transistor, a first p-type current mirror transistor and a second p-type current mirror transistor; a first pole of the first n-type current mirror transistor is configured to be electrically connected with a current source; the first pole of the first n-type current mirror transistor is electrically connected with a gate of the first n-type current mirror transistor; a second pole of the first n-type current mirror transistor is electrically connected with a first pole of the second n-type current mirror transistor; a second pole of the second n-type current mirror transistor is grounded; and a gate of the second n-type current mirror transistor is electrically connected with a gate of the third n-type current mirror transistor and a gate of the n-type current source transistor; The first pole of the third n-type current mirror transistor is grounded, and the second pole of the third n-type current mirror transistor is electrically connected with the first pole of the fourth n-type current mirror transistor; The second pole of the fourth n-type current mirror transistor is electrically connected with the first pole of the first p-type current mirror transistor, and the gate of the fourth n-type current mirror transistor is electrically connected with the gate of the first n-type current mirror transistor; The gate of the first p-type current mirror transistor is electrically connected with the first pole of the first p-type current mirror transistor, and the second pole of the first p-type current mirror transistor is electrically connected with the first pole of the second p-type current mirror transistor; The second pole of the second p-type current mirror transistor is electrically connected with a high-level signal end, and the gate of the second p-type current mirror transistor is electrically connected with the gate of the p-type current source transistor.

2. The clock receiving circuit according to claim 1, characterized by The p-type transistor differential pair comprises a first p-type transistor and a second p-type transistor, the first pole of the first p-type transistor is electrically connected with the first pole of the second p-type transistor, the first pole of the first p-type transistor and the first pole of the second p-type transistor are respectively formed as two first ends of the p-type differential pair, the second pole of the first p-type transistor and the second pole of the second p-type transistor are respectively formed as two second ends of the p-type differential pair, the gate of the first p-type transistor and the gate of the second p-type transistor are respectively formed as two input ends of the p-type transistor differential pair, the gate of the first p-type transistor is electrically connected with a low-level n-type signal output end, and the gate of the second p-type transistor is electrically connected with a low-level p-type signal output end.

3. The clock receiving circuit according to claim 2, characterized by The n-type transistor differential pair comprises a first n-type transistor and a second n-type transistor, the first pole of the first n-type transistor and the first pole of the second n-type transistor are respectively formed as two first ends of the n-type transistor differential pair, the first pole of the first n-type transistor is electrically connected with the second pole of the first p-type transistor, and the first pole of the second n-type transistor is electrically connected with the second pole of the second p-type transistor; The second pole of the first n-type transistor and the second pole of the second n-type transistor are respectively formed as two second ends of the n-type differential pair, and the second pole of the first n-type transistor is electrically connected with the second pole of the second n-type transistor; The gate of the first n-type transistor and the gate of the second n-type transistor are respectively formed as two input ends of the n-type transistor differential pair, the gate of the first n-type transistor is electrically connected with a high-level n-type signal output end, and the gate of the second n-type transistor is electrically connected with a high-level p-type signal output end.

4. The clock receiving circuit according to any one of claims 1 to 3, characterized by, The common-mode voltage adjustment module further comprises an impedance matching resistor, a first voltage dividing resistor and a second voltage dividing resistor, one end of the impedance matching resistor is connected between a p port and an n port of the common-mode voltage adjustment module, one end of the first voltage dividing resistor is electrically connected with a high-level signal end, and the other end of the first voltage dividing resistor is electrically connected with the gate of the first n-type current mirror transistor. The p-type signal conversion unit comprises a first coupling capacitor, a third coupling capacitor and a third resistor, a fifth resistor, a seventh resistor and a ninth resistor connected in series, one end of the third coupling capacitor is electrically connected with the other end of the first voltage dividing resistor, the ninth resistor is electrically connected with one end of the second voltage dividing resistor, the second end of the second voltage dividing resistor is grounded, the first coupling capacitor is connected in parallel with the fifth resistor, and the high-level p-type signal output end is electrically connected with the connection position of the third resistor and the fifth resistor, the third coupling capacitor is connected in parallel with the seventh resistor, and the low-level p-type signal output end is electrically connected with the connection position of the seventh resistor and the ninth resistor, and the p port is electrically connected with the connection position of the fifth resistor and the seventh resistor; The n-type signal conversion unit comprises a second coupling capacitor, a fourth coupling capacitor and a fourth resistor, a sixth resistor, an eighth resistor and a tenth resistor connected in series, one end of the fourth coupling capacitor is electrically connected with the other end of the first voltage dividing resistor, the tenth resistor is electrically connected with one end of the second voltage dividing resistor, the second coupling capacitor is connected in parallel with the sixth resistor, and the high-level n-type signal output end is electrically connected with the connection position of the fourth resistor and the sixth resistor, the fourth coupling capacitor is connected in parallel with the eighth resistor, and the low-level n-type signal output end is electrically connected with the connection position of the eighth resistor and the tenth resistor, and the n port is electrically connected with the connection position of the sixth resistor and the eighth resistor.

5. The clock receiving circuit according to any one of claims 1 to 3, wherein The level conversion module comprises a first inverter, a second inverter, a first feedback component and a second feedback component; The input end of the first inverter is electrically connected with the p-type signal output end of the amplitude amplification module, and the output end of the first inverter forms the n-type signal output end of the clock receiving circuit; The first feedback component is used for collecting the current output by the first inverter and feeding back the collected current to the input end of the first inverter; The input end of the second inverter is electrically connected with the n-type signal output end of the amplitude amplification module, and the output end of the second inverter forms the p-type signal output end of the clock receiving circuit; The second feedback component is used for collecting the current output by the second inverter and feeding back the collected current to the input end of the second inverter.

6. The clock receiving circuit according to claim 5, characterized by The first feedback component comprises a first n-type feedback transistor and a first p-type feedback transistor, The gate of the first n-type feedback transistor is electrically connected with the output end of the first inverter, the first pole of the first n-type feedback transistor is electrically connected with the high-level signal end, and the second pole of the first n-type feedback transistor is electrically connected with the input end of the first inverter; The gate of the first p-type feedback transistor is electrically connected with the output end of the first inverter, the first pole of the first p-type feedback transistor is grounded, and the second pole of the first p-type feedback transistor is electrically connected with the input end of the first inverter.

7. The clock receiving circuit according to claim 5, wherein The second feedback component comprises a second n-type feedback transistor and a second p-type feedback transistor, The gate of the second n-type feedback transistor is electrically connected with the output end of the second inverter, the first pole of the second n-type feedback transistor is electrically connected with a high level signal end, and the second pole of the second n-type transistor is electrically connected with the input end of the second inverter; The gate of the second p-type feedback transistor is electrically connected with the output end of the second inverter, the first pole of the second p-type feedback transistor is grounded, and the second pole of the second p-type transistor is electrically connected with the input end of the second inverter. 8.An electronic device, comprising a clock receiving circuit and a core module, wherein a clock signal input end of the core module is electrically connected with an output end of the clock receiving circuit, and the clock receiving circuit is the clock receiving circuit according to any one of claims 1 to 7.

9. The electronic device of claim 8, wherein, The core module is any one of the following devices: an analog-to-digital converter, a digital-to-analog converter, and a phase-locked loop module.

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