Electronic converter circuit and method

Abstract

Embodiments of the present disclosure generally relate to electronic converter circuits and methods. In one embodiment, a circuit includes a voltage-controlled oscillator (VCO) circuit having a first node configured to receive a reference voltage, a second node configured to receive a feedback signal, and a third node configured to provide a clock signal having a clock period based on the reference voltage and the feedback signal, the feedback signal being a comparison signal indicative of a change in a regulated output voltage of an electronic voltage regulator relative to the reference voltage, and a pulse-width modulation (PWM) signal generator circuit having a first node coupled to the VCO circuit and configured to receive the clock signal, a second node configured to receive an input signal at an input node of the electronic voltage regulator proportional to an input voltage signal, and a third node configured to provide at least one PWM drive signal to one or more electronic switches of a switching stage based on the clock signal.

Description

[0001] Cross-reference to related applications

[0002] This application claims priority to Italian patent application No. 102021000017048, filed on June 29, 2021, which is incorporated herein by reference. Technical Field

[0003] This manual relates to electronic converter circuits, such as switching voltage regulator circuits. This manual also relates to power management integrated circuits (PMICs). Background Technology

[0004] Switching DC-DC converters (or voltage regulators) can operate using a constant on-time (COT) control mode. COT envisions comparing the rate of decline of the voltage level output by the DC-DC converter to a reference threshold, thereby adjusting the output voltage level based on this ripple.

[0005] A first method suitable for COT operation is disclosed, for example, in U.S. Patent No. 8,963,519,B2, which discloses a switching voltage regulator including a comparator module and a control module. The comparator module is configured to receive a reference voltage and a feedback voltage and generate a comparison signal based on the difference between the reference voltage and the feedback voltage. The control module is configured to generate a gain control threshold signal based on at least one of the reference voltage and the feedback voltage. The control module can be configured to control the duration of a PWM pulse based on at least one of the reference voltage and the feedback voltage; the feedback voltage can be the regulated output voltage of the switching voltage regulator.

[0006] Another method for COT control mode operation is used in EP3026893A1, which discusses a method for controlling a multiphase interleaved converter. This method includes the steps of: detecting when a change in load applied to the output terminals of the converter occurs; simultaneously activating all phases of the converter; and resuming the drive of the interleaved phase shift to restart normal operation of the converter. A controller for performing this method is also described.

[0007] Existing solutions for COT control mode operation of switching voltage regulators have one or more of the following limitations:

[0008] It exhibits a constant small-signal (modulator) gain, and therefore has a fixed loop bandwidth to respond to load transients (i.e., small-signal changes in the output voltage level).

[0009] Due to the fixed bandwidth, the regulator's dynamic performance is limited.

[0010] If the increased load causes a negative change in the output voltage level, the modulator may change the duty cycle by acting on the switching frequency of the converter, which is undesirable.

[0011] As the desired target bandwidth (GBWP) increases, the presence of additional singularities in the signal path may reduce the phase margin of the loop.

[0012] This may increase complexity and static consumption, for example, due to strict limitations on the performance of circuit components or due to the introduction of nonlinear secondary loops and additional passive components (internal or external) to achieve high-pass filtering of the output voltage.

[0013] Nonlinear solutions are difficult to derive from analytical design methods.

[0014] Due to power usage, it may not be suitable for low-power applications.

[0015] It may be sensitive to the shape of the (output) ripple. Summary of the Invention

[0016] The embodiments help to overcome the above limitations.

[0017] One or more embodiments relate to a corresponding electronic converter.

[0018] One or more embodiments relate to a corresponding method.

[0019] One or more embodiments may present one or more of the following advantages:

[0020] This provides the possibility of locally changing the modulator gain.

[0021] It is beneficial for providing boost voltage for positive load transients.

[0022] This enables a faster response and lower voltage drop in the regulated output voltage, which helps to handle undervoltage faults and reduces the need for output capacitor arrays to control output voltage drop.

[0023] The output voltage drop in response to sustained positive load transients is mitigated.

[0024] Circuit design is largely independent of load transient profiles.

[0025] Reduced circuit complexity, size, power consumption, and implementation cost.

[0026] The number of active blocks in the error signal path is also reduced.

[0027] The restrictions on the performance of the circuit blocks have been relaxed, which helps to maintain the stability of the main control loop. Attached Figure Description

[0028] One or more embodiments will now be described with reference to the accompanying drawings, which are merely non-limiting examples, in which:

[0029] Figure 1 Example diagrams are shown of an embodiment of the architecture of an electronic converter circuit according to the present disclosure;

[0030] Figure 2 yes Figure 1 A diagram of an exemplary embodiment of a portion of the diagram;

[0031] Figure 3 yes Figure 1 A diagram of an exemplary embodiment of another part of the diagram;

[0032] Figure 4A and Figure 4B It is a timing diagram of signal examples in one or more embodiments;

[0033] Figure 5A This is a comparison example diagram of the transfer function of the circuit according to this disclosure with a benchmark solution;

[0034] Figure 5B This is an example diagram of the frequency response of an electronic converter circuit according to the present disclosure;

[0035] Figure 6A and Figure 6B This is an example diagram of a method for operating an electronic converter circuit according to this disclosure; and

[0036] Figure 7 This is an example graph showing the performance benchmark of the solution based on this disclosure. Detailed Implementation

[0037] In the following description, one or more specific details are set forth to provide a thorough understanding of examples of embodiments of this specification. Embodiments may be obtained without one or more specific details, or using other methods, components, materials, etc. In other instances, known structures, materials, or operations are not detailed or described in order to avoid obscuring certain aspects of the embodiments.

[0038] References to “embodiment” or “one embodiment” within the framework of this specification are intended to indicate that a particular configuration, structure, or feature described with respect to that embodiment is included in at least one embodiment. Therefore, phrases such as “in an embodiment” or “in one embodiment” that may appear in one or more places in this specification do not necessarily refer to one and the same embodiment.

[0039] Furthermore, specific configurations, structures, or characteristics can be combined in any suitable manner in one or more embodiments.

[0040] The attached diagram is a simplified version and is not an exact scale.

[0041] In all the accompanying drawings, similar parts or elements are indicated by similar reference symbols / numerals, and for the sake of brevity, the corresponding descriptions will not be repeated.

[0042] The references used herein are provided for convenience only and therefore do not limit the scope of protection or the scope of the embodiments.

[0043] For simplicity, the same reference symbols may be used in the following detailed description to represent both nodes / lines in a circuit and signals that may appear at that node or line.

[0044] like Figure 1 As shown, the voltage regulator circuit 10 includes:

[0045] At least one input node V IN It is configured to couple to the mains power supply (referred to as AC power) to receive the input power signal V from it. IN ;

[0046] At least one output node V OUT It is configured to couple to load Z L To provide it with an output voltage level V OUT ,

[0047] Switching circuit block 11 includes coupling (e.g., direct) at output node V OUT With input node V IN A pair of electronic switches LS and HS (and their current paths) are configured to receive a power supply signal V. IN Furthermore, the switching signal is provided as an output (e.g., based on the control signal PM) to the switching node SW, which is located between the electronic switches LS and HS.

[0048] Specifically, the electronic switch HS is coupled (e.g., directly) to the (input) node V. IN The high-side switch is connected to the switch node SW, and the electronic switch LS is a low-side switch connected (e.g., directly) between the switch node SW and ground GND.

[0049] In the example considered, the (high-side) switch HS and the (low-side) switch LS are therefore configured to couple the switching node SW to the output node V. OUT A half-bridge to ground (GND). For example, switches LS and / or HS are typically transistors, such as n-channel or p-channel metal-oxide-semiconductor field-effect transistors (nMOS or pMOS FETs).

[0050] like Figure 1As shown, voltage regulator 10 includes coupling (e.g., direct) at switching node SW and output node V. OUT At least one inductor L between, and connected (e.g., directly) at the output node V OUT At least one capacitor C between the capacitor and ground (GND) OUT .

[0051] like Figure 1 As shown, the converter circuit 10 also includes a feedback branch fb, which will output node V OUT Coupled to control arrangements 12 and 14, which are configured to provide a control signal PM to drive switches LS and HS to regulate the output voltage level, as previously described. For example, switches LS and HS have corresponding control nodes coupled to corresponding drive circuits 110 and 112, which control the state of the corresponding switches based on the control signal PM.

[0052] In the example under consideration, control arrangements 12, 14 include:

[0053] Reference voltage node V REF It is configured to receive reference voltage level V. REF Reference voltage level V REF For example, equal to the DC operating point value or signal level.

[0054] Compensator circuit block 12 is coupled to the reference voltage node V. REF And it is configured to receive a reference voltage level V from it. REF The compensator circuit block 12 is also coupled to the output node V via the feedback branch fb. OUT The compensator circuit block 12 is configured to provide an indication of the regulated output voltage V to the modulator circuit block 14. OUT Relative to reference voltage V REF The compensator circuit block 12 is also configured to provide stability to the modulator circuit block 14, for example, by introducing zeros and singularities within the voltage regulation loops 12 and 14.

[0055] Modulator circuit block 14 is coupled to the input voltage node V. IN Compensator circuit block 12 and reference voltage node V REF Modulator circuit block 14 is configured to receive input voltage level V from the corresponding node. IN Compensation signal COMP and reference voltage level V REF And the control signal PM is provided to the switching circuit block 11.

[0056] Specifically, the compensator circuit block 12 may include an operational amplifier 120, which has a coupling to the reference voltage node V.REF The amplifier 120 has a first (e.g., non-inverting) node and a second (e.g., inverting) node coupled to the feedback branch fb, for example, arranged via voltage dividers R1 and R4, and an output node that is inversely coupled to the second input node and has a certain amplification gain Av.

[0057] like Figure 1 As shown, the modulator circuit block 14 includes:

[0058] Voltage-controlled oscillator (VCO) circuit block 20 is configured to receive the compensation signal COMP and the voltage reference level V. REF To generate clock signal CK, and

[0059] PWM signal generator circuit block 30, coupled to VCO circuit block 20 and configured to receive clock signal CK from it, is configured to generate pulse width modulation (PWM) control signal PM with a duty cycle δ (i.e., the signal period T at the first "active" level). SW A small portion of T ON Based on the switching frequency and compensation signal COMP set in CK in 20, the PWM signal generator circuit block 30 is also configured to provide the control signal PM to the switching circuit 11, and in particular to the drive circuits 110 and 112 of the half-bridge transistor arrangement HS and LS.

[0060] For example, when the value of the control signal PM is "1", the drive circuit 110 determines that the high-side MOSHS is turned on for a period of time T. ON The time interval T ON The total switching period T SW It is a small part and is determined based on the duty cycle δ of the control signal PM.

[0061] For example, in response to load Z L Changes in, such as its increase, affect the output voltage level V. OUT It can be relative to the regulated output voltage V OUT The value changes according to the expected value. This change can be detected by the compensator 12, and the modulator 14 can change the switching period of the switching arrangement 11 in response to the detected change, thereby adjusting the drive signal PM and restoring the regulated output voltage level V. OUT .

[0062] like Figure 1 As shown, for example, in the frequency domain:

[0063] The average voltage at the switching node SW Define a first (especially small-signal) transfer function between the voltage of the compensation signal COMP and the signal. as well as

[0064] A second (especially small-signal) transfer function dδ / dCOMP can be defined between the change in the duty cycle δ of the control signal PM and the compensation signal COMP.

[0065] For example, the first transfer function This can be expressed as the second transfer function dδ / dCOMP multiplied by the input voltage V. IN The product of.

[0066] These transfer functions dδ / dCOMP can be used to discuss the working principle of one or more embodiments, as described below.

[0067] In one or more embodiments, the modulator circuit 14 is configured to present a (small-signal) transfer function between the switching node SW (the average voltage at the switching node SW) and the compensation signal COMP, the (small-signal) transfer function being relative to the compensation signal COMP with respect to the reference voltage V. REF The reciprocal (DC) of the value is proportional to the second power, as described below.

[0068] like Figure 2 As shown, the VCO circuit block 20 includes:

[0069] Operational amplifier 200 is configured to receive voltage reference level V. REF And to the voltage reference level V REF Applying current conversion, operational amplifier 200 has a voltage reference level V that is configured to receive the voltage. REF The first (e.g., non-inverting) node, coupled to the output node, and (preferably finely adjustable) resistor R VCO The second (e.g., the opposite) node,

[0070] The bias branch includes a current generator 202, which is configured to generate current as flowing through resistor R. VCO A copy of the current (e.g., multiplied by some mirror factor K) MIR ),

[0071] Capacitor C VCO It is coupled to current generator 202 and configured to receive compensation signal COMP.

[0072] Comparator circuit block 204 has coupling to current generator 202 and capacitor C VCO The first (e.g., non-inverting) node, and coupled to the threshold level V TH (with reference voltage V) REF The value, for example, V TH =K VCO *V REFThe second (e.g., inverting) node of the VCO block 20, wherein the comparator circuit block 204 in the VCO block 20 is configured to receive the integration signal VCO_RAMP at the first node and perform integration of the VCO_RAMP with a reference threshold level V TH The comparison is used to provide a clock signal CK as the result of the comparison. The clock signal CK is provided in response to the integral signal VCO_RAMP crossing the reference threshold level V. TH The signal VCO_RAMP, which has a first value (e.g., "1"), fails to reach the reference threshold level V in response to the integral signal VCO_RAMP. TH And has a second value (e.g., "0").

[0073] like Figure 2 As shown, the output node of comparator circuit block 204 is coupled to a switch (e.g., a transistor) M. VCO The switch (e.g., transistor) M VCO It has a control node configured to receive a clock signal CK and a current path passing through it, which is configured to be on to bypass capacitor C. VCO This ensures that when the voltage VCO_RAMP reaches the threshold level V TH At that time, the output of comparator circuit block 204 changes its state, causing the output clock pulse CK to reset (again) capacitor C. VCO And make the signal VCO_RAMP equal to the compensation signal COMP output by the compensator circuit block 12.

[0074] In such Figure 2 In an alternative embodiment of the VCO circuit block 20 shown, the (e.g., non-inverting) input node of the first amplifier stage 200 can receive a compensation signal COMP from the compensator circuit block 12. For example, this can further sacrifice the equalization DC gain (e.g., V0). OUT / COMP=PART) and the AC (small signal) transfer function of modulator circuit block 14 The possibility of increasing modulator gain by an additional constant factor is at the cost of this.

[0075] In such Figure 2 In an alternative embodiment of the VCO circuit block 20 shown, the (e.g., non-inverting) input node of the comparator circuit block 204 can be coupled to the threshold V. TH The other (e.g., inverting) input node of comparator circuit 204 can be coupled to intermediate current generator 202 and capacitor C. VCO For example, this results in the threshold V acting on amplifier 204. TH Instead of modulating the amplitude of the VCO ramp by acting on the "base" of the VCO_RAMP signal, as described below, this may come at the cost of negative modulator gain, potentially leading to reduced system stability.

[0076] like Figure 3 As shown, the control signal generation block 30 receives the clock signal CK generated from the VCO circuit block 20 and the input voltage level VIN, and is configured to change the duty cycle of the control signal PM based on these signals, thereby setting the T value of the high-side transistor HS in the switch arrangement 11. ON time.

[0077] like Figure 3 As shown, circuit block 30 includes:

[0078] Operational amplifier 300 is configured to receive input voltage V IN (Optionally using factor K) IN (Scaled), and to the input voltage V IN Applying current conversion, operational amplifier 300 is configured to receive input voltage level V. IN The first (e.g., non-inverting node), and the resistor R coupled to the output node (preferably finely adjustable). TON The second (e.g., the opposite) node,

[0079] The bias branch includes a current generator 302, which is configured to provide current flowing through resistor R. TON A copy of the current (e.g., multiplied by some mirror factor K') MIR ),

[0080] Capacitor C TON Coupled to current generator 302 and connected to ground, the capacitor is configured to provide a voltage signal TON_RAMP, for example, by integrating the current from generator 302.

[0081] Comparator circuit block 304 has a coupling between current generator 302 and capacitor C TON The first (e.g., non-inverting) node in the middle, and coupled to the threshold level V TH2 (with reference voltage V) REF The value, for example, V TH2 =K TON *V REF The second (e.g., inverting) node of the comparator circuit block 304 is configured to sense across capacitance C. TON The integral signal TON_RAMP is then integrated with the reference threshold level V. TH2 The comparison is based on the comparison signal COMP_TON, which is provided in response to the integral signal TON_RAMP crossing the reference threshold level V. TH2The system with a first value (e.g., "1") and which fails to reach the reference threshold level V in response to the integral signal TON_RAMP is in operation. TH2 And has a second value (e.g., "0"). Figure 3 As shown, the PWM signal generator circuit block 30 also includes a logic circuit block 306, which is configured to receive a clock signal CK from the VCO circuit block 20 and a comparison signal COMP_TON from the comparator circuit block 304. The logic circuit block 306 is configured to provide a control signal PM based on the clock signal CK and the COMP_TON signal, as described below.

[0082] like Figure 3 As shown, logic block 306 is also coupled to a capacitor C configured to... TON The discharge switch allows the voltage TON_RAMP to reach the threshold level V. TH2 At that time, the output of the TON comparator circuit block 304 changes its state and its output signal COMP_TON reset capacitor C TON (and therefore the reset signal TON_RAMP).

[0083] Circuit block 30 applicable to one or more embodiments is discussed in document US 8963 519 A1, assigned to STMicroelectronics.

[0084] like Figure 4A As shown, the signal VCO_RAMP sensed at the second input node of the comparator circuit block 204 in the PWM circuit block 20 has a reference voltage level V REF The fixed slope of the compensation signal COMP (direct) modulated signal VCO_RAMP is used to modulate the compensation signal COMP output from the compensator circuit 12. As a result, for example, in response to a sudden increase in the output load current (and the resulting decrease in the output voltage), the compensation signal COMP increases; this further leads to an increase in the switching frequency of the switching arrangement 11.

[0085] Specifically, VCO circuit block 20 generates a clock signal CK, which determines the switching period (reciprocal of the frequency) T of regulator circuit 10. SW It can be represented as:

[0086]

[0087] As shown in this paper, the clock signal CK has a clock period T that varies linearly with the feedback signal COMP. SW The feedback signal COMP indicates that the output voltage V has been adjusted. OUT Relative to the above reference voltage V REF The changes.

[0088] like Figure 4B As shown, the clock signal CK triggers the "on" time interval T (programmable length). ON The start of the time interval T ON This continues until the signal TON_RAMP in the PWM signal generator circuit block 30 reaches the reference threshold V. TH2 For example, the conduction time interval can be expressed as:

[0089]

[0090] As a result, the frequency response of the voltage loop shows the closed-loop bandwidth, and the duty cycle δ of the control signal PM output by logic block 306 can be expressed as:

[0091]

[0092] The second small-signal transfer function of modulator circuit block 14 (Also known as modulator gain GMOD) can be expressed as (e.g., by differentiating the duty cycle "δ" relative to the compensation signal COMP):

[0093]

[0094] For example, the first small-signal transfer function This can be expressed as the modulator gain GMOD multiplied by the input voltage V. IN The product of:

[0095]

[0096] like Figure 5A As shown, based on the above expression, the small-signal transfer function There is a hyperbolic relationship between the compensation signal COMP value and the compensation signal value (in Figure 5A (Represented by a chain of circles with black circles). Conversely, the conventional solution presents a different relationship (in...). Figure 5A (Represented by a chain of circles with white circles). Therefore, if the compensation signal COMP responds to the regulated output voltage V OUT The decrease increases (e.g., in) Figure 5A (represented on the horizontal axis), this leads to a decrease in the absolute value of the VCO ramp amplitude, for example, with the factor (K). VCO The modulator gain GMOD is proportional to VEF-COMP, therefore the modulator gain GMOD is proportional to VEF-COMP. IN The product between (in) Figure 5A (represented by the vertical axis) shows a quadratic growth.

[0097] like Figure 5BAs shown, the operation of feedback loops 12 and 14 can be represented by the total loop gain GLOOP in the frequency domain:

[0098]

[0099] like Figure 5B As shown, the reactance component LC OUT The complex conjugate pole pairs (represented by dashed lines) are compensated via compensation circuit block 12 (represented by dotted lines). The dominant pole corresponds to the pole pair associated with the integral part of the compensator, which is limited by the finite open-loop gain of the error amplifier and the feedback splitting factor given by R1 and R4. For example, the unity-gain bandwidth UGBW of loops 12 and 14 can be expressed as the DC gain multiplied by the frequency of the dominant pole:

[0100]

[0101] Therefore, the frequency response of the voltage loop shows that it is related to the product GOM D·V IN Proportional closed-loop bandwidth. For example, this would be the term... The quadratic relation is extended to the frequency domain.

[0102] like Figure 5B As shown, the bandwidth BW of the loop gain GLOOP GL Based on the output voltage V OUT Local changes due to disturbances.

[0103] For example:

[0104] The output voltage V has been adjusted OUT In the event of a (sudden) drop and a subsequent increase in the compensation signal COMP, resulting in a faster loop response, the bandwidth (temporarily) changes from BW2 to BW3.

[0105] The output voltage V has been adjusted OUT When the loop response speed is locally reduced due to a sudden increase and a corresponding decrease in the compensation signal COMP, the bandwidth (temporarily) changes from BW2 to BW1.

[0106] Note that, according to Figure 5A The quadratic trend shown indicates that the increase in bandwidth is greater than the corresponding decrease in the change of the compensation signal COMP from its DC operating point.

[0107] like Figure 5A , Figure 5B As shown in Figure 6, the performance of the modulator circuit 14 may vary slightly depending on whether the load transient change is positive or negative (i.e., increasing or decreasing).

[0108] like Figure 6A As shown:

[0109] At the first time t1, a positive load (current) change (represented by a solid line) is detected via feedback chains 12 and 14, and

[0110] At the second time t2, the change in negative load (current) is detected via feedback chains 12 and 14.

[0111] like Figure 6B As shown:

[0112] At time t1, the feedback chain responds to the output load Z. L The change is triggered to limit its change to the first limit value V. OUT - ,

[0113] At time t2, feedback chains 12 and 14 respond to the output load Z. L The change is triggered again to limit its change to the second limit value V. OUT + .

[0114] like Figure 6B As shown, the first limit value V OUT - Second limit value V OUT + They can be different; this defines circuit 10 relative to... Figure 6A and Figure 6B The "asymmetrical" behavior of concepts represented by dashed lines in the middle.

[0115] like Figure 5A and Figure 6B As shown, the increase in modulator gain during positive load transients is related to the bandwidth of regulation loops 12 and 14, which are locally modulated to a higher value. This results in better performance compared to existing solutions, with the output voltage V... OUT The decrease is even lower. Conversely, the reduction in bandwidth relative to the decrease in negative load transients makes modulator 14 only slightly less responsive than existing solutions.

[0116] Figure 7 This shows that within a certain amplitude range (e.g., ΔI) LOAD Within the range of 1.875A to 7.5A and over a duration (especially Δt approximately 1μs, 2μs, ..., 5μs), the output voltage V corresponds to a step change in load (current). OUT The deviation from its adjusted (DC) value (e.g., V) OUT -V OUT - (The difference). For example, Figure 7 As shown, the bandwidth increase during positive load transients can also compensate for faster (positive) load transients with the same load change step size, thereby reducing the larger Vb in existing solutions.OUT The decline (indicated by dashed lines) is particularly relevant to the document US 8 963 519 B2 discussed above.

[0117] As shown in this paper, modulator circuit block 14 can increase its bandwidth (resulting in a smaller local VCO ramp) by allowing a larger deviation of the compensator output voltage COMP from its nominal DC value. This results in a smaller VCO ramp during positive load steps compared to known solutions. OUT The decrease is relatively low, which is almost unrelated to the load transient signal curve.

[0118] One or more embodiments may provide a switching frequency F SW (Switching period T) SW Customizable adjustability (the reciprocal of the output voltage), for example, by selecting different target output voltages V. REF Or independent of the input power supply V IN The input power supply V IN This can be maintained by selecting a suitable DC operating point for modulator 14 according to this disclosure.

[0119] As mentioned earlier, the duty cycle δ can be expressed as the on-time T. ON With switching period T SW The ratio, or equivalently expressed as the on-time T of the PWM control signal PM generated for the control power section 11. ON and switching frequency F SW The product of the two. For example, the duty cycle δ can be set to be equal to the output voltage level V. OUT and input voltage level V IN The ratio, which can be expressed as:

[0120]

[0121] For a given duty cycle δ, a suitable modulator 14 helps maintain the above relationship and provides (custom) programmability.

[0122] For example, modulator 14 can be based on a constant on-time T ON The architecture is configured accordingly. For this purpose, a PWM signal generator circuit block 30 can be used to output a regulated voltage V for a given target. OUT Switching frequency F SW and input voltage V IN Set a constant on-time T ON For example, this can be achieved by rearranging the on-time T. ON The expression is used to derive:

[0123]

[0124] in It is a constant value, VTH2 =K TON ·V REF It is the reference threshold of PWM signal generator circuit block 30.

[0125] In one or more embodiments, the (customized) programmable on-time T ON The generated on-time T is provided by generating circuit 30. ON The generated conduction time T ON With the desired regulated output voltage V OUT Proportional to, and related to the target switching frequency F SW and input voltage level V IN Inversely proportional.

[0126] Rearrange the expression to "stack" all the constant scaling factors together, for example:

[0127]

[0128] in It is an effective conduction time parameter.

[0129] Consider a typical "simple" case where the scaling factor K TON It is singular, that is, K. TON =1, the selected V can be used OUT For conduction time T ON To program, for example, by letting V TH2 =V REF For example, the following expressions are true:

[0130]

[0131] PART is the voltage division factor of the resistor network of compensator circuit block 12.

[0132] For example, replacing V in the expression derived from the duty cycle. TH2 The expression yields:

[0133]

[0134] in It is a constant value for the conduction time, which leads to the acquisition of an effective conduction time constant. With switching frequency F SW Expressions between, for example:

[0135]

[0136] As shown in this article, adjusting the switching frequency F SW This includes adjusting the effective time constant of the PWM signal generator circuit block 30 according to the above expression.

[0137] Combined with support output voltage V OUT Switching frequency F SW Programmability and input voltage V IN As previously described, a similar analysis performed on the VCO circuit block 20 can be concluded regarding the independent PWM signal generator circuit block 30:

[0138]

[0139] Where τ VCO =C VCO R VCO It is an effective VCO constant.

[0140] Considering that VCO circuit block 20 promotes V OUT Exemplary cases of programmability, for example, when V TH =V REF At that time, the switching period T SW It can be represented as:

[0141]

[0142] In one or more embodiments, the switching frequency F is adjusted. SW This includes adjusting the effective VCO time constant of modulator circuit block 14 and / or adjusting the effective time constant of PWM signal generator circuit block 30.

[0143] Note that, as a result of the above discussion, the modulator gain in the absence of output change (i.e., under DC) is also a function of the effective time constant, i.e.:

[0144]

[0145] This could promote discussions about V OUT F SW or V IN Invariant loop stability for any programmed value.

[0146] In one or more embodiments, the scaling factor K VCO It can be used to adjust DC gain (e.g., V). OUT / COMP=PART) and the AC small-signal gain of compensator 12 The difference between them. For example, the quadratic correlation between the modulator gain GMOD and the output of the compensator COMP helps distinguish between the two, except when K VCO When =2, they are equal.

[0147] In one or more embodiments, the reference voltage V can be selected within a range limited by the digital-to-analog converter (DAC). REF For example, approximately 0 to 1.5 volts. This also limits the dynamic range of the voltage at the input of the comparator circuit block 204 in the VCO circuit block 20.

[0148] In one or more embodiments, the scaling factor K VCO It can be selected to have a value of approximately 1.5, resulting in a reference voltage threshold V. TH Within a range of approximately 0-2.25V, the (small signal) gain of modulator block 14 can be equal to twice the partition factor PART of compensator block 12.

[0149] In one or more embodiments, the resistive elements R1 and R4 in the compensator circuit block 12 can be selected to provide a voltage division factor PART in the range of approximately 1.25-2.5. Specifically, in single-range mode and with the output voltage value V OUT Within a range of approximately 0.5-1.875 volts, the lower limit of the range can be selected, while the upper limit of the PART range can be applied to the output voltage V. OUT The value is approximately 1.875-3.75 volts in dual-range mode.

[0150] For the chosen value of the scaling factor, such as K VCO =1.5, which follows the chosen value of the effective VCO time constant, for example

[0151] In one or more embodiments, the switching frequency can be selected from a set of frequency values, such as {0.50; 0.75; 1.00; 1.50} MHz. Therefore, the effective time constant of the VCO can be one (e.g., four) of the corresponding set of values ​​calculated as described above, such as {4.00; 2.66; 2.00; 1.33} μs.

[0152] For example, a fine-tunable resistor R can be used. VCO Select any one of these values ​​for modulator 14. Alternatively or additionally, a fine-tuning capacitor C can be used. VCO This reduces the variability of the high-frequency poles of the voltage-to-current converter amplifier 200, thus facilitating its stability analysis.

[0153] In one or more embodiments, the adjustable resistors of the VCO circuit block 20 and the PWM signal generator circuit block 30 can both be selected to have the same properties (e.g., R0). VCO =RT ON In this exemplary case, capacitor C VCO The value can be represented as:

[0154]

[0155] In the exemplary case under consideration, the corresponding effective on-time constant is It can have values ​​selected from a set of values, such as the value

[0156] For example, assume (for simplicity) a single-proportion on-time factor K TON =1, On-time generator C TON The capacitance can be expressed as:

[0157]

[0158] In one or more embodiments, capacitor C VCO The values ​​in the first group can be adjusted, for example, C. VCO = {15.0; 10.0; 7.50; 5.00} pF, and capacitor C TON The second set of values ​​C can be used. TON The value can be adjusted between {7.50; 5.00; 3.75; 2.50} pF.

[0159] In one or more embodiments, due to the mirror factor K MIR The existence of [something] can affect capacitor C. TON Use a reduced set of selectable values.

[0160] As shown herein, one method includes controlling a switching stage (e.g., 11) of an electronic converter (e.g., 10) according to the present disclosure via a circuit (e.g., 14) according to the present disclosure.

[0161] As shown herein, the electronic converter (e.g., 10) includes:

[0162] First node (e.g., V) IN It is configured to receive an input voltage (e.g., V) from an energy source. IN ),

[0163] Second node (e.g., V) OUT ), configured to direct to the load (e.g., Z) L Provides a stable output voltage (e.g., V). OUT ),

[0164] Load (e.g., Z) L It is coupled to a second node to receive the regulated output voltage from it.

[0165] The third node (e.g., SW) is coupled to a reactive network called ground (e.g., L, C). OUT ),

[0166] A first electronic switch (e.g., HS) and a second electronic switch (e.g., LS), the first electronic switch having a current path through it coupled between a first node and a third node, the second electronic switch having a current path through it coupled between a third node and a second node, and the first and second electronic switches having corresponding control nodes.

[0167] According to the (modulator) circuit of this disclosure (e.g., 14), the control nodes of the first and second electronic switches coupled to the switching stage are configured to operate based on a clock signal (e.g., CK), an input voltage level, and a reference voltage (e.g., V). REF It provides at least one pulse width modulation (PWM) drive signal (e.g., PM) to it.

[0168] As illustrated herein, a circuit (e.g., 14, 110, 112) is configured to drive one or more electronic switches (e.g., LS, HS) in the switching stage (e.g., 11) of an electronic voltage regulator (e.g., 10) to adjust the voltage according to the input node (e.g., V). IN The input voltage received at the output node (e.g., V) is used to... OUT The regulated output voltage is provided at the point, and the switching stage is configured to be coupled to a reactive network (e.g., L, C) called ground. OUT The circuit includes:

[0169] A voltage-controlled oscillator (VCO) circuit (e.g., 20) includes a first node (e.g., V) configured to receive a reference voltage. REF A second node (e.g., COMP) configured to receive a feedback signal (e.g., COMP) indicating a change in the regulated output voltage relative to a reference voltage, and configured to provide a clock period (e.g., T) SW The third node of the clock signal (e.g., CK), whose clock period is a function of the reference voltage and the feedback signal, and

[0170] A pulse width modulation (PWM) signal generator circuit (e.g., 30) includes a first node coupled to a VCO circuit and configured to receive a clock signal (e.g., CK) (which is a function of a reference voltage and a feedback signal), and a second node (e.g., K) configured to receive an input signal proportional to the input voltage signal. IN V IN ), and a third node configured to provide at least one PWM drive signal (e.g., PM) to one or more electronic switches of the aforementioned switching stage based on a clock signal, wherein the input signal is proportional to an input voltage signal and a reference voltage, and wherein the PWM signal generator circuit is configured to generate a signal with a duty cycle (e.g., δ = T). ON / T SWThe ratio between a small portion of the time period in which the PWM drive signal is at the first “active” level and the signal period, wherein the ratio is inversely proportional to the feedback signal indicating the change of the regulated output voltage relative to the aforementioned reference voltage.

[0171] As shown in this article, the VCO circuit includes:

[0172] Signal processing circuitry (e.g., 200, C) VCO M VCO ), coupled to the first input node and the second input node and configured to generate a first signal (e.g., VCO_RAMP) as a function of a feedback signal and a reference voltage, and

[0173] A comparator circuit (e.g., 204) includes a first input node (e.g., VCO_RAMP) coupled to a signal processing circuit and configured to receive a first signal therefrom, and a second signal (e.g., V) configured to receive a level proportional to a reference voltage. TH The second input node of ) (e.g., V) TH ), and output nodes (e.g., CK) configured to provide clock signals.

[0174] For example, the comparator circuit is configured to perform a comparison between the first signal and the second signal and generate a clock signal based on the comparison between the first signal and the second signal.

[0175] As shown in this document, the signal processing circuitry in the VCO circuit includes a current generator (e.g., 202) and a capacitor (e.g., C). VCO ) and transistors (e.g., M VCO The current generator is configured to generate a reference current based on a reference voltage level. The capacitor has a first capacitor node coupled to the current generator to receive the reference current therefrom and coupled to a second input node of the comparator circuit. The capacitor has a second capacitor node coupled to a second node of the VCO circuit to receive the aforementioned feedback signal therefrom. The transistor has a control node coupled to the output node of the comparator circuit to receive a clock signal therefrom, a first node coupled to the first capacitor node, and a second node coupled to the second capacitor node. The transistor has a current path passing through it between the first node and the second node, which is configured to selectively turn on and off in response to the clock signal having a first value and a second value, respectively. When the current path passing through the transistor is off or on in response to the clock signal having a first value and a second value, respectively, the capacitor is charged or discharged according to the aforementioned reference current generated by the current generator.

[0176] As shown in this document, the PWM signal generator circuit is configured to control the duty cycle (e.g., δ) of the PWM drive signal based on the reference voltage signal level, the input voltage signal, and the clock signal.

[0177] It will also be understood that the various individual implementation options shown in the accompanying drawings are not necessarily intended to be employed in the same combinations illustrated in the drawings. Therefore, one or more embodiments may employ these (otherwise non-mandatory) options individually and / or in different combinations relative to the combinations shown in the drawings.

[0178] Without prejudice to the fundamental principles and without departing from the scope of protection, details and embodiments may vary or even significantly differ from what has been described by way of example only. The scope of protection is defined by the appended claims.

Claims

1. A circuit comprising: The voltage-controlled oscillator (VCO) circuit includes: The first node is configured to receive the reference voltage; The second node is configured to receive a feedback signal, which is a comparison signal indicating a change in the regulated output voltage of the electronic voltage regulator relative to the reference voltage; and The third node is configured to provide a clock signal having a clock period based on the reference voltage and the comparison signal; and The pulse width modulation (PWM) signal generator circuit includes: The first node is coupled to the VCO circuit and configured to receive the clock signal; The second node is configured to receive an input signal proportional to the input voltage signal at the input node of the electronic voltage regulator; and The third node is configured to provide at least one pulse-width modulation (PWM) drive signal to one or more electronic switches of the switching stage of the voltage regulator based on the clock signal. The input signal is proportional to the input voltage signal and the reference voltage, and The at least one PWM drive signal has a duty cycle that is inversely proportional to the comparison signal indicating the change of the regulated output voltage relative to the reference voltage.

2. The circuit according to claim 1, The switching stage is coupled to the reactor network via a switching node, and The reactor network is connected to ground.

3. The circuit according to claim 2, The comparison signal has a DC operating point equivalent to the level of the reference voltage, and The average voltage at the switching node varies as a function of the comparison signal.

4. The circuit of claim 3, wherein the function is a function of the change in the level of the comparison signal relative to the reference voltage in the voltage domain.

5. The circuit according to claim 1, wherein the VCO circuit comprises: A signal processing circuit device, coupled to the first node and the second node, and configured to provide a first signal as a function of the comparison signal and the reference voltage; as well as The comparator circuit includes: A first input node is coupled to the signal processing circuit device and configured to receive the first signal; The second input node is configured to receive a second signal proportional to the level of the reference voltage; and The output node is configured to provide the clock signal. The comparator circuit is configured as follows: Compare the first signal with the second signal, and The clock signal is generated based on the comparison between the first signal and the second signal.

6. The circuit according to claim 5, wherein the signal processing circuit device comprises: A current generator is configured to generate a reference current based on the level of the reference voltage; as well as Capacitors, including: A first capacitor node, coupled to the current generator and configured to receive the reference current, and coupled to the first input node of the comparator circuit; and A second capacitor node, coupled to the second node of the VCO circuit and configured to receive the comparison signal; and Transistors, including: A control node is coupled to the output node of the comparator circuit and configured to receive the clock signal from the output node; The first node, coupled to the first capacitor node; and The second node is coupled to the second capacitor node, and the transistor has a current path through the transistor between the first node and the second node. The current path selectively turns on and off in response to the clock signal having a first value and a second value, respectively. When the current path through the transistor is either not conducting or conducting in response to the clock signal having the first value and the second value respectively, the capacitor is charged or discharged according to the reference current.

7. The circuit according to claim 5, The amplitude of the first signal is inversely proportional to the comparison signal, and The clock period of the clock signal varies as a function of the amplitude of the first signal.

8. The circuit of claim 1, wherein the PWM signal generator circuit is configured to control the duty cycle of the PWM drive signal based on the levels of the reference voltage signal, the input voltage signal, and the clock signal.

9. A voltage regulator, comprising: The first node is configured to receive input voltage from the energy source; The second node is configured to provide a regulated output voltage to the load; Switching nodes are coupled to a reactor network connected to ground. A first electronic switch and a second electronic switch, the first electronic switch having a current path through the first electronic switch coupled between the first node and the switch node, the second electronic switch having a current path through the second electronic switch coupled between the third node and the switch node, the first electronic switch and the second electronic switch having corresponding control nodes; as well as The circuit of claim 1, coupled to the control nodes of the first electronic switch and the second electronic switch, provides the at least one PWM drive signal based on the clock signal, the level of the input voltage, and the reference voltage.

10. A method for providing the at least one PWM drive signal to the switching stage of a voltage regulator according to claim 1.

11. A method for providing at least one pulse width modulation (PWM) drive signal, the method comprising: The reference voltage is received at the first node of the circuit; A feedback signal is received at the second node of the circuit. The feedback signal is a comparison signal indicating the change in the regulated output voltage of the electronic voltage regulator relative to the reference voltage. as well as At the third node of the circuit, the at least one PWM drive signal is provided to one or more electronic switches of the switching stage of the voltage regulator. The at least one PWM drive signal provided by the PWM signal generator circuit is based on a clock signal and an input signal proportional to the input voltage signal at the input node of the electronic voltage regulator. The clock signal provided by the voltage-controlled oscillator (VCO) circuit has a clock period based on the reference voltage and the comparison signal. The input signal is proportional to the input voltage signal and the reference voltage, and The at least one PWM drive signal has a duty cycle that is inversely proportional to the comparison signal indicating the change of the regulated output voltage relative to the reference voltage.

12. The method according to claim 11, The switching stage is coupled to the reactor network via a switching node, and The reactor network is connected to ground.

13. The method according to claim 12, The comparison signal has a DC operating point equivalent to the level of the reference voltage, and The average voltage at the switching node varies as a function of the comparison signal.

14. The method of claim 13, wherein the function is a function of the change in the level of the comparison signal relative to the reference voltage in the voltage domain.

15. The method of claim 11, wherein the at least one PWM drive signal includes the duty cycle based on the levels of the reference voltage signal, the input voltage signal, and the clock signal.

16. The method of claim 11, further comprising providing a first signal, as a function of the comparison signal and the reference voltage, to the comparator circuit of the VCO circuit by a signal processing circuit means of the VCO circuit.

17. The method of claim 16, further comprising: The first signal is received by the comparator circuit; The comparator circuit receives a second signal that is proportional to the level of the reference voltage; The comparator circuit compares the first signal with the second signal; as well as The clock signal is provided based on the comparison between the first signal and the second signal.

18. The method according to claim 16, The amplitude of the first signal is inversely proportional to the comparison signal, and The clock period of the clock signal varies as a function of the amplitude of the first signal.

19. The method of claim 16, wherein the VCO circuit includes a current generator for generating a reference current based on the level of the reference voltage.

20. The method of claim 19, further comprising: The reference current is received from the current generator by the capacitor of the VCO circuit; as well as The comparison signal is received by the capacitor. The transistor is coupled to the capacitor such that the control node of the transistor receives the clock signal, and the current path of the transistor coupled between the two nodes of the capacitor selectively turns on and off in response to the clock signal having a first value and a second value, respectively. When the current path through the transistor is either not conducting or conducting in response to the clock signal having the first value and the second value respectively, the capacitor is charged or discharged according to the reference current.

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