High-speed transmission system, signal repeater, and control method of signal repeater

Abstract

The present invention provides a high-speed transmission system, a signal repeater and a control method for the signal repeater. The high-speed transmission system includes a transmission device, a receiving device and a signal repeater. The signal repeater includes a terminal resistor. The high-speed receiving end and the high-speed transmitting end of the signal repeater are respectively coupled to the high-speed transmitting end of the transmission device and the high-speed receiving end of the receiving device. The signal repeater is coupled to the control signal transmission end of the transmission device and the control signal receiving end of the receiving device. The signal repeater monitors the control signal transmitted between the transmission device and the receiving device. The signal repeater determines whether to enter a sleep mode based on the control signal. The terminal resistor of the signal repeater is continuously coupled to the high-speed receiving end of the signal repeater in the sleep mode.

Description

Technical Field

[0001] The present invention relates to a transmission system, and more particularly to a high-speed transmission system, a signal repeater (redriver), and a control method of the signal repeater. Background Art

[0002] A signal repeater (Redriver, also known as Repeater) can improve the transmission quality of the signal between the transmitting device and the receiving device. For example, the signal repeater can be used in the Peripheral Component Interconnect Express (PCIe) bus. However, the signal repeater currently used in PCIe does not have an extremely low power consumption sleep mode. In order to save power, the previous technology would shut down the entire signal repeater. If the signal repeater is turned off directly, the terminal resistor of the signal repeater may not meet the PCIe specification. Furthermore, after shutting down the entire signal repeater, the startup time of the signal repeater may be too long to start again. Excessive startup time will cause the PCIe device to fail to connect or the PCIe to be disconnected.

[0003] It should be noted that the contents of the "Background Technology" section are used to help understand the present invention. Some (or all) of the contents disclosed in the "Background Technology" section may not be known to those skilled in the art. The contents disclosed in the "Background Technology" section do not mean that the contents have been known to those skilled in the art before the present invention is applied. Summary of the invention

[0004] The invention provides a high-speed transmission system, a signal repeater and a control method of the signal repeater, wherein the signal repeater has a sleep mode to reduce power consumption.

[0005] In an embodiment of the present invention, the high-speed transmission system includes a transmitting device, a receiving device and a signal repeater. The transmitting device has a first high-speed transmitting end and a first control signal transmission end. The receiving device has a first high-speed receiving end and a second control signal transmission end. The second control signal transmission end is coupled to the first control signal transmission end. The signal repeater includes a terminal resistor. The signal repeater is coupled between the transmitting device and the receiving device. The signal repeater has a second high-speed receiving end coupled to the first high-speed transmitting end of the transmitting device, and has a second high-speed transmitting end coupled to the first high-speed receiving end of the receiving device. The signal repeater is coupled to the first control signal transmission end and the second control signal transmission end. The signal repeater monitors the control signal transmitted between the first control signal transmission end of the transmitting device and the second control signal transmission end of the receiving device. The signal repeater determines whether to enter the sleep mode based on the control signal. The terminal resistor of the signal repeater is continuously coupled to the second high-speed receiving end of the signal repeater in the sleep mode.

[0006] In an embodiment of the present invention, the signal repeater includes a relay circuit, a terminal resistor, a switch and a monitoring circuit. The relay circuit has an input end coupled to a high-speed receiving end of the signal repeater. The output end of the relay circuit is coupled to a high-speed transmitting end of the signal repeater. The terminal resistor and the switch are connected in series between the high-speed receiving end of the signal repeater and a reference voltage. The monitoring circuit is coupled to a first control signal transmission end of a transmitting device and a second control signal transmission end of a receiving device. The monitoring circuit is used to monitor a control signal transmitted between the first control signal transmission end of the transmitting device and the second control signal transmission end of the receiving device to determine whether to enter a sleep mode. The monitoring circuit continuously turns on the switch in the sleep mode, and the monitoring circuit turns off the switch in the disconnect mode.

[0007] In an embodiment of the present invention, the control method includes: providing a signal repeater between a transmitting device and a receiving device, wherein a first high-speed transmitting end of the transmitting device and a first high-speed receiving end of the receiving device are respectively coupled to a second high-speed receiving end and a second high-speed transmitting end of the signal repeater; monitoring a control signal transmitted between a first control signal transmission end of the transmitting device and a second control signal transmission end of the receiving device through the signal repeater; determining whether the signal repeater enters a sleep mode based on the control signal; and causing the terminal resistor of the signal repeater to continue to be coupled to the second high-speed receiving end of the signal repeater in the sleep mode.

[0008] Based on the above, the high-speed transmission system, signal repeater and signal repeater control method described in the embodiments of the present invention can determine whether the signal repeater enters the sleep mode by monitoring the control signal transmitted between the transmitting device and the receiving device, and in the sleep mode, the terminal resistance of the signal repeater is continuously coupled to the high-speed receiving end of the signal repeater to couple to the high-speed transmitting end of the transmitting device, thereby reducing the power consumption of the signal repeater while maintaining the terminal impedance of the transmitting device.

[0009] In order to make the above features and advantages of the present invention more clearly understood, embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 FIG. 4 is a schematic diagram of a circuit block of a high-speed transmission system according to an embodiment of the present invention.

[0011] Figure 2 FIG. 4 is a circuit block diagram of a high-speed transmission system according to another embodiment of the present invention.

[0012] Figure 3 FIG. 4 is a circuit block diagram of a high-speed transmission system according to another embodiment of the present invention.

[0013] Figure 4 According to an embodiment of the present invention, Figure 3 The finite-state machine schematic diagram of the signal repeater is shown.

[0014] Figure 5 The present invention is a flowchart of a control method for a signal repeater according to an embodiment of the present invention.

[0015] Description of Reference Numerals

[0016] 100, 200, 300: High-speed transmission system

[0017] 110, 310: Transmission device

[0018] 120, 320: Receiving device

[0019] 130, 230, 330: signal repeater

[0020] 210: PCIe root complex device

[0021] 220: PCIe endpoint device

[0022] 240: Clock source

[0023] 311: Equalizer Circuit

[0024] 312: Driver circuit

[0025] 313: Signal Detector

[0026] 331: Relay circuit

[0027] 332: Monitoring Circuit

[0028] 333: Receiver Detector

[0029] 410, 420, 430, 440, 450: working mode

[0030] CLK_REF: reference clock signal

[0031] CLKREQ#: Clock request signal

[0032] CS: Control signal

[0033] EN:Enable signal

[0034] R1, R2: high-speed receiving end

[0035] RD: Detection signal

[0036] RT: terminal resistance

[0037] S1, S2: High-speed transmission end

[0038] S510, S520, S530, S540: Steps

[0039] SD: Valid detection signal

[0040] SW: Switch

[0041] t1, t2: control signal transmission terminal

[0042] VR: reference voltage DETAILED DESCRIPTION

[0043] The term "coupled (or connected)" used in the entire specification of this case (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device coupled (or connected) to a second device, it should be interpreted that the first device can be directly connected to the second device, or the first device can be indirectly connected to the second device through other devices or some connection means. The terms "first", "second", etc. mentioned in the entire specification of this case (including the claims) are used to name the components (element) or to distinguish different embodiments or ranges, and are not used to limit the upper or lower limit of the number of components, nor to limit the order of components. In addition, wherever possible, components / components / steps with the same number in the drawings and embodiments represent the same or similar parts. Components / components / steps using the same number or the same terminology in different embodiments can refer to the relevant descriptions of each other.

[0044] Figure 1 1 is a schematic diagram of a high-speed transmission system 100 according to an embodiment of the present invention. According to actual design, the high-speed transmission system 100 may be a Peripheral Component Interconnect Express (PCIe) system or other transmission systems. Figure 1 In the illustrated embodiment, the high-speed transmission system 100 includes a transmission device 110, a receiving device 120, and a signal repeater 130. The transmission device 110 has a high-speed transmission terminal S1 and a control signal transmission terminal t1. The receiving device has a high-speed receiving terminal R2 and a control signal transmission terminal t2. The signal repeater 130 is coupled between the transmission device 110 and the receiving device 120. For example, the high-speed receiving terminal R1 of the signal repeater 130 is coupled to the high-speed transmission terminal S1 of the transmission device 110, and the high-speed transmission terminal S2 of the signal repeater 130 is coupled to the high-speed receiving terminal R2 of the receiving device 120. According to design requirements, the signal repeater 130 can be provided in the form of a circuit board or a cable, which is not limited in this embodiment. For example, in some embodiments, the high-speed receiving terminal R2 of the receiving device 120 can be coupled to the high-speed transmission terminal S1 of the transmission device 110 through a cable, and the signal repeater 130 can be configured in this cable. In other embodiments, the transmitting device 110, the receiving device 120 and the signal repeater 130 may be three integrated circuits. In still other embodiments, the transmitting device 110 and the signal repeater 130 may be integrated into one integrated circuit, and the receiving device 120 may be another integrated circuit. In still other embodiments, the transmitting device 110 may be one integrated circuit, and the receiving device 120 and the signal repeater 130 may be integrated into another integrated circuit.

[0045] The control signal CS is transmitted between the control signal transmission terminal t1 of the transmitting device 110 and the control signal transmission terminal t2 of the receiving device 120. According to the actual design, in some embodiments, the transmitting device 110 can transmit the control signal CS to the control signal transmission terminal t2 of the receiving device 120 through the control signal transmission terminal t1. In other embodiments, the receiving device 120 can transmit the control signal CS to the control signal transmission terminal t1 of the transmitting device 110 through the control signal transmission terminal t2. In still other embodiments, not shown in FIG. Figure 1 Other circuits of the transmitter 110 may transmit a control signal CS to the control signal transmission terminal t1 of the transmitter 110 and the control signal transmission terminal t2 of the receiver 120. Based on the control signal CS, the transmitter 110 and / or the receiver 120 may determine whether to enter the power saving mode.

[0046] The signal repeater 130 can monitor the control signal CS transmitted between the control signal transmission terminal t1 of the transmitting device 110 and the control signal transmission terminal t2 of the receiving device 120. Based on the control signal CS, the signal repeater 130 can determine whether to enter the sleep mode. When the signal repeater 130 enters the sleep mode from the standby mode (normal operation state), the terminal resistor inside the signal repeater 130 will continue to be coupled to the high-speed receiving terminal R1 of the signal repeater 130, and most of the circuits inside the signal repeater 130 will be turned off to reduce the power consumption of the signal repeater 130. Because the terminal resistor of the signal repeater 130 is continuously coupled to the high-speed receiving terminal R1 of the signal repeater 130 in the sleep mode, the signal repeater 130 still complies with the terminal specification of the high-speed transmission system 100 in the sleep mode. After the signal repeater 130 returns to the standby mode (normal operation state) from the sleep mode, the recovery time of reactivating the signal repeater 130 can meet the time specification of the high-speed transmission system 100 .

[0047] For example, Figure 2 FIG. 2 is a schematic diagram of a high-speed transmission system 200 according to another embodiment of the present invention. Figure 2 In the illustrated embodiment, the high-speed transmission system 200 includes a PCIe root complex device 210, a PCIe endpoint device 220, and a signal repeater 230. According to the actual design, in some embodiments, Figure 2 The PCIe root complex device 210 shown may be Figure 1 An example embodiment of the conveying device 110 is shown, or Figure 2 The PCIe root complex device 210 shown may be Figure 1 An internal component of the delivery device 110 is shown. Figure 2The PCIe endpoint device 220 may be Figure 1 An example implementation of the receiving device 120 is shown, or Figure 2 The PCIe endpoint device 220 shown may be Figure 1 An internal component of the receiving device 120 shown. According to the actual design, Figure 2 The signal repeater 230 shown can refer to Figure 1 The relevant description of the signal repeater 130 shown in FIG. 1 is analogous to that of FIG. 1 , and (or) Figure 1 The signal repeater 130 shown can refer to Figure 2 The relevant description of the signal repeater 230 is analogous.

[0048] At Figure 2 In the illustrated embodiment, the high-speed transmission end S1 of the PCIe root complex device 210 can be coupled to the high-speed reception end R2 of the PCIe endpoint device 220 via a PCIe bus and a signal repeater 230. Figure 2 In the illustrated embodiment, the high-speed transmission system 200 further includes a clock source 240. The clock terminals of the PCIe root complex device 210 and the PCIe endpoint device 220 are commonly coupled to the output terminal of the clock source 240 to receive the reference clock signal CLK_REF. Figure 2 The clock request signal CLKREQ# can be Figure 1 An example implementation of the control signal CS is shown, or Figure 2 The clock request signal CLKREQ# can be Figure 1One of the components of the control signal CS shown. The PCIe root complex device 210 and / or the PCIe endpoint device 220 can send a clock request signal CLKREQ# that complies with the PCIe specification to the clock source 240 through the control signal transmission terminal. According to the clock request signal CLKREQ#, the clock source 240 can determine whether to generate a reference clock signal CLK_REF to the PCIe root complex device 210 and the PCIe endpoint device 220. For example, when the clock request signal CLKREQ# is at a first logic level (e.g., a high logic level), the reference clock signal CLK_REF is canceled, that is, the PCIe root complex device 210 and / or the PCIe endpoint device 220 enter a power saving mode (e.g., a L1.2 low power link state (LinkState) under the PCIe specification). When the clock request signal CLKREQ# is at a second logic level (e.g., a low logic level), the reference clock signal CLK_REF is provided to the PCIe root complex device 210 and the PCIe endpoint device 220, that is, the PCIe root complex device 210 and the PCIe endpoint device 220 both operate in a normal mode. The clock request signal CLKREQ# is a signal that complies with the PCIe specification, so the details of the clock request signal CLKREQ# are not repeated here.

[0049] In the present embodiment, the signal repeater 230 can monitor the clock request signal CLKREQ# (control signal CS) transmitted between the PCIe root complex device 210, the PCIe endpoint device 220 and the clock source 240. In this way, the signal repeater 230 can switch the working mode of the signal repeater 230 according to the clock request signal CLKREQ#. For example, in the present embodiment, when the clock request signal CLKREQ# is a first logic level (e.g., a high logic level), the signal repeater 230 can enter the sleep mode (in the sleep mode, the terminal resistor of the signal repeater 230 is continuously coupled to the high-speed receiving end R1 of the signal repeater 230). When the clock request signal CLKREQ# is a second logic level (e.g., a low logic level), the signal repeater 230 can end the sleep mode.

[0050] Figure 3 FIG. 4 is a circuit block diagram of a high-speed transmission system 300 according to yet another embodiment of the present invention. Figure 3 The high-speed transmission system 300 shown includes a transmitting device 310, a receiving device 320, and a signal repeater 330. According to the actual design, in some embodiments, Figure 2 The PCIe root complex device 210 shown may be Figure 3 An example embodiment of the conveying device 310 is shown, or Figure 2 The PCIe root complex device 210 shown may be Figure 3An internal component of the delivery device 310 is shown. Figure 2 The PCIe endpoint device 220 may be Figure 3 An example implementation of the receiving device 320 is shown, or Figure 2 The PCIe endpoint device 220 may be Figure 3 An internal component of the receiving device 320 shown. In other embodiments, Figure 3 The transmitting device 310 and the receiving device 320 can refer to Figure 1 The transmission device 110 and the receiving device 120 are described in detail by analogy, or Figure 1 The transmitting device 110 and the receiving device 120 can refer to Figure 3 The related descriptions of the transmitting device 310 and the receiving device 320 are analogous and will not be repeated here.

[0051] According to the actual design, in some embodiments, Figure 2 The signal repeater 230 shown can refer to Figure 3 The relevant description of the signal repeater 330 shown in FIG. 3 is analogous, and (or) Figure 3 The signal repeater 330 shown can refer to Figure 2 The relevant description of the signal repeater 230 shown in the figure is analogous. In other embodiments, Figure 3 The signal repeater 330 shown can refer to Figure 1 The relevant description of the signal repeater 130 shown in FIG. Figure 1 The signal repeater 130 shown can refer to Figure 3 The relevant description of the signal repeater 330 shown in the figure is analogous. Figure 3 In the illustrated embodiment, the signal repeater 330 includes a repeater circuit 331, a monitoring circuit 332, a terminal resistor RT, and a switch SW. The monitoring circuit 332 may include a microcontroller or other control / processing circuits.

[0052] The terminal resistor RT and the switch SW can be connected in series between the high-speed receiving terminal R1 of the signal repeater 330 and the reference voltage VR. For example, the first end of the terminal resistor RT is coupled to the reference voltage VR, the first end of the switch SW is coupled to the second end of the terminal resistor RT, and the second end of the switch SW is coupled to the high-speed receiving terminal R1 of the signal repeater 330. It must be noted here that Figure 3 The connection method of the terminal resistor RT and the switch SW shown is only one embodiment. In other embodiments, the positions of the terminal resistor RT and the switch SW can be interchanged or coupled to the high-speed receiving terminal R1 in other forms, which is not limited in this embodiment. The reference voltage VR can be, for example, a ground voltage or other fixed voltage, which is not limited in this embodiment.

[0053] The input end of the relay circuit 331 is coupled to the high-speed receiving end R1 of the signal repeater 330. The output end of the relay circuit 331 is coupled to the high-speed transmitting end S2 of the signal repeater. The relay circuit 331 can increase the signal quality on the high-speed transmission channel between the transmitting device 310 and the receiving device 320.

[0054] The monitoring circuit 332 can monitor the control signal CS transmitted between the control signal transmission terminal of the transmitting device 310 and the control signal transmission terminal of the receiving device 320 to determine whether the signal repeater 330 enters the sleep mode. In the application scenario where the transmitting device 310 and the receiving device 320 are PCIe devices, the control signal CS can include a clock request signal CLKREQ# and (or) other PCIe signals that comply with the PCIe specification. The monitoring circuit 332 can control the switch SW according to the control signal CS. When the control signal CS (e.g., the clock request signal CLKREQ#) is at a first logic level, the signal repeater 230 can enter the sleep mode; and when the control signal CS (e.g., the clock request signal CLKREQ#) is at a second logic level, the signal repeater 230 can end the sleep mode. When the signal repeater 330 is in the sleep mode, the monitoring circuit 332 can continuously turn on the switch SW, that is, the terminal resistor RT can be continuously coupled to the high-speed receiving terminal R1 of the signal repeater 330. When the signal repeater 330 ends the sleep mode and returns to the standby mode (normal operation state), the monitoring circuit 332 continues to turn on the switch SW. When the signal repeater 330 operates in either the standby mode or the active mode, the monitoring circuit 332 continues to turn on the switch SW. When the transmitting device 310 and / or the receiving device 320 are disconnected from the signal repeater 330, the signal repeater 230 may enter the disconnect mode. According to the actual design, in some embodiments, the monitoring circuit 332 may turn off the switch SW in the disconnect mode.

[0055] At Figure 3 In the illustrated embodiment, according to design requirements, the signal repeater 330 may further include a receiver detector 333. The receiver detector 333 is coupled to the high-speed transmitting end S2 of the signal repeater 330. The receiver detector 333 may detect whether the high-speed transmitting end S2 of the signal repeater 330 is coupled to the high-speed receiving end of the receiving device 320, and output a detection signal RD.

[0056] In this embodiment, the relay circuit 331 may include an equalizer circuit 311 and a driver circuit 312. The input end of the equalizer circuit 311 may be coupled to the high-speed receiving end R1 of the signal repeater 330. The equalizer circuit 311 may be used to optimize the transmission signal received by the signal repeater 330. The input end of the driver circuit 312 may be coupled to the output end of the equalizer circuit 311. The output end of the driver circuit 312 may be coupled to the high-speed transmitting end S2 of the signal repeater 330. Figure 3 In the illustrated embodiment, according to design requirements, the relay circuit 331 may further include a signal detector 313. The signal detector 313 is coupled to the output end of the equalizer circuit 311. The signal detector 313 may detect whether there is a valid signal at the output end of the equalizer circuit 311, and output a valid detection signal SD.

[0057] According to different design requirements, the blocks of the monitoring circuit 332, the receiver detector 333 and / or the signal detector 313 may be implemented in the form of hardware, firmware, software (i.e., program) or a combination of more than one of the above three.

[0058] In hardware form, the above-mentioned monitoring circuit 332, receiver detector 333 and / or signal detector 313 can be implemented as a logic circuit on an integrated circuit. The related functions of the above-mentioned monitoring circuit 332, receiver detector 333 and / or signal detector 313 can be implemented as hardware using hardware description languages ​​(such as Verilog HDL or VHDL) or other suitable programming languages. For example, the related functions of the above-mentioned monitoring circuit 332, receiver detector 333 and / or signal detector 313 can be implemented in various logic blocks, modules and circuits in one or more controllers, microcontrollers, microprocessors, application-specific integrated circuits (ASICs), digital signal processors (DSPs), field programmable gate arrays (FPGAs) and / or other processing units.

[0059] In software form and / or firmware form, the above-mentioned monitoring circuit 332, receiver detector 333 and / or signal detector 313 or related functions can be implemented as programming codes. For example, the above-mentioned monitoring circuit 332, receiver detector 333 and / or signal detector 313 are implemented using general programming languages ​​(such as C, C++ or assembly language) or other suitable programming languages. The programming codes can be recorded / stored in a "non-transitory computer readable medium". In some embodiments, the non-transitory computer readable medium includes, for example, a read-only memory (ROM), a tape, a disk, a card, a semiconductor memory, a programmable logic circuit and / or a storage device. The storage device includes a hard disk drive (HDD), a solid-state drive (SSD) or other storage devices. A central processing unit (CPU), a controller, a microcontroller or a microprocessor may read and execute the programming code from the non-temporary computer-readable medium, thereby implementing the related functions of the above-mentioned monitoring circuit 332, the receiver detector 333 and / or the signal detector 313.

[0060] Figure 4 According to an embodiment of the present invention, Figure 3 The finite state machine diagram of the signal repeater 330 is shown in FIG. Figure 3 and Figure 4 In the illustrated embodiment, the signal repeater 330 may have multiple operating modes and may switch the enabling state of the internal circuit components in different operating modes. Figure 4 In the illustrated embodiment, the operating modes of the signal repeater 330 may include an off mode (OFF) 410, a disconnect mode (DISCONNECT) 420, a standby mode (STAMDBY) 430, an active mode (ACTIVE) 440, and a sleep mode (SLEEP) 450. It should be noted that the operating modes described in this embodiment are only exemplary, and in other embodiments, the signal repeater 330 may also include other operating modes or have fewer operating modes.

[0061] In this embodiment, the signal repeater 330 can switch the working mode to the shutdown mode 410 or the disconnection mode 420 according to the external input enable signal EN. For example, when the signal repeater 330 receives the enable signal EN as disable, the signal repeater 330 can enter the shutdown mode 410 from any mode. In the shutdown mode 410, when the signal repeater 330 receives the enable signal EN as enable, the shutdown mode 410 can be terminated and the disconnection mode 420 can be entered.

[0062] In the disconnect mode 420, the signal repeater 330 may determine whether to switch the working mode of the signal repeater 330 from the disconnect mode 420 to the standby mode 430, or from the standby mode 430 to the disconnect mode 420 according to the detection signal RD output by the receiver detector 333. For example, when the detection signal RD output by the receiver detector 333 indicates that the high-speed transmission end S2 of the signal repeater 330 is coupled to the high-speed receiving end of the receiving device 320 and the signal repeater 330 is in the disconnect mode 420, the working mode of the signal repeater 330 may be switched from the disconnect mode 420 to the standby mode 430. When the detection signal RD output by the receiver detector 333 indicates that the high-speed transmission end S2 of the signal repeater 330 is not coupled to any receiving device and the signal repeater 330 is in the standby mode 430 (or the sleep mode 450), the working mode of the signal repeater 330 may be switched from the standby mode 430 (or the sleep mode 450) to the disconnect mode 420.

[0063] In the standby mode 430, the signal repeater 330 may determine whether to switch the working mode of the signal repeater 330 from the standby mode 430 to the actuation mode 440 according to the valid detection signal SD output by the signal detector 313. For example, when the valid detection signal SD output by the signal detector 313 indicates that the output of the equalizer circuit 311 is a valid signal (i.e., the high-speed receiving end R1 of the signal repeater 330 receives a valid signal from the transmission device 310) and the signal repeater 330 is in the standby mode 430, the working mode of the signal repeater 330 may be switched from the standby mode 430 to the actuation mode 440 (normal working mode). When the valid detection signal SD output by the signal detector 313 indicates that the equalizer circuit 311 does not output a valid signal (i.e., the high-speed receiving end R1 of the signal repeater 330 does not receive a valid signal from the transmission device 310) and the signal repeater 330 is in the actuation mode 440, the working mode of the signal repeater 330 may be switched from the actuation mode 440 back to the standby mode 430.

[0064] In the standby mode 430, the signal repeater 330 may determine whether to switch the working mode of the signal repeater 330 from the standby mode 430 to the sleep mode 450 according to the control signal CS transmitted between the transmitting device 310 and the receiving device 320. For example, when the control signal CS transmitted between the transmitting device 310 and the receiving device 320 is at the default first logic level and the signal repeater 330 is in the standby mode 430, the working mode of the signal repeater 330 may be switched from the standby mode 430 to the sleep mode 450. When the control signal CS transmitted between the transmitting device 310 and the receiving device 320 is at the default second logic level and the signal repeater 330 is in the sleep mode 450, the working mode of the signal repeater 330 is switched back from the sleep mode 450 to the standby mode 430. In addition, in the sleep mode 450, when the detection signal RD output by the receiver detector 333 indicates that the receiving device 320 originally coupled to the high-speed transmitting end S2 of the signal repeater 330 has been disconnected, the working mode of the signal repeater 330 can be switched from the sleep mode 450 back to the disconnection mode 420. In some embodiments, the power consumption of the signal repeater 330 in the sleep mode 450 can be less than the power consumption in the standby mode 430.

[0065] For example, the following Table 1 is a diagram illustrating an embodiment of the present invention. Figure 3 The table shows the enabled status of the internal circuit components of the signal repeater 330. The vertical axis in Table 1 represents Figure 3 The internal circuit components of the signal repeater 330 shown in Table 1 include a terminal resistor RT, an equalizer circuit 311, a driver circuit 312, a signal detector 313, and a receiving detector 333. The horizontal axis shown in Table 1 represents the working mode of the signal repeater 330, including Figure 4 The disconnect mode 420, the activation mode 440, the standby mode 430 and the sleep mode 450 are shown. The "X" shown in Table 1 indicates disable, turn off or disconnect. The "O" shown in Table 1 indicates enable, turn on or connect. The enabling states of the multiple circuit components shown in Table 1 are only one embodiment, and the present embodiment is not limited thereto.

[0066] Table 1: Relationship between the operating modes and the enabling of the internal components of the signal repeater 330

[0067]

[0068] Please refer to Figure 3 , Figure 4As shown in Table 1, in the present embodiment, when the signal repeater 330 is in the disconnection mode 420, for example, only the receiver detector 333 is enabled to detect the coupling state of the high-speed transmission terminal S2 of the signal repeater 330. In the disconnection mode 420, the switch SW is turned off (i.e., the terminal resistor RT is disconnected from the high-speed receiving terminal R1 of the signal repeater 330), and the equalizer circuit 311, the driver circuit 312, the signal detector 313 and the receiver detector 333 are disabled or turned off. When the signal repeater 330 is in the activation mode 440, the receiver detector 333 can be disabled to reduce the power consumption of the signal repeater 330 in the activation mode 440. In the activation mode 440, the switch SW is turned on (i.e., the terminal resistor RT is connected to the high-speed receiving terminal R1 of the signal repeater 330), and the equalizer circuit 311, the driver circuit 312 and the signal detector 313 are enabled or turned on.

[0069] When the signal repeater 330 is in the standby mode 430, for example, only the driver circuit 312 is disabled. In the standby mode 430, the switch SW is turned on (i.e., the terminal resistor RT is connected to the high-speed receiving terminal R1 of the signal repeater 330), and the equalizer circuit 311, the signal detector 313, and the receiver detector 333 are enabled or turned on. When the signal repeater 330 is in the sleep mode 450, the receiver detector 333 is enabled and the terminal resistor RT is connected to the high-speed receiving terminal R1 of the signal repeater 330 (i.e., the switch SW is turned on). In the sleep mode 450, the equalizer circuit 311, the driver circuit 312, and the signal detector 313 are disabled or turned off.

[0070] In other words, the equalizer circuit 311 in the signal repeater 330 is enabled in the actuation mode 440 and the standby mode 430, and is disabled in the disconnection mode 420 and the sleep mode 450. The driver circuit 312 is enabled in the actuation mode 440, and is disabled in the disconnection mode 420, the standby mode 430, and the sleep mode 450. The signal detector 313 is enabled in the actuation mode 440 and the standby mode 430, and is disabled in the disconnection mode 420 and the sleep mode 450. The receiver detector 333 is enabled in the disconnection mode 420, the standby mode 430, and the sleep mode 450, and may be disabled in the actuation mode 440. In the present embodiment, the monitoring circuit 332 may control the switch SW to continuously turn on the switch SW when the signal repeater 330 is in the sleep mode 450, the standby mode 430, and the actuation mode 440, and to turn off the switch SW in the disconnection mode 420. As a result, when the signal repeater 330 is in the sleep mode 450 , the relay circuit 331 can be disabled to reduce the power consumption of the signal repeater 330 while maintaining the terminal resistor RT enabled.

[0071] Figure 5FIG. 1 is a flow chart of a control method of a signal repeater according to an embodiment of the present invention. According to the actual design, Figure 5 The relevant instructions for the control method shown can be applied to Figure 1 The signal repeater 130 shown, Figure 2 The signal repeater 230 and (or) Figure 3 The signal repeater 330 is shown. Figure 1 The circuit block diagram shown in the figure assists in explaining Figure 5 Control method shown.

[0072] Please refer to Figure 1 and Figure 5 . Step S510 provides a signal repeater 130 between the transmitting device 110 and the receiving device 120. Among them, the high-speed transmitting terminal S1 of the transmitting device 110 is coupled to the high-speed receiving terminal R1 of the signal repeater 130, and the high-speed receiving terminal R2 of the receiving device 120 is coupled to the high-speed transmitting terminal S2 of the signal repeater 130. In step S520, the signal repeater 130 can monitor the control signal CS transmitted between the control signal transmission terminal t1 of the transmitting device 110 and the control signal transmission terminal t2 of the receiving device 120. In step S530, the signal repeater 130 can decide whether to enter the sleep mode 450 based on the control signal CS. In step S540, the signal repeater 130 can make the terminal resistance (for example Figure 3 The terminal resistor RT) is continuously coupled to the high-speed receiving terminal R1 of the signal repeater 130 in the sleep mode 450 .

[0073] In summary, the high-speed transmission system and the signal repeater described in the above embodiments can determine whether the signal repeater enters the sleep mode 450 by monitoring the control signal CS (e.g., the clock request signal CLKREQ#) transmitted between the transmitting device and the receiving device. In the sleep mode 450, the terminal resistor RT of the signal repeater can be continuously coupled to the high-speed receiving terminal R1 of the signal repeater. Under the premise of maintaining the terminal impedance of the high-speed receiving terminal R1, the power consumption of the signal repeater can be reduced as much as possible.

[0074] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A high-speed transmission system, characterized in that: The high-speed transmission system comprises: The transmission device has a first high-speed transmission end and a first control signal transmission end; A receiving device having a first high-speed receiving terminal and a second control signal transmission terminal, wherein the second control signal transmission terminal is coupled to the first control signal transmission terminal; and a signal repeater coupled between the transmitting device and the receiving device, wherein the signal repeater has a second high-speed receiving end coupled to the first high-speed transmitting end of the transmitting device, the signal repeater has a second high-speed transmitting end coupled to the first high-speed receiving end of the receiving device, and the signal repeater is coupled to the first control signal transmission end and the second control signal transmission end, The signal repeater monitors the control signal transmitted between the first control signal transmission terminal and the second control signal transmission terminal, and the signal repeater determines whether to enter the sleep mode based on the control signal. The signal repeater includes a terminal resistor, and the terminal resistor of the signal repeater is continuously coupled to the second high-speed receiving end of the signal repeater in the sleep mode.

2. The high-speed transmission system according to claim 1, characterized in that: The first high-speed transmitting end of the transmitting device is coupled to the first high-speed receiving end of the receiving device through a PCI Express bus and the signal repeater. The transmitting device includes a PCI Express root complex device, and the receiving device includes a PCI Express endpoint device.

3. The high-speed transmission system according to claim 1, characterized in that: The control signal includes a clock request signal that complies with the Peripheral Component Interconnect Express specification, the signal repeater enters the sleep mode when the clock request signal is at a first logic level, and the signal repeater ends the sleep mode when the clock request signal is at a second logic level.

4. The high-speed transmission system according to claim 1, characterized in that: The signal repeater also includes: a relay circuit having an input end coupled to the second high-speed receiving end of the signal repeater, wherein an output end of the relay circuit is coupled to the second high-speed transmitting end of the signal repeater; a switch, wherein a first end of the switch is coupled to a second end of the terminal resistor, a second end of the switch is coupled to the second high-speed receiving end of the signal repeater, and a first end of the terminal resistor receives a reference voltage; and The monitoring circuit is used to monitor the control signal transmitted between the transmitting device and the receiving device to determine whether to enter the sleep mode, wherein the monitoring circuit continuously turns on the switch in the sleep mode, and the monitoring circuit turns off the switch in the disconnection mode.

5. The high-speed transmission system according to claim 4, characterized in that: The monitoring circuit continuously turns on the switch in the standby mode and the actuation mode.

6. The high-speed transmission system according to claim 5, characterized in that: The signal repeater also includes: A receiver detector is coupled to the second high-speed transmitting end of the signal repeater, and is used to detect whether the second high-speed transmitting end of the signal repeater is coupled to the first high-speed receiving end of the receiving device, wherein the receiver detector is enabled in the disconnect mode, the standby mode, and the sleep mode, and the receiver detector is disabled in the actuation mode.

7. The high-speed transmission system according to claim 5, characterized in that: The relay circuit comprises: an equalizer circuit having an input terminal coupled to the second high-speed receiving terminal of the signal repeater, wherein the equalizer circuit is enabled in the activation mode and the standby mode, and the equalizer circuit is disabled in the disconnection mode and the sleep mode; and A driver circuit has an input end coupled to the output end of the equalizer circuit, wherein the output end of the driver circuit is coupled to the second high-speed transmission end of the signal repeater, the driver circuit is enabled in the actuation mode, and the driver circuit is disabled in the disconnect mode, the standby mode and the sleep mode.

8. The high-speed transmission system according to claim 7, characterized in that: The relay circuit also includes: A signal detector is coupled to the output end of the equalizer circuit, and is used to detect whether there is a valid signal at the output end of the equalizer circuit, wherein the signal detector is enabled in the actuation mode and the standby mode, and the signal detector is disabled in the disconnection mode and the sleep mode.

9. A signal repeater, characterized in that: The signal repeater comprises: a relay circuit having an input end coupled to a high-speed receiving end of the signal repeater, wherein an output end of the relay circuit is coupled to a high-speed transmitting end of the signal repeater; a terminal resistor and a switch, wherein a first end of the switch is coupled to a second end of the terminal resistor, a second end of the switch is coupled to the high-speed receiving end of the signal repeater, and a first end of the terminal resistor receives a reference voltage; and A monitoring circuit is coupled to a first control signal transmission terminal of a transmitting device and a second control signal transmission terminal of a receiving device, and is used to monitor a control signal transmitted between the first control signal transmission terminal and the second control signal transmission terminal to determine whether to enter a sleep mode, wherein the monitoring circuit continuously turns on the switch in the sleep mode, and the monitoring circuit turns off the switch in the disconnection mode.

10. The signal repeater according to claim 9, characterized in that: The control signal includes a clock request signal that complies with the Peripheral Component Interconnect Express specification, the signal repeater enters the sleep mode when the clock request signal is at a first logic level, and the signal repeater ends the sleep mode when the clock request signal is at a second logic level.

11. The signal repeater according to claim 9, characterized in that: The monitoring circuit continuously turns on the switch in the standby mode and the actuation mode.

12. The signal repeater according to claim 11, characterized in that: The signal repeater also includes: A receiver detector is coupled to the high-speed transmitting end of the signal repeater to detect whether the high-speed transmitting end of the signal repeater is coupled to the high-speed receiving end of the receiving device, wherein the receiver detector is enabled in the disconnect mode, the standby mode and the sleep mode, and the receiver detector is disabled in the actuation mode.

13. The signal repeater according to claim 11, characterized in that: The relay circuit comprises: an equalizer circuit having an input terminal coupled to the high-speed receiving terminal of the signal repeater, wherein the equalizer circuit is enabled in the activation mode and the standby mode, and the equalizer circuit is disabled in the disconnection mode and the sleep mode; and A driver circuit has an input end coupled to the output end of the equalizer circuit, wherein the output end of the driver circuit is coupled to the high-speed transmission end of the signal repeater, the driver circuit is enabled in the actuation mode, and the driver circuit is disabled in the disconnect mode, the standby mode and the sleep mode.

14. The signal repeater according to claim 13, characterized in that: The relay circuit also includes: A signal detector is coupled to the output end of the equalizer circuit, and is used to detect whether there is a valid signal at the output end of the equalizer circuit, wherein the signal detector is enabled in the actuation mode and the standby mode, and the signal detector is disabled in the disconnection mode and the sleep mode.

15. A control method for a signal repeater, characterized in that: The control method comprises: Providing the signal repeater between a transmitting device and a receiving device, wherein a first high-speed transmitting end of the transmitting device and a first high-speed receiving end of the receiving device are respectively coupled to a second high-speed receiving end and a second high-speed transmitting end of the signal repeater; monitoring the control signal transmitted between the first control signal transmission terminal of the transmitting device and the second control signal transmission terminal of the receiving device through the signal repeater; Determining whether the signal repeater enters a sleep mode based on the control signal; and The terminal resistor of the signal repeater is continuously coupled to the second high-speed receiving end of the signal repeater in the sleep mode.

16. The control method according to claim 15, characterized in that: The control method further comprises: When the signal repeater receives an enable signal indicating that the enable signal is disabled, the signal repeater enters a shutdown mode; and When the signal repeater receives the enable signal as enable, the signal repeater ends the shutdown mode and enters the disconnection mode.

17. The control method according to claim 15, characterized in that: The control method further comprises: When the detection signal indicates that the second high-speed transmitting end of the signal repeater is coupled to the first high-speed receiving end of the receiving device and the signal repeater is in a disconnection mode, the signal repeater enters a standby mode from the disconnection mode; and When the detection signal indicates that the second high-speed transmitting end of the signal repeater is not coupled to any receiving device and the signal repeater is in the standby mode or the sleep mode, the signal repeater enters the disconnect mode from the standby mode or the sleep mode.

18. The control method according to claim 15, characterized in that: The control method further comprises: When the valid detection signal indicates that the second high-speed receiving end of the signal repeater receives a valid signal from the transmitting device and the signal repeater is in a standby mode, the signal repeater enters an activation mode from the standby mode; and When the valid detection signal indicates that the second high-speed receiving end of the signal repeater has not received the valid signal from the transmitting device and the signal repeater is in the activation mode, the signal repeater enters the standby mode from the activation mode.

19. The control method according to claim 15, characterized in that: The control method further comprises: When the control signal is at a first logic level and the signal repeater is in a standby mode, the signal repeater enters the sleep mode from the standby mode; and When the control signal is at the second logic level and the signal repeater is in the sleep mode, the signal repeater enters the standby mode from the sleep mode.

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