A PCIe switch management apparatus, method and PCIe switch

Abstract

The application belongs to the technical field of PCIe communication, and particularly relates to a PCIe switch management device, a PCIe switch management method and a PCIe switch. Through the PCIe switch management device provided in the application, the cooperative control of PCIe switch links and power management can be realized, so that the conversion of low power consumption of the PCIe switch is realized. The device comprises a first control module, a second control module and a global power management module. The first control module is used for monitoring a first link state of a first link. The global power management module is used for generating a first control signal according to the first link state. The second control module is used for controlling the update of a second link state of a second link according to the first control signal. The updated second link state is the same as the first link state.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of PCIe communication, and particularly relates to a PCIe switch management device and method and a PCIe switch. BACKGROUND

[0002] The Peripheral Component Interconnect Express (PCIe) is widely applied to the fields of data collection and storage. The power states of a PCIe switch connected by a PCIe bus include device power states (D-states) and link power states (L-states).

[0003] The PCIe protocol defines two power management mechanisms, namely a PCI power management (PCI-PM) mechanism and an active state power management (ASPM) mechanism. The PCIe protocol defines device power states including a D0 state, a D1 state, a D2 state, a D3hot state, a D3cold state and the like. The PCIe protocol defines link power states including an L0 state, an L0s state, an L1 state, an L2 / 3ready state, an L2 state, an L3 state and the like. The ASPM mechanism works only in the D0 power state, and the possible link states thereof are L0, L0s and L1. The PCI-PM mechanism works in any power state. However, the PCIe protocol does not specifically describe how to implement low power consumption in the device when the PCIe switch enters a certain state, and therefore, it is urgent to provide a PCIe switch management method. SUMMARY

[0004] In view of this, the embodiments of the application provide a PCIe switch management device and method and a PCIe switch, which can realize low power consumption setting of a device PCIe switch under the premise of meeting the protocol requirements.

[0005] The first aspect of the embodiment of the application provides a PCIe switch management device, comprising a first control module, a second control module and a global power management module, the first control module is connected with a first PCIe device through a first interface, the second control module is connected with a second PCIe device through a second interface, a link between the first control module and the first PCIe device is a first link, and a link between the second control module and the second PCIe device is a second link; the first control module is used for monitoring a first link state of the first link; the global power management module is used for generating a first control signal according to the first link state; and the second control module is used for controlling a second link state of the second link to be updated according to the first control signal, and the updated second link state is the same as the first link state.

[0006] With reference to the first aspect, in a first possible implementation manner of the first aspect, when the first control module is an upstream port control module and the second control module is a downstream port control module, the first link state is L0s, and the control signal is usp_in_l0s; the second control module is specifically used for updating the second link state to L0s according to usp_in_l0s when a first preset condition is met; and the first preset condition comprises that there is no TLP or DLLP waiting to be sent in the upstream port, and the usp_in_l0s signal is at a high level.

[0007] With reference to the first aspect, in a second possible implementation manner of the first aspect, when the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L0s, and the control signal is all_dsp_in_rl0s; the second control module is specifically used for updating the second link state to L0s according to all_dsp_in_rl0s when a second preset condition is met; and the second preset condition comprises that there is no TLP or DLLP waiting to be sent in the downstream port, and the all_dsp_in_rl0s signal is at a high level.

[0008] With reference to the first aspect, in a third possible implementation manner of the first aspect, when the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L1 or a state with power consumption lower than L1, and the control signal is all_dsp_in_l1; the second control module is specifically used for updating the second link to L1 according to the control signal all_dsp_in_l1 when a third preset condition is met; and the third preset condition comprises that after a time when a receiving direction and a sending direction of the second link are both in L0s reaches a preset time length, the first link state is in a L1 ASMP or a state with power consumption lower than L1 ASMP, a TLP message being sent is sent completely, and a blocking signal is generated to prevent a new TLP message from being sent, so that a retransmission buffer on the second link is empty.

[0009] With reference to the first aspect, in a fourth possible implementation manner of the first aspect, the first control module is a downstream port control module, the second control module is an upstream port control module, the first link state is L1 or a state with power consumption lower than L1, and the control signal is a PM_ENTER_L1 DLLP; the second control module is specifically configured to update the second link to L1 according to the PM_ENTER_L1 DLLP when a fourth preset condition is met; the fourth preset condition includes that the time when the receiving direction and the sending direction of the second link are both in L0s reaches a preset time length, the first link state is in L1 ASMP or a state with power consumption lower than L1 ASMP, the sending of the TLP message being sent is waited to be completed, a blocking signal is generated to prevent a new TLP message from being sent, and the retransmission buffer on the sending link is emptied.

[0010] With reference to the first aspect, in a fifth possible implementation manner of the first aspect, the first control module is further configured to acquire a link control instruction sent by the first PCIe device; the global power management module is further configured to generate a second control signal according to the link control instruction; and the second control module is further configured to update the second link state according to the second control signal, and the updated second link state corresponds to the link control instruction.

[0011] With reference to the first aspect, in a sixth possible implementation manner of the first aspect, the first PCIe device is a root component device, and the second PCIe device is a PCIe terminal device; the link control instruction is used to instruct the second link state to be updated to an L2 or L3 state; the first PCIe device is a PCIe terminal device, and the second PCIe device is a root component device; and the link control instruction is used to instruct the second link state to be updated to an L1 state.

[0012] With reference to the first aspect, in a seventh possible implementation manner of the first aspect, when the first control module is a downstream port control module and the second control module is an upstream port control module, the second control module is configured to set the second interface from a P0 state to a P0s state and control an all_dsp_in_rl0 signal to be high when the first link state is L0s; when the first control module is an upstream port control module and the second control module is a downstream port control module, the second control module is further configured to set the second interface from a P0 state to a P0s state and control an usp_in_rl0 signal to be high when the first link state is L0s; and when the first link or the second link is updated to L1, the second control module is further configured to set the first interface or the second interface from a P0 state to a P1 state, to close a logical clock output by the first interface or the second interface, and to control an aux_clk_sel signal to be pulled high.

[0013] The second aspect of the embodiment of the present application provides a PCIe switch management method, characterized in that the PCIe switch comprises a first interface and a second interface, the first interface and a first PCIe device are connected through a first link, and the second interface and a second PCIe device are connected through a second link, and the method comprises the following steps: monitoring a first link state of the first link; generating a first control signal according to the first link state; and controlling to update a second link state of the second link according to the first control signal, wherein the updated second link state is the same as the first link state.

[0014] The third aspect of the embodiment of the present application provides a PCIe switch, characterized in that the PCIe switch comprises the PCIe switch management device of the first aspect.

[0015] Compared with the prior art, the embodiment of the present application has the following beneficial effects:

[0016] The PCIe switch management device, method and PCIe switch provided in the embodiment can realize the cooperative control of the PCIe switch link and power management, thereby realizing the conversion of the low power consumption of the PCIe switch. BRIEF DESCRIPTION OF DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0018] Figure 1 is an application scenario diagram of a PCIe switch provided by the embodiment of the present application;

[0019] Figure 2 is a structure diagram of a PCIe switch and the setting relationship between the PCIe switch and the PCIe switch management device provided by the embodiment of the present application;

[0020] Figure 3 is a low power consumption implementation block diagram of a PCIe switch provided by the embodiment of the present application;

[0021] Figure 4 is a schematic diagram of a global power management module implementing global power message processing provided by an embodiment of the present application;

[0022] Figure 5 is a flowchart of a PCIe-PM mechanism entering an L1 link state provided by an embodiment of the present application;

[0023] Figure 6is a flowchart of a process of entering L1 link state by the ASMP mechanism provided in an embodiment of the present application;

[0024] Figure 7 is a flowchart of a process of entering and exiting L0s link state by the clock control unit and the physical layer interface connected therewith in linkage provided in an embodiment of the present application;

[0025] Figure 8 is a flowchart of a process of entering and exiting L0s link state by the clock control unit and the physical layer interface connected therewith in linkage provided in an embodiment of the present application;

[0026] Figure 9 is a flowchart of a process of entering and exiting L1 link state by the clock control unit and the physical layer interface connected therewith in linkage provided in an embodiment of the present application;

[0027] Figure 10 is a flowchart of a process of a PCIe switch management method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0028] In the following description, specific details are set forth in order to provide a thorough understanding of embodiments of the application. However, persons of ordinary skill in the art will readily recognize that embodiments of the application can be practiced without

[0029] The technical solutions provided by the present application are explained in detail below in combination with specific embodiments.

[0030] Some terms or names involved in the embodiments of the present application are explained below.

[0031] (I) Device power state

[0032] D0 state: normal working power state.

[0033] D1 state: light sleep state.

[0034] D2 state: deep sleep state.

[0035] D3hot state: full shutdown state, but the power of the device has not been cut off.

[0036] D3cold state: full shutdown state, but the power of the device has been cut off.

[0037] (II) Link power state

[0038] L0 state: normal working link state.

[0039] L0s state: standby state.

[0040] L1 state: low-power standby state.

[0041] L2 / 3 ready state: power-off stage state.

[0042] L2 state: low-power sleep state.

[0043] L3 state: power-off state.

[0044] Among different device power states, the link states that can be entered by the PCI-PM mechanism and the ASPM mechanism are shown in Table 1 as follows:

[0045] Table 1

[0046] Device power state PCI-PM ASPM D0 L0 L0, L0s, L1 D1 L1 - D2 L1 - D3 L1, L2 / 3 ready, L2, L3 -

[0047] (Three) PHY interface: physical interface

[0048] (Four) signal type

[0049] PME_Turn_Off: a protocol-defined message name, which is a power management event, and the event changes all PCIe device link states to L2 / L3.

[0050] RC: root complex device.

[0051] PME_TO_Ack: a protocol-defined message name, which is an acknowledgement to PME_turn_off.

[0052] turn_off_rcv_ack: an internal signal indicating that the current downstream port has received the PME_TO_Ack message.

[0053] all_dsp_rcv_ack: an internal signal indicating that all downstream ports have received the PME_TO_Ack message.

[0054] (Five) link state

[0055] link_in_rl0s: link state in which the link is in L0s.

[0056] link_in_l1: link state in which the link is in L1 or deeper link state.

[0057] link_in_l23: link state in which the link is in L2 / L3.

[0058] l1_exit: Link state of the link exiting L1.

[0059] l23_exit: Link state of the link exiting L2 / L3.

[0060] tx link is transport, rx link is receive.

[0061] (vi) Link state signals

[0062] all_dsp_in_l0s: Internal signal indicating that all downstream ports are in L0s link state on the second receive link.

[0063] usp_in_l0s: Internal signal indicating that the upstream port is in L0s link state on the first receive link.

[0064] PM_Enter_L1 DLLP: A protocol-defined message name, a power management event indicating that the downstream component requests to enter L1 link state.

[0065] PM_Active_state_request_L1 DLLP: A protocol-defined message name, indicating that the downstream component requests to enter L1 link state via ASPM.

[0066] all_dsp_in_l1 signal: Internal signal indicating that all downstream ports are in L1 or deeper link state.

[0067] PM_Enter_L23 DLLP: A protocol-defined message name, a power management event indicating that the downstream component requests to enter L2 / 3 link state.

[0068] ready_entr_l23 signal: Internal signal indicating that all downstream ports are in L2 / L3 link state.

[0069] one_dsp_exit_l1: Internal signal indicating that one or more downstream ports exit L1 link state.

[0070] req_exit_l1: Internal signal for informing the downstream port to start exiting L1 link state.

[0071] one_dsp_exit_l23: Internal signal for informing the upstream port that one or more downstream ports exit L23 link state.

[0072] all_dsp_in_l0s: an internal signal indicating that all downstream ports receive links are in L0s link state.

[0073] usp_in_l0s signal: an internal signal indicating that the upstream link is in L0s link state.

[0074] PMCSR: a power management register indicating PCIe protocol register.

[0075] PM_ENTER_L1 DLLP message: a protocol-specified message name used to indicate a request signal for entering L1 link state through the PM-PCI mechanism.

[0076] PM_Request_ack DLLP message: a protocol-specified message name used to indicate that the PM_ENTER_L1 DLLP message is received.

[0077] PM_active_state_request_L1 message: a protocol-specified message name used to indicate a request signal for entering L1 link state through the ASPM mechanism.

[0078] PM_active_state_request_L1 message: a protocol-specified message name used to indicate that the PM_active_state_request_L1 message is received.

[0079] TLP: a transport layer packet.

[0080] DLLP: a data link layer packet.

[0081] Figure 1 An application scenario of a PCIe switch provided by an embodiment of the present application is shown in FIG. 1. Figure 1 As shown in FIG. 1, in general, a root complex (RC) and a plurality of PCIe terminal devices are connected through a PCIe switch (also referred to as a switch). The PCIe switch is used to implement data transmission between the root complex device and each PCIe terminal device, or between each PCIe terminal device.

[0082] The PCIe switch provided in the embodiment includes a PCIe switch management device, such as a PCIe switch management device 100 shown in FIG. 2. Figure 2As shown in the figure, the shaded part is the module unit of the PCIe switch management device provided in the embodiment. The PCIe switch provided in the embodiment includes: a first physical layer interface (referred to as a first interface), a port controller of an upstream port, a port controller of a downstream port, a packet exchange module arranged between the upstream and downstream port controllers, a second physical layer interface (referred to as a second interface), and a PCIe switch management device. According to the PCIe protocol, the number of port controllers of the upstream port in the PCIe switch is 1, and the number of port controllers of the downstream port is n (n is any value in 1-32). The root component device is connected with the PCIe switch through the first physical layer interface, and the PCIe terminal device is connected with the PCIe switch through the second physical layer interface.

[0083] The PCIe switch management device provided in the embodiment is explained in combination with the structure of the PCIe switch provided in the embodiment. Referring to Figure 2 As shown in the figure, the PCIe switch management device provided in the embodiment includes: an upstream port control module, a downstream port control module, and a global power management module. The upstream port control module is arranged in the port controller of the upstream port of the PCIe switch, and the upstream port control module is completed by means of the protocol logic of the port controller of the upstream port when performing the corresponding operation. Similarly, the downstream port control module is arranged in the port controller of the downstream port of the PCIe switch, and the downstream port control module is completed by means of the protocol logic of the port controller of the downstream port when performing the corresponding operation. The global power management module is embedded in the PCIe switch and exists in parallel with the packet exchange processing module in the PCIe switch, and is connected with the upstream port control module and the downstream port control module respectively. It should be noted that, according to the setting condition of the number of port controllers of the upstream and downstream ports in the PCIe switch structure, the number of upstream port control modules in the PCIe switch management device provided in the embodiment is 1, and the number of downstream port control modules is n, wherein n is any value in 1-32.

[0084] In the PCIe switch provided in the embodiment, the global power management module exists in parallel with the packet exchange processing module, so that the exchange logic of the global power management module and the packet exchange module is independently working when completing the cooperative work, and therefore the bandwidth is not occupied or the normal communication of the data packet is not affected.

[0085] Figure 3 The PCIe switch low-power consumption implementation block diagram provided in an embodiment of the application is shown in the figure. In the figure, Figure 3 The solid line box part in the figure is the structure block diagram of the PCIe switch management device provided in an embodiment of the application. Referring to Figure 3As shown, the upstream port control module in the PCIe switch management device can connect the root complex device based on a differential link including a transmit path and a receive path through a first physical layer interface. The downstream port control module can connect the PCIe endpoint device based on a differential link including a transmit path and a receive path through a second physical layer interface.

[0086] The PCIe switch management device and the PCIe switch management method provided in the embodiment are explained in detail below with the number of upstream port control modules in the PCIe switch management device being 1 and the number of downstream port control modules being 1 as an example.

[0087] The upstream port control module includes a message processing unit of upstream port attributes, a link control unit, and a clock control unit.

[0088] In the upstream port, the message processing unit is configured to send and receive power management related messages specified in the PCIe protocol, receive instructions from the global power management module and the link control unit, send specified power messages to the sending link, and feed back the received power messages to the link control unit and the global power management module.

[0089] The link control unit is configured to control the link state and the power state of the PCIe device according to the information of the message processing unit and the global power management module, control the message processing unit to send power management messages, and control the closing and opening of the clock.

[0090] The clock control unit is configured to receive instructions from the link control unit, close and open the clock according to the PIPE interface protocol, and control the power state of the physical layer interface (PHY).

[0091] The downstream port control module includes a message processing unit of downstream port attributes, a link control unit, and a clock control unit.

[0092] In the downstream port, the message processing unit is configured to send and receive power management related messages specified in the PCIe protocol, receive instructions from the global power management module and the link control unit, send specified power messages to the sending link, and feed back the received power messages to the link control unit and the global power management module.

[0093] The link control unit is configured to control the link state and the power state of the PCIe device according to the information of the message processing unit and the global power management module, control the message processing unit to send power management messages, and control the closing and opening of the clock.

[0094] The clock control unit receives instructions from the link control unit, turns the clock on and off according to the PIPE interface protocol, and controls the power state of the physical layer interface (PHY).

[0095] The global power management module is used for: (i) processing global power messages; and (ii) collaborative management of link status.

[0096] The functions performed by the global power management module will be explained in detail below from the two aspects mentioned above.

[0097] (I) Handling of global power messages

[0098] The global power management module receives link status information sent by the message processing unit. This link status information is a link control command used to instruct all PCIe devices to change their link status to the corresponding low-power state. Then, based on the link status information, the module controls the message processing unit to generate a control signal. This control signal is used to change the link status of all PCIe devices to the power state corresponding to the link status information.

[0099] Specifically, it includes the following steps: See Figure 4 As shown, the message processing unit of the upstream port, after receiving the first PME_Turn_Off message sent by the root component device through the transmission path, uses this message to instruct the link state of all PCIe terminal devices connected to the downstream port to be modified to L2 or L3 state, and submits the turn_off request (indicating that the upstream port control module has received the first PME_Turn_Off message) to the global power management module; the global power management module then controls the message processing modules of all active downstream ports to generate and send the second PME_Turn_Off message to the PCIe devices connected to it (e.g., ...). Figure 5PCIe device 1 and PCIe device 2, etc. in FIG. 1). The message processing module of the downstream port sends the second PME_turn_off message and waits for the PME_TO_Ack message (the PCIe device of the active downstream port sends the PME_TO_Ack message to the message processing module of the respective downstream port after receiving the corresponding second PME_turn_off message, indicating that the second PME_turn_off message has been received). If the PME_TO_Ack message is received, the message processing module of the downstream port sets the turn_off_rcv_ack signal (indicating that the current downstream port has received the PME_TO_Ack message) to notify the global power management module. The global power management module waits for the turn_off_rcv_ack signal of all active downstream port message processing modules (i.e. indicating that the link state of all PCIe devices connected by the downstream port has been modified to L2 or L3 state), and then sets the all_dsp_rcv_ack signal (indicating that all downstream ports have received the PME_TO_Ack message) to the message processing module of the upstream port, which generates the PME_TO_Ack message and sends it to the root component device.

[0100] (II) Cooperative management of link state

[0101] The global power management module receives the link state information of each port through the link control unit, which is used to indicate the link state of each upstream and downstream port, and then generates a corresponding control signal according to the link state information, and cooperatively manages the link state of each upstream and downstream port according to the control signal.

[0102] The link control unit is used to monitor the link state of the corresponding receiving link and transmitting link, for example, the link control unit monitors the link state of the receiving link and transmitting link between the PCIe terminal device and the PCIe switch. The link control unit is also used to send the monitored link state of the corresponding receiving link and transmitting link to the global power management module.

[0103] The link control unit feeds back the link state of the corresponding port through internal signals link_in_rL0s (indicating that the link is in L0s), link_in_l1 (indicating that the link is in L1 or deeper link state), link_in_l23 (indicating that the link is in L2 / L3), l1_exit (indicating that the link exits L1), l23_exit (indicating that the link exits L2 / L3). The following is explained with specific examples.

[0104] 1. link_in_rL0s

[0105] Referring to Figure 3As shown in the figure, if the receiving link state of the downstream port is L0s, the link control unit of the downstream port sets link_in_rl0s to report to the global power management module. When the global power management module detects that all the receiving link directions of the downstream ports enter the L0s link state, it sets the all_dsp_in_rl0s (indicating that all the receiving links of the downstream ports are in the L0s state) signal to the link control unit of the upstream port, and the link control unit of the upstream port controls the sending link direction to start the entering process of L0s.

[0106] When the receiving link direction of the upstream port enters L0s, the link control unit of the upstream port sets link_in_rl0s (indicating that the receiving link is in the L0s state) to report to the global power management module, and the global power management module sets the usp_in_l0s (indicating that the receiving link is in the L0s state) signal to the link control unit of all the downstream ports after receiving the link_in_rl0s signal. The link control unit of the downstream port controls all the sending link directions of the downstream port to start the entering process of L0s.

[0107] 2、link_in_L1

[0108] It should be noted that according to the PCIe protocol, the request to enter the L1 link state can only be initiated by the downstream component of the PCIe switch. In this embodiment, the upstream and downstream components are divided by differential lines, for example, see Figure 3 As shown in the figure, if the downstream component in the figure is the upstream port of the PCIe switch, the upstream component in the figure is the PCIe device connected to the upstream port of the PCIe switch, such as the root component RC. If the upstream component in the figure is the downstream port of the PCIe switch, the downstream component in the figure is the PCIe device connected to the downstream port of the PCIe switch, such as the endpoint device. That is, the request to enter the L1 link state can only be initiated by the upstream port or the PCIe device connected to the downstream port.

[0109] When the PCIe protocol specifies entering the L1 link state through upper software control, the link state information of the PM_Enter_L1DLLP (indicating that the downstream component requests to enter the L1 link state through upper software control) signal is used, and the specific process is described in the process of implementing the global power message processing of the global power management module in the above embodiment.

[0110] The hardware way to automatically enter L1 state uses the PM_Active_state_request_L1 DLLP (Downstream component requests to enter L1 link state through ASPM) signal. As the PCIe switch upstream port that can initiate entering ASPM L1 (entering L1 link state through ASPM), one of the conditions for entering ASPM L1 is that all downstream port links are in L1 (or deeper) link state, or the link is in the off state. Therefore, if the downstream port link state is in L1 or lower, the link control unit of the downstream port sets link_in_l1 (all downstream port links are in L1 or deeper link state) to report to the global power management module. When the global power management module detects that all downstream port link states are in L1 link state, the all_dsp_in_l1 signal (all downstream port link states are in L1 or deeper link state) is set to the link control unit of the upstream port, and the link control unit of the upstream port controls the upstream port link to start the L1 entering process.

[0111] 3、link_in_L23

[0112] The PCIe protocol specifies that one of the conditions for the upstream port link to enter L23 Ready link state is that all downstream port links enter L23 Ready link state. The upstream port sends PM_Enter_L23 DLLP (downstream component requests to enter L23 link state), and then the upstream port link enters L23 Ready link state. Therefore, if the downstream port link state is in L23 ready, the link control unit of the downstream port sets link_in_l23 (all downstream port links are in L2 / L3 link state) to report to the global power management module. When the global power management module detects that all downstream port links are in L23 Ready link state, the ready_entr_l23 signal (all downstream port links are in L23 link state) is set to the link control unit of the upstream port, and the link control unit of the upstream port controls the upstream port link direction to start the L23 entering process.

[0113] 4、L1_exit

[0114] If the downstream port link exits from the link state of L1, the link control unit of the downstream port sets L1_exit (indicating that the downstream port link exits from the link state of L1), and the global power management module sets one_dsp_exit_l1 (indicating that one or more downstream port links exit from the link state of L1) to notify the link control unit of the upstream port when it is perceived that any one or more downstream port links exit from the link state of L1, and the link control unit of the upstream port controls the upstream port link to start the exit process of L1.

[0115] If the upstream port link exits from the link state of L1, the link control unit of the upstream port sets L1_exit (indicating that the port link state exits from L1), and the global power management module sets req_exit_l1 (used to notify the downstream port link to start exiting from the link state of L1) to signal the link control unit of the downstream port when it is perceived that the upstream port link exits from the link state of L1, and the link control unit of the downstream port controls the link of the downstream port to start the exit process of L1.

[0116] 5. Exit of L23

[0117] If the downstream port link state exits from L23, the link control unit of the downstream port sets L23_exit, and the global power management module sets one_dsp_exit_l23 (used to notify the upstream port that one or more downstream ports exit from the link state of L23) to notify the link control unit of the upstream port when it is perceived that any one or more downstream ports exit from the link state of L23, and the link control unit of the upstream port controls the link of the upstream port to start the exit process of L23.

[0118] The link control unit is used to synchronize the link state with the link control units of other ports through the global power management module, and to control the corresponding ports to enter the respective link states. The following describes the specific operations performed by the link control unit when controlling the corresponding upstream and downstream ports to enter different link states.

[0119] 1. L0s entry

[0120] For the link control unit of the upstream port, if there is no TLP (Transport Layer Packet) or DLLP (Data Link Layer Packet) waiting to be sent in the port, and the all_dsp_in_rl0s signal (indicating that all the receiving links of the downstream ports are in L0s link state) is high, the condition for the sending link of the upstream port to enter L0s state is met; for the link control unit of the downstream port, if there is no TLP or DLLP waiting to be sent in the port, and the usp_in_l0s signal (indicating that the sending link of the upstream port is in L0s link state) is high, the TLP or DLLP waiting to be sent. When the link control unit detects that the time for the corresponding upstream and downstream ports to meet the condition for entering L0s reaches a first preset length of time, the corresponding link is controlled to enter L0s link state. The link control unit controls the transmitter of the corresponding physical layer interface to send an electrical idle sequence, and sets the transmitter to Hi-Z state to reduce the power consumption of the transmitter, thereby reducing the power consumption of the PCIe switch.

[0121] 2. L0s exit

[0122] When the link control unit detects that the corresponding port no longer meets the condition for entering L0s, the transmitter of the physical layer interface is controlled to exit Hi-Z state, and N FTS ordered sets are sent to notify the peer device to exit L0s.

[0123] 3. L1 entry

[0124] There are two ways to enter L1 link state, one is PM-PCI mechanism, and the other is ASPM mechanism.

[0125] The way to enter L1 link state by PM-PCI mechanism is shown in Figure 5 , if the downstream component in Figure 5 is the upstream port of the PCIe switch, the upstream component in Figure 5 is the PCIe device connected to the upstream port of the switch, such as the root complex. If the upstream component in Figure 5 is the downstream port of the PCIe switch, the downstream component in Figure 5 is the PCIe device connected to the downstream port of the switch, such as the endpoint device.

[0126] After the downstream component's link control unit detects that the PMCSR (a power management register, representing the PCIe protocol register) has been configured to enter the L1 link state, it waits for the currently transmitted TLP message to finish sending, generates a blocking signal value, sends a new TLP message, and then waits for the retry buffer on the transmission link to be empty. Once preset conditions are met, the downstream component's link control unit controls the message processing unit to begin periodically sending PM_ENTER_L1 DLLP messages to the peer PCIe device. Upon receiving PM_ENTER_L1, the upstream component's message processing unit notifies the link control unit and subsequently begins L1 preparation, i.e., waiting for the currently transmitted TLP message to finish sending, generating a blocking signal value, sending a new TLP message, and then waiting for the retry buffer on the transmission path to be empty. After the preset conditions are met, the link control unit of the upstream component controls the message processing unit to periodically send PM_Request_ack DLLP messages (a protocol-defined message name used to indicate receipt of PM_ENTER_L1 DLLP) to the peer PCIe device. Simultaneously, the link control unit of the upstream component controls the transmitter of the physical layer interface to send an idle sequence, setting the transmitter to the Hi-Z state. Upon receiving the PM_Request_ack DLLP, the link control unit of the downstream component controls the transmitter of the physical layer interface to send an idle sequence, setting the transmitter to the Hi-Z state to reduce transmitter power consumption.

[0127] It should be noted that the main differences between ASMP L1 entry and PM-PCI L1 entry are as follows: First, for an upstream port to enter ASMP L1, all downstream ports must be in L1 ASPM or lower state, that is, the link control unit of the upstream port needs to detect whether the all_dsp_in_l1 signal is high; Second, the L1 entry request message sent is PM_active_state_request_L1.

[0128] The ASMP mechanism enters the L1 link state in the following way: Figure 6 As shown, similarly, if the downstream component in 6 is an upstream port of a PCIe switch, then Figure 6 The upstream component in the context is the root component device connected to the upstream port of the switch. If... Figure 6 If the upstream component is the downstream port of the PCIe switch, then... Figure 6 The downstream components are PCIe terminal devices connected to the downstream ports of the switch.

[0129] The link control unit of the downstream component detects that the sending link direction and the receiving link direction are both in L0s for a second preset time length, and the link state of all downstream ports is in L1 ASMP or a lower state. The link control unit waits for the sending of the TLP message to be completed, generates a blocking signal to block the sending of a new TLP message, and then waits for the retry buffer on the sending link to be empty. After the preset condition is met, the link control unit of the downstream component controls the message processing unit to start periodically and cyclically sending the PM_active_state_request_L1 message to the PCIe device at the opposite end. After the message processing unit of the upstream component receives the PM_active_state_request_L1, the message processing unit waits for the sending of the TLP message to be completed, generates a blocking signal to block the sending of a new TLP message, and then waits for the retry buffer on the sending link to be empty. After the condition is met, the link control unit of the upstream component controls the message processing unit to start periodically and cyclically sending the PM_Request_ack DLLP message (a protocol specified message name, used to indicate that the PM_active_state_request_L1 is received) to the PCIe device at the opposite end, and the link control unit of the upstream component controls the transmitter of the physical layer interface to send the electrical idle sequence to set the transmitter to the Hi-Z state. After the downstream component receives the PM_Request_ack DLLP, the link control unit of the downstream component controls the transmitter of the physical layer interface to send the electrical idle sequence to set the transmitter to the Hi-Z state to reduce the power consumption of the transmitter.

[0130] 4. L1 exit

[0131] When the link control unit detects that the port no longer meets the L1 condition (PM-PCI control or ASPM automatic detection), the physical layer interface transmitter is controlled to exit the Hi-Z state and send N FTS training ordered sets to exit to L0.

[0132] A clock control unit is used to realize the exit and entry of the ASPM states of the upstream and downstream ports through the method of linkage with the physical layer interface (phy) connected thereto.

[0133] 1. Entry and exit of the upstream port into and out of L0s

[0134] Referring to Figure 7As shown in FIG. 6, when the receiving link of all downstream ports is in the L0s link state (all_dsp_in_rl0 = 1), the clock control unit of the upstream port controls the frequency of the clock signal (pclk) to remain unchanged, then sends a Powerdown signal to the first physical layer interface, for making the first physical layer interface set the P0s state from the P0 state, and waits for the control signal (phystatus) of the first physical layer interface (phy) after determining that it is in the P0s state. Wherein, Powerdown and phystatus are standard pipe interface signals. When the first physical layer interface confirms that it is in the P0s state, the control sends the differential line in the transmission link direction to be in the Hi-Z state, and the transmitter of the first physical layer interface is in the low power consumption state.

[0135] Referring to Figure 7 As shown in FIG. 6, when the receiving link of all downstream ports is in the L0s link state (all_dsp_in_rl0 = 1), the clock control unit of the upstream port controls the frequency of the clock signal (pclk) to remain unchanged, then sends a Powerdown signal to the first physical layer interface, for making the first physical layer interface set the P0s state from the P0 state, and waits for the control signal (phystatus) of the first physical layer interface (phy) after determining that it is in the P0s state. Wherein, Powerdown and phystatus are standard pipe interface signals. When the first physical layer interface confirms that it is in the P0s state, the control sends the differential line in the transmission link direction to be in the Hi-Z state, and the transmitter of the first physical layer interface is in the low power consumption state.

[0136] 2, the downstream port enters the L0s exit

[0137] Referring to Figure 8 As shown in FIG. 6, when the receiving link of all downstream ports is in the L0s link state (all_dsp_in_rl0 = 1), the clock control unit of the upstream port controls the frequency of the clock signal (pclk) to remain unchanged, then sends a Powerdown signal to the first physical layer interface, for making the first physical layer interface set the P0s state from the P0 state, and waits for the control signal (phystatus) of the first physical layer interface (phy) after determining that it is in the P0s state. Wherein, Powerdown and phystatus are standard pipe interface signals. When the first physical layer interface confirms that it is in the P0s state, the control sends the differential line in the transmission link direction to be in the Hi-Z state, and the transmitter of the first physical layer interface is in the low power consumption state.

[0138] Referring to Figure 8As shown, when all the downstream ports' receive links receive the signal of exiting L0s link state (usp_in_rl0 = 0), the clock control unit of the downstream port controls the frequency of the clock signal (pclk) to remain unchanged, then sends a Powerdown signal to the second physical layer interface, for making the second physical layer interface set P0 state from P0s state, and waits for the control signal (phystatus) of the second physical layer interface (phy) after determining to be in P0 state. When the second physical layer interface confirms to be in P0 state, the control sends the differential line in the transmission link direction to exit Hi-Z state, and the transmitter of the second physical layer interface exits low power state.

[0139] 3. Entering and exiting L1

[0140] In some embodiments, when the upstream and downstream ports on the PCIe switch enter and exit L1 state, the link control unit is to reduce the power consumption of the PCIe switch by the following way.

[0141] Referring to Figure 9 As shown, when the upstream and downstream ports meet the entering L1 condition, the clock control unit sends a Powerdown signal to the corresponding physical layer interface, for making the physical layer interface set P1 state from P0 state, and waits for the control signal (phystatus) of the physical layer interface (phy) after determining to be in P1 state. Wherein, Powerdown and phystatus are standard pipe interface signals. When the physical layer interface confirms to be in P1 state, the logical clock (core_clk) output by the physical layer interface is turned off, at the same time the clock control unit pulls up the aux_clk_sel (internal signal, indicating the switching of normal clock and auxiliary clock) signal, and switches the driving clock (mux_aux_clk) of the clock control unit internal circuit which must work from high frequency clock to low frequency auxiliary clock, so as to achieve the purpose of reducing power consumption. In addition, in P1 power state, the clock control unit controls the differential line in the transmission link direction of the physical layer interface to be in Hi-Z state, and the transmitter of the physical layer interface to be in low power state.

[0142] Referring to Figure 9As shown, when the upstream and downstream ports receive a signal for exiting the L1 link state, the clock control unit sends a Powerdown signal to the corresponding physical layer interface for setting the physical layer interface from the P1 state to the P0 state, and waits for a control signal (phy status) from the physical layer interface (phy) after determining that the physical layer interface is in the P0 state. When the physical layer interface confirms that it is in the P0 state, the logical clock (core_clk) output by the physical layer interface is turned on, and at the same time the clock control unit lowers the aux_clk_sel (internal signal, indicating the switching of the normal clock and the auxiliary clock) signal, and switches the driving clock (mux_aux_clk) of the internal circuit of the clock control unit that must work from the low-frequency auxiliary clock to the high-frequency clock, so as to achieve the normal working state. In addition, in the P0 power state, the clock control unit controls the differential line in the transmission link direction of the physical layer interface to exit the Hi-Z state, and the transmitter of the physical layer interface exits the low-power state.

[0143] Figure 10 A flowchart of a PCIe switch management method is provided in the embodiment. The method is applied to a PCIe switch, the PCIe switch comprising a first interface and a second interface, the first interface and a first PCIe device being connected through a first link, and the second interface and a second PCIe device being connected through a second link. The method comprises the following steps:

[0144] S1001, monitoring a first link state of the first link.

[0145] S1002, generating a first control signal according to the first link state.

[0146] S1003, controlling to update a second link state of the second link according to the first control signal, and the updated second link state being the same as the first link state.

[0147] The embodiment further provides a PCIe switch, which is internally provided with the PCIe switch management device described in the embodiment.

[0148] The PCIe switch management device, method and PCIe switch provided in the embodiment can realize the cooperative control of the PCIe switch link and power management, thereby realizing the low-power conversion of the PCIe switch, and the realization method is described in detail from the functional block diagram and the timing control.

[0149] It should be understood that the word "comprising" when used in the specification and claims of this application indicates the existence of the stated features, integers, steps or elements but does not preclude the presence or addition of one or more other features, integers, steps, elements or groups thereof.

[0150] Reference throughout this specification to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the application. Thus, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment, but can refer to different embodiments. The terms "including," "comprising," "having" and their variants are meant to be equivalent to the term "comprising" and therefore should not be interpreted as limiting. The use of the term "about" in relation to a reference number can indicate that the value of the reference number is variable and can vary by ±10%.

[0151] The above-described embodiments are merely intended to illustrate the technical solutions of the present application, but not to limit the same; even though the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: they can still make modifications to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some technical features therein; and these modifications or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be included in the protection scope of the present application.

Claims

1. A PCIe switch management device, characterized in that, include: The system comprises a first control module, a second control module, and a global power management module. The first control module is connected to a first PCIe device via a first interface, and the second control module is connected to a second PCIe device via a second interface. The link between the first control module and the first PCIe device is a first link, and the link between the second control module and the second PCIe device is a second link. The first control module is used to monitor the first link status of the first link; The global power management module is used to generate a first control signal based on the first link status; The second control module is used to control the update of the second link status of the second link according to the first control signal, and the updated second link status is the same as the first link status; When the first control module is a downstream port control module and the second control module is an upstream port control module, the second control module is used to set the second interface from the P0 state to the P0s state when the first link state is L0s, and control the all_dsp_in_rl0 signal to be high level. When the first control module is an upstream port control module and the second control module is a downstream port control module, the second control module is further configured to set the second interface from the P0 state to the P0s state and control the usp_in_rl0 signal to a high level when the first link state is L0s. When updating the first link or the second link to L1, the second control module is further configured to set the first interface or the second interface from the P0 state to the P1 state, turn off the logic clock output by the first interface or the second interface, and control the pull-up of the aux_clk_sel signal.

2. The PCIe switch management device according to claim 1, characterized in that, When the first control module is an upstream port control module and the second control module is a downstream port control module, the first link state is L0s and the control signal is usp_in_l0s. The second control module is specifically used to update the second link status to L0s according to usp_in_l0s when the first preset condition is met; The first preset condition includes: no TLP or DLLP waiting to be sent at the upstream port, and the usp_in_l0s signal is at a high level.

3. The PCIe switch management device according to claim 1, characterized in that, When the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L0s and the control signal is all_dsp_in_rl0s. The second control module is specifically used to update the second link status to L0s according to all_dsp_in_rl0s when the second preset condition is met; The second preset condition includes: no TLP or DLLP waiting to be sent at the downstream port, and the all_dsp_in_rl0s signal is at a high level.

4. The PCIe switch management device according to claim 1, characterized in that, When the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L1 or a state with power consumption lower than L1, and the control signal is all_dsp_in_l1; The second control module is specifically used to update the second link to L1 according to the control signal all_dsp_in_l1 when the third preset condition is met; The third preset condition includes: after the receiving and sending directions of the second link are both in L0s for a preset time length, the first link is in L1 ASMP or the power consumption is lower than L1 ASMP, waiting for the TLP message being sent to finish sending, and generating a blocking signal to prevent the sending of new TLP messages, so that the retransmission buffer on the second link is empty.

5. The PCIe switch management device according to claim 1, characterized in that, When the first control module is a downstream port control module and the second control module is an upstream port control module, the first link state is L1 or a state with power consumption lower than L1, and the control signal is PM_ENTER_L1DLLP. The second control module is specifically used to update the second link to L1 according to the PM_ENTER_L1 DLLP when the fourth preset condition is met; The fourth preset condition includes: after the receiving and sending directions of the second link are both in L0s for a preset time length, the first link is in L1 ASMP or the power consumption is lower than L1 ASMP, waiting for the TLP message being sent to finish sending, and generating a blocking signal to prevent the sending of new TLP messages, so that the retransmission buffer on the sending link is empty.

6. The PCIe switch management device according to claim 1, characterized in that, The first control module is further configured to acquire link control commands sent by the first PCIe device; The global power management module is also used to generate a second control signal according to the link control command; The second control module is further configured to update the second link status according to the second control signal, wherein the updated second link status corresponds to the link control command.

7. The PCIe switch management device according to claim 6, characterized in that, The first PCIe device is a root component device, and the second PCIe device is a PCIe terminal device; the link control command is used to instruct the second link state to be updated to L2 or L3 state. The first PCIe device is a PCIe terminal device, the second PCIe device is a root component device, and the link control command is used to instruct the second link state to be updated to L1 state.

8. A PCIe switch management method, characterized in that, The PCIe switch includes a first interface and a second interface. The first interface and a first PCIe device are connected via a first link, and the second interface and the second PCIe device are connected via a second link. The method includes: Monitor the status of the first link of the first link; A first control signal is generated based on the first link status; The second link state of the second link is updated according to the first control signal, and the updated second link state is the same as the first link state. The method further includes: when the first link state is L0s, setting the second interface from P0 state to P0s state, and controlling the all_dsp_in_rl0 signal to be high level; When the first link state is L0s, the second interface is set from P0 state to P0s state, and the usp_in_rl0 signal is controlled to be high level. When updating the first link or the second link to L1, the first interface or the second interface is set from P0 state to P1 state, the logic clock output by the first interface or the second interface is turned off, and the aux_clk_sel signal is pulled high.

9. A PCIe switch, characterized in that, Includes the PCIe switch management device as described in any one of claims 1-7.

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