Pixel column readout circuit and image sensor

Abstract

This invention provides a pixel column readout circuit and an image sensor. The pixel column readout circuit includes: a subtraction circuit, comprising a reset voltage sampling capacitor and a signal voltage sampling capacitor, one end of which is electrically connected to the output of a pixel signal generation circuit via two switches, and one end of which is connected via a third switch, and the other end via a fourth switch; a ramp generator, the output of which is connected to the subtraction circuit; a comparator circuit, including a first comparator, the negative input of which is electrically connected to the connection point of the reset voltage sampling capacitor and the fourth switch, and the positive input of which receives a fixed voltage; and a counter, electrically connected to the output of the comparator circuit. The ramp generator provided by this invention ensures linear output of the analog-to-digital conversion.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and specifically relates to a pixel column readout circuit and an image sensor. Background Technology

[0002] Image sensors are increasingly widely used due to their low power consumption, simple power supply, high integration, and low cost. An image sensor is used to generate images representing objects, and includes rows and columns of pixels, as well as row and column readout circuits.

[0003] In the pixel column readout circuit, the comparator flip point varies with the pixel output voltage across the entire ramp range. Different flip points lead to changes in the comparator's operating state, resulting in a non-linear degradation of the output as a function of the input. At the instant of counting, the ramp output also experiences undershoot, causing ramp non-linearity and severely impacting the linearity of the analog-to-digital converter (ADC). When the output of the ramp generator directly drives the ADC array, the different pixel output sizes in each column of the array result in different comparator flip times. This leads to significant kickback noise during comparator flips, which directly couples to the integrating capacitor, causing abrupt changes in the output voltage and ultimately resulting in ramp non-linearity. Summary of the Invention

[0004] The purpose of this invention is to provide a pixel column readout circuit and an image sensor that achieves subtraction function by changing the capacitor connection method without increasing the number of sampling capacitors, ensuring the linearity of analog-to-digital conversion, while reducing the design difficulty of comparator, allowing for a simpler structure, and reducing area and power consumption.

[0005] To achieve the above objectives, the present invention provides a pixel column readout circuit, comprising at least:

[0006] The subtraction circuit includes a reset voltage sampling capacitor and a signal voltage sampling capacitor. One end of the reset voltage sampling capacitor is electrically connected to the output terminal of the pixel signal generation circuit through a first switch, and one end of the signal voltage sampling capacitor is electrically connected to the output terminal of the pixel signal generation circuit through a second switch. One end of the reset voltage sampling capacitor and the signal voltage sampling capacitor are connected through a third switch, and the other end is electrically connected through a fourth switch.

[0007] The output of the ramp generator is electrically connected to the other end of the signal voltage sampling capacitor via a fifth switch.

[0008] A comparator circuit includes a first comparator, the negative input of which is electrically connected to the connection point of the reset voltage sampling capacitor and the fourth switch, and a fixed voltage is input to its positive input; and

[0009] The counter is electrically connected to the output of the comparator circuit.

[0010] In one embodiment of the present invention, the negative input terminal and the output terminal of the first comparator are connected by a switch.

[0011] In one embodiment of the present invention, the ramp generator includes:

[0012] Slope current source;

[0013] Correct the current source;

[0014] A first buffer, the negative input terminal of which is electrically connected to the ramp current source via a switch, and the negative input terminal of which is electrically connected to the correction current source via a switch, and the positive input terminal of which receives a reference voltage; and

[0015] The integrating capacitor has one end electrically connected to the negative input terminal of the first buffer and the other end electrically connected to the output terminal of the first buffer.

[0016] In one embodiment of the present invention, the negative input terminal and the output terminal of the first buffer are connected by a switch.

[0017] In one embodiment of the present invention, the ramp generator further includes a second buffer, the positive input terminal of the second buffer being electrically connected to the output terminal of the first buffer, and the negative input terminal of the second buffer being electrically connected to the output terminal of the second buffer.

[0018] In one embodiment of the present invention, the output current of the ramp current source is equal to the output current of the correction current source.

[0019] In one embodiment of the present invention, the comparator circuit further includes a second comparator, the negative input terminal of the second comparator is electrically connected to the output terminal of the first comparator, the positive input terminal is input with the fixed voltage, and the negative input terminal and the output terminal of the second comparator are connected by a switch.

[0020] In one embodiment of the present invention, the comparator circuit further includes a coupling capacitor, which is electrically connected to the output terminal of the first comparator and the negative output terminal of the second comparator.

[0021] In one embodiment of the present invention, the counter is connected to the output of the second comparator.

[0022] In one embodiment of the present invention, the pixel column readout circuit further includes a latch, which is electrically connected to the output terminal of the counter.

[0023] The present invention also provides an image sensor, comprising:

[0024] Photodiodes, and

[0025] The pixel column reading circuit described in any of the above descriptions.

[0026] In summary, the pixel column readout circuit provided by this invention integrates the reset voltage, pixel signal voltage, and ramp generator output voltage. These are processed by a subtraction circuit and then connected to the inverting input of a comparator. The initial value of the comparator's inverting input varies with the difference between the pixel reset voltage and the pixel signal voltage, but the comparator's flip point remains constant. This constant flip point prevents changes in the comparator's operating state, thus avoiding nonlinear degradation of the output voltage due to the input. Furthermore, fixing the comparator's flip point reduces the design complexity, allowing for a simpler structure and reduced area and power consumption. The newly designed ramp generator also ensures the linearity of the output ramp voltage. Attached Figure Description

[0027] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0028] Figure 1 This is a circuit diagram of an image sensor according to the present invention.

[0029] Figure 2 This is a timing diagram of the operation of an image sensor in this invention.

[0030] Figure 3 This is a timing diagram of the operation of an image sensor in this invention.

[0031] Figure 4 This is a schematic diagram of a ramp generator structure in this invention.

[0032] Figure 5 This is a timing diagram of the operation of a ramp generator in this invention.

[0033] Figure 6 This is a timing diagram of the operation of an image sensor in this invention. Detailed Implementation

[0034] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0035] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0036] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0037] Please see Figure 1 As shown, the image sensor includes a pixel signal generation circuit 100 and a pixel column readout circuit. In the pixel signal generation circuit 100, a photodiode D converts an optical signal into an electrical signal and stores it. The pixel column readout circuit includes multiple logic controllers that can read the photoelectric signal and convert it into an image.

[0038] Please see Figure 1 As shown, in one embodiment of the present invention, the image sensor includes a pixel column readout circuit comprising a ramp generator 200, a subtraction circuit 300, a comparator circuit 400, a counter 500, and a latch 600. The pixel signal generation circuit 100 outputs a pixel signal voltage VS or a reset voltage VR, and the ramp generator 200 outputs a ramp voltage Vramp_buf. The subtraction circuit 300 is electrically connected to the pixel signal generation circuit 100 and the ramp generator 200, and can obtain the sum of the difference between the pixel signal voltage VS and the reset voltage VR and the ramp voltage Vramp_buf. The comparator circuit 400 subtracts the output value of the subtraction circuit 300 from a fixed voltage VCM, ensuring the comparator has a constant flip point. The counter 500 counts the comparison results of the comparator, and the latch 600 latches the output value of the counter 500.

[0039] Please see Figure 1As shown, in one embodiment of the present invention, the pixel signal generation circuit 100 includes a transmission transistor M1, a reset transistor M2, a source follower M3, and a row select transistor M4. The connection relationships of the transmission transistor M1, the reset transistor M2, the source follower M3, and the row select transistor M4 are as follows: Figure 1 As shown. Transmission transistor M1 effectively reduces pixel thermal noise and dark current, while source follower M3 acts as a buffer amplifier, isolating the column bus with its large parasitic capacitance and subsequent readout circuit from each sensitive node of the pixel. When the image sensor is operating, photodiode D provides an optical signal output representing the amount of light striking it, and transmission transistor M1 selectively transfers this optical signal. With pass-through transistor M4 connected, source follower M3 outputs a photoelectric signal, i.e., the pixel signal voltage VS. The pixel signal generation circuit 100 in this embodiment is merely an example of a pixel signal generation circuit; the column readout circuit of this invention is suitable for pixel signal generation circuits of any structure.

[0040] Specifically, when the signal of row select transistor M4 is high, source follower M3 selects and outputs the pixel signal voltage VS of a certain row's pixel. When the SEL signal terminal (the gate terminal of reset transistor M2) is high, the RX signal terminal controls reset transistor M2 to conduct, resetting the signal at the connection point between the source terminal of reset transistor M2 and the gate terminal of source follower M3 to the voltage value of the drain terminal of reset transistor M2. The RX signal terminal (the gate terminal of transmission transistor M1) is disconnected. Due to the channel charge injection effect and clock feedthrough, and because there is no path to ground at the connection point between the source terminal of reset transistor M2 and the gate terminal of source follower M3, the connection point between the source terminal of reset transistor M2 and the gate terminal of source follower M3 will remain at a voltage value approximately lower than the drain terminal of reset transistor M2, outputting the reset voltage VR.

[0041] Please combine Figure 1 and Figure 4As shown, in one embodiment of the present invention, the ramp generator 200 includes a ramp current source In, a correction current source Ip, a first buffer 201, and a second buffer 202. The ramp current source In is electrically connected to the negative input terminal of the first buffer 201 via a ninth switch S9, and the correction current source Ip is electrically connected to the negative input terminal of the first buffer 201 via a tenth switch S10. The current value at the negative input terminal of the first buffer 201 can be adjusted by opening and closing the ninth switch S9 and the tenth switch S10. An integrating capacitor Cf and an eighth switch S8 connected in parallel with the integrating capacitor Cf are also electrically connected between the negative input terminal and the output terminal of the first buffer 201. A reference voltage is input to the positive input terminal of the first buffer 201, and the initial ramp voltage Vramp is output to the output terminal of the first buffer 201. The first buffer 201, the integrating capacitor Cf, and the eighth switch S8 can form an integrator. At the output of the first buffer 201, a second buffer 202 is also provided. The output of the first buffer 201 is electrically connected to the positive input of the second buffer 202, the negative input of the second buffer 202 is electrically connected to the output of the second buffer 202, and the output of the second buffer 202 outputs the final ramp voltage Vramp_buf.

[0042] Please combine Figure 1 , Figure 4 and Figure 5As shown, in one embodiment of the present invention, the output currents of the ramp current source In and the correction current source Ip are equal. Before counting, the eighth switch S8 is closed to reset the integrating capacitor Cf. Then, the ninth switch S9 is opened and the tenth switch S10 is closed, and this state is maintained for a rise time of the first duration L1. During this time period, the ramp voltage Vramp_buf decreases linearly. Finally, the ninth switch S9 is closed and the tenth switch S10 is opened, the ramp voltage Vramp_buf increases linearly, and after a second duration L2, the ramp voltage Vramp_buf returns to the voltage value when the integrating capacitor Cf is reset, i.e., the reference voltage VREF. Counting begins when the ramp voltage Vramp_buf returns to the voltage value when the integrating capacitor Cf is reset. Since the output currents of the ramp current source In and the correction current source Ip are equal, the slopes of the ramp voltage Vramp_buf during the decrease and increase are equal, therefore the first duration L1 is equal to the second duration L2. After the second duration L2, the ninth switch S9 remains closed and the tenth switch S10 remains open until the voltage output by the second buffer 202 rises to the original voltage. During this process, the slope of the ramp voltage Vramp_buf remains constant. The configured correction current source Ip works in conjunction with the ramp current source In to avoid undershoot in the output ramp voltage Vramp_buf at the instant the eighth switch S8 opens and the ninth switch S9 closes, which would cause nonlinearity in the output ramp voltage Vramp_buf and severely affect the ADC linearity.

[0043] Please combine Figure 1 , Figure 4 and Figure 5 As shown, in one embodiment of the present invention, the addition of a second buffer 202 can prevent the kickback noise from comparator flipping in the ADC array from coupling to the integrator. This results in the output ramp voltage Vramp_buf of the second buffer 202 having lower coupling noise, and the ramp voltage Vramp_buf can quickly return to its original trajectory, ensuring the linearity of the output ramp voltage Vramp_buf. Simultaneously, due to the strong driving capability of the second buffer 202, the kickback noise has a smaller impact on the output ramp voltage Vramp_buf. Because the output size of each column of pixels in the array is different, the comparator flipping time is different, resulting in significant kickback noise during comparator flipping. This noise is directly coupled to the integrating capacitor Cf, causing a sudden change in the output voltage, ultimately leading to ramp nonlinearity and affecting the linearity of the ADC.

[0044] Please see Figure 1As shown, in one embodiment of the present invention, the subtraction circuit 300 includes two sampling capacitors. Specifically, the subtraction circuit 300 includes a reset voltage sampling capacitor CR and a signal voltage sampling capacitor CS. One end of the reset voltage sampling capacitor CR is electrically connected to the output terminal of the pixel signal generation circuit 100 through a first switch S1, and one end of the signal voltage sampling capacitor CS is electrically connected to the output terminal of the pixel signal generation circuit 100 through a second switch S2. A third switch S3 is provided between the connection point of the first switch S1 and the reset voltage sampling capacitor CR, and the connection point of the second switch S2 and the signal voltage sampling capacitor CS. The other end of the reset voltage sampling capacitor CR is electrically connected to the negative input terminal of the first comparator 401. The other end of the signal voltage sampling capacitor CS is electrically connected to the negative input terminal of the first comparator 401 through a fourth switch S4. The output terminal of the ramp generator 200 is electrically connected to the connection point of the signal voltage sampling capacitor CS and the fourth switch S4 through a fifth switch S5.

[0045] Please see Figure 1 As shown, in one embodiment of the present invention, the comparator circuit 400 includes a first comparator 401 and a second comparator 402 connected in series. The negative input terminal of the first comparator 401 is electrically connected to the output terminal of the subtraction circuit 300, and the positive input terminal of the first comparator 401 receives a fixed voltage VCM. A sixth switch S6 is also provided between the negative input terminal and the output terminal of the first comparator 401. The negative input terminal of the second comparator 402 is electrically connected to the output terminal of the first comparator 401 through a coupling capacitor, and the positive input terminal of the second comparator 402 receives a fixed voltage VCM. A seventh switch S7 is also provided between the negative input terminal and the output terminal of the second comparator 402. A counter 500 is connected to the output terminal of the second comparator 402, and a latch 600 is electrically connected to the output terminal of the counter 500.

[0046] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, during the operation of the pixel column readout circuit, the subtraction circuit 300 first operates and obtains the pixel signal voltage VS, reset voltage VR, and ramp voltage Vramp_buf generated by the pixel signal generation circuit 100, and calculates the difference between the pixel signal voltage VS and the reset voltage VR before performing ADC conversion.

[0047] Please see Figure 1 and Figure 2As shown, in one embodiment of the present invention, during the operation of the pixel column readout circuit, the reset voltage VR generated by the pixel signal generation circuit 100 is acquired first. Specifically, during period t1, the pixel control signal RX and SEL terminals are high, and the TX signal terminal is low, and the output voltage Vpix of the pixel signal generation circuit is the reset voltage VR. When the RX signal terminal is turned off, the final output voltage Vpix of the pixel signal generation circuit 100 is the reset voltage VR. During period t2, the first switch S1, the fourth switch S4, the sixth switch S6, and the seventh switch S7 are turned on, the first comparator 401 is reset, the negative input voltage Vin of the first comparator 401 is equal to the fixed voltage VCM, the voltage of the upper plate of the reset voltage sampling capacitor CR is the fixed voltage VCM, and the lower plate samples the reset voltage VR. After sampling is completed, the first switch S1 is turned off, and the fourth switch S4, the sixth switch S6, and the seventh switch S7 remain on.

[0048] Please see Figure 1 and Figure 2 As shown, in one embodiment of the present invention, after obtaining the reset voltage VR, the pixel signal voltage VS is then obtained. Specifically, during t3, the pixel control signal TX and SEL terminals are high, and the RX signal terminal is low. The pixel signal generation circuit outputs voltage Vpix, which is the pixel signal voltage VS. When the TX terminal is turned off, the pixel signal generation circuit outputs voltage Vpix, which is ultimately the pixel signal voltage VS. During t4, the second switch S2, the fourth switch S4, the sixth switch S6, and the seventh switch S7 are turned on. The first comparator 401 remains in the reset state. The voltage on the upper plate of the signal voltage sampling capacitor CS is a fixed voltage VCM, and the lower plate samples the pixel signal voltage VS. After sampling is completed, the second switch S2 is turned off.

[0049] Please see Figures 1 to 5 As shown, in one embodiment of the present invention, the ramp generator 200 operates during the period t5 to t6, and the specific process is as follows: Figure 4 as well as Figure 5 As shown. During period t5, before counting, the eighth switch S8 is closed, resetting the integrating capacitor Cf. Then, the ninth switch S9 is opened, and the tenth switch S10 is closed, maintaining this state for a rise time of the first duration L1. During this time period, the ramp voltage Vramp_buf decreases linearly. Finally, the ninth switch S9 is closed, and the tenth switch S10 is opened, causing the ramp voltage Vramp_buf to rise linearly. After a second duration L2, the ramp voltage Vramp_buf returns to the voltage value at which the integrating capacitor Cf was reset, i.e., the reference voltage VREF. During period t6, the ninth switch S9 remains closed, and the tenth switch S10 remains open.

[0050] Please see Figures 1 to 6 As shown, in one embodiment of the present invention, during period t6, the fourth switch S4, the sixth switch S6, and the seventh switch S7 are open, while the third switch S3 and the fifth switch S5 are closed. At this time, the negative input voltage Vin of the first comparator 401 is Vramp_buf + VS - VR. In the present invention, when the initial voltage of Vramp_buf is set to the reference voltage VREF, and VREF = VCM, the negative input voltage Vin of the first comparator 401 is VCM + VS - VR, the comparator voltage difference is VR - VS, and the output Vout is low.

[0051] Please see Figures 1 to 6 As shown, in one embodiment of the present invention, after obtaining the difference between the reset voltage VR and the pixel signal voltage VS, AD conversion is performed. Specifically, during period t6, when the third switch S3, the fifth switch S5, and the ninth switch S9 are closed, and the first switch S1, the second switch S2, the fourth switch S4, the sixth switch S6, the seventh switch S7, the eighth switch S8, and the tenth switch S10 are open, A / D conversion begins, the enable signal EN_CNT of counter 500 is high, and counter 500 starts counting. The negative input voltage Vin of the first comparator 401 is Vramp_buf + VS - VR. At this time, Vramp_buf starts to rise from the reference voltage VREF (set to be equal to VCM). When it rises to a value greater than VCM + VR - VS, the output value of the comparator circuit flips, the output value Vout of the second comparator 402 rises from low to high, counter 500 stops counting, and the current count value Dcnt is the conversion result. When the transfer signal EN_LAT is high, the data is transferred into latch 600. In this embodiment, since the positive input of the comparator is a fixed voltage VCM, the comparator flip point is always the same VCM for different pixel output results VR-VS. Furthermore, the counting stops when the comparator flips. The current pixel output VR-VS is converted by the ADC and outputs a digital code Dn.

[0052] Please see Figures 1 to 6 As shown, in one embodiment of the present invention, a compensation value can be conveniently added to the output signal Dout by setting a reference voltage VREF and a fixed voltage VCM. This compensation value is added to the signal voltage and participates in the ADC conversion, which is different from adding a digital compensation value to the ADC conversion result. Let VREF - VCM = ΔV. When ΔV > 0, it is a negative compensation value, that is, Dout is less than the theoretical value of the pixel output. When ΔV < 0, it is a positive compensation value, that is, Dout is greater than the theoretical value of the pixel output.

[0053] In summary, the pixel column readout circuit provided by this invention includes a subtraction circuit, a ramp generator, a comparator, a counter, and a latch. The subtraction circuit includes a reset voltage sampling capacitor and a signal voltage sampling capacitor. The reset voltage sampling capacitor is electrically connected to the output of the pixel signal generation circuit via a switch. The signal voltage sampling capacitor is also electrically connected to the output of the pixel signal generation circuit via a switch. One end of the reset voltage sampling capacitor and the signal voltage sampling capacitor are connected via a switch, and the other end is also electrically connected via a switch. The ramp generator is also electrically connected to the other end of the signal voltage sampling capacitor via a switch. By closing and opening different switches, the pixel signal voltage and the reset voltage can be acquired, and the difference between the reset voltage and the pixel signal voltage and the sum of the ramp voltage can be obtained. The comparator circuit calculates the difference between the output value of the subtraction circuit and a fixed voltage, ensuring the comparator has a constant flip point. The counter counts the comparison results of the comparator, and the latch latches the output value of the counter.

[0054] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A pixel column readout circuit, characterized in that, At least including: The subtraction circuit includes a reset voltage sampling capacitor and a signal voltage sampling capacitor. One end of the reset voltage sampling capacitor is electrically connected to the output terminal of the pixel signal generation circuit through a first switch, and one end of the signal voltage sampling capacitor is electrically connected to the output terminal of the pixel signal generation circuit through a second switch. One end of the reset voltage sampling capacitor and the signal voltage sampling capacitor are connected through a third switch, and the other end is electrically connected through a fourth switch. The output of the ramp generator is electrically connected to the other end of the signal voltage sampling capacitor via a fifth switch. The comparator circuit includes a first comparator, the negative input terminal of which is electrically connected to the connection point of the reset voltage sampling capacitor and the fourth switch, and the positive input terminal receives a fixed voltage. as well as The counter is electrically connected to the output terminal of the comparator circuit; The initial voltage of the ramp voltage output by the ramp generator is the fixed voltage.

2. The pixel column readout circuit according to claim 1, characterized in that, The negative input and output of the first comparator are connected by a switch.

3. The pixel column readout circuit according to claim 1, characterized in that, The ramp generator includes: Slope current source; Correct the current source; A first buffer, the negative input terminal of which is electrically connected to the ramp current source via a switch, and the negative input terminal of which is electrically connected to the correction current source via a switch, and the positive input terminal of which receives a reference voltage; and The integrating capacitor has one end electrically connected to the negative input terminal of the first buffer and the other end electrically connected to the output terminal of the first buffer.

4. The pixel column readout circuit according to claim 3, characterized in that, The negative input and output terminals of the first buffer are connected by a switch.

5. A pixel column readout circuit according to claim 3, characterized in that, The ramp generator further includes a second buffer, the positive input terminal of which is electrically connected to the output terminal of the first buffer, and the negative input terminal of which is electrically connected to the output terminal of the second buffer.

6. A pixel column readout circuit according to claim 3, characterized in that, The output current of the ramp current source is equal to the output current of the correction current source.

7. The pixel column readout circuit according to claim 1, characterized in that, The comparator circuit further includes a second comparator, the negative input terminal of which is electrically connected to the output terminal of the first comparator, the positive input terminal of which receives the fixed voltage, and the negative input terminal and the output terminal of the second comparator are connected by a switch.

8. A pixel column readout circuit according to claim 7, characterized in that, The comparator circuit also includes a coupling capacitor, which is electrically connected to the output terminal of the first comparator and the negative output terminal of the second comparator.

9. A pixel column readout circuit according to claim 7, characterized in that, The counter is connected to the output of the second comparator.

10. A pixel column readout circuit according to claim 1, characterized in that, The pixel column readout circuit also includes a latch, which is electrically connected to the output of the counter.

11. An image sensor, characterized in that, include: Photodiodes, and The pixel column readout circuit as described in any one of claims 1 to 10.

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