Refresh operation of memory cells

Abstract

Methods, systems, and devices for refresh operations for memory cells are described. A memory device can include a plurality of rows of memory cells. Each row of memory cells can undergo a certain number of access operations (e.g., read operations, write operations). During a read operation, a logic state of one or more memory cells can be determined by applying a read pulse having a first polarity. Based on the one or more memory cells storing a particular logic state (e.g., a first logic state), a refresh operation can be performed. During the refresh operation, a refresh pulse having a second polarity (e.g., a different polarity than the first polarity) can be applied to the one or more memory cells.

Description

[0001] Cross-references

[0002] This patent application claims priority to U.S. Patent Application No. 15 / 931,131, filed May 13, 2020, entitled “Refresh Operation of a Memory Cell”, by Sinipete et al., which is assigned to the assignee herein and is expressly incorporated herein by reference. Background Technology

[0003] The following text generally refers to one or more memory systems, and more specifically, to refresh operations on memory cells.

[0004] Memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information is stored by programming memory cells within the memory device into different states. For example, a binary memory cell can be programmed to support one of two states, typically indicated by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, a component can read or sense at least one stored state in the memory device. To store information, a component can write states into the memory device or program those states.

[0005] Various types of memory devices and memory cells exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), auto-select memory, chalcogenide memory technology, etc. Memory cells can be volatile or non-volatile. Attached Figure Description

[0006] Figure 1 This describes an example of a system that supports refresh operations of memory cells, based on examples disclosed herein.

[0007] Figure 2 This describes an example of a memory die that supports refresh operations of memory cells, as disclosed in the examples herein.

[0008] Figure 3 This describes an instance of a memory cell that supports refresh operations for memory cells, as illustrated in the examples disclosed herein.

[0009] Figure 4Aand 4B This document provides example timing diagrams illustrating refresh operations for memory cells based on examples disclosed herein.

[0010] Figure 5 A block diagram of a memory device that supports refresh operations of memory cells according to an example disclosed herein is shown.

[0011] Figure 6 and 7 A flowchart illustrating one or more methods for supporting memory cell refresh operations according to examples disclosed herein is shown. Detailed Implementation

[0012] A memory device may comprise a plurality of memory cells arranged in one or more rows (e.g., rows of memory cells). Memory cells within any row can be accessed (e.g., read from, or write to) a memory cell over a period of time. The logic state stored in any memory cell may be based on the voltage distribution of the memory cell and on the polarity of the read pulse applied during a read operation. In some instances, when memory cells have been read for a relatively large period of time, a particular distribution may shift (e.g., move toward a different distribution associated with different logic states). For example, a memory cell programmed to a first logic state may be susceptible to such unintentional shifts, which may increase the likelihood of errors occurring during read operations. Periodically refreshing memory cells can reduce or minimize the likelihood of such errors occurring.

[0013] This document describes a memory device configured to perform refresh operations on one or more memory cells. The memory device may include a controller (or other logic) configured to determine the logical state of the memory cells. The logical state of a memory cell can be determined by applying a pulse (e.g., a read pulse) to the memory cell. Based on the polarity of the read pulse, the memory cell may (or may not) experience a threshold processing event (e.g., a fast return event). Whether a threshold processing event occurs or not indicates whether the memory cell is programmed to a first logical state (e.g., a reset state) or a second logical state (e.g., a set state).

[0014] When a memory cell is determined to be programmed into a first logic state, a refresh operation can be performed to enhance the logic state programmed into the cell. The refresh operation may require applying a pulse with a polarity opposite to the read pulse (e.g., a refresh pulse). In some instances, a refresh pulse may be applied each time a memory cell is determined to be programmed into the first logic state or based on the number of access operations performed on the cell. When a refresh pulse is applied, the first logic state is enhanced, which can mitigate any unintentional shifts in the voltage distribution of the memory cell. Additionally, enhancing the logic state programmed into the memory cell reduces the likelihood of the memory cell's logic state being incorrectly sensed during subsequent read operations.

[0015] First, as referenced Figure 1-3 Features of this disclosure are described in the context of the memory system, die, and array described herein. (See references...) Figure 4A and 4B The features of this disclosure are described in the context of the timing diagrams described herein. This is further illustrated by references to other sources. Figure 5-7 The device diagrams and flowcharts describing the refresh operations of the memory cells further illustrate these and other features of this disclosure, and these and other features of this disclosure are further described with reference to the device diagrams and flowcharts.

[0016] Figure 1 This describes an example of a system 100 that supports refresh operations of memory cells according to examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0017] System 100 may include portions of electronic devices, such as computing devices, mobile computing devices, wireless devices, graphics processing devices, vehicles, or other systems. For example, system 100 may describe aspects of computers, laptop computers, tablet computers, smartphones, cellular phones, wearable devices, internet-connected devices, vehicle controllers, etc. Memory device 110 may be a component of the system that can be used to store data from one or more other components of system 100.

[0018] At least a portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor or other circuitry within a device that uses memory to execute processes (e.g., a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or other fixed or portable electronic device), and other examples. In some examples, host device 105 may refer to hardware, firmware, software, or a combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host or host device 105.

[0019] Memory device 110 may be a separate device or component that can provide physical memory address / space available for use or reference by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices 105. Signaling between host device 105 and memory device 110 may be used to support one or more of the following: modulation schemes for modulating signals, various pin configurations for transmitting signals, various form factors for the physical packages of host device 105 and memory device 110, clock signaling and synchronization between host device 105 and memory device 110, timing conventions, or other factors.

[0020] Memory device 110 may be used to store data of components of host device 105. In some instances, memory device 110 may act as a slave device to host device 105 (e.g., responding to and executing commands provided by host device 105 via external memory controller 120). Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0021] The host device 105 may include one or more of the following components: an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or, for example, one or more peripheral components or one or more input / output controllers. The components of the host device may be coupled to each other using bus 135.

[0022] Processor 125 may be used to provide control or other functionality for at least a portion of system 100 or at least a portion of host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or combinations thereof. In such instances, processor 125 may be an instance of central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or system-on-a-chip (SoC), and other instances. In some instances, external memory controller 120 may be implemented by processor 125 or as part of said processor.

[0023] BIOS component 130 may be a software component containing a BIOS used as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain programs or software stored in read-only memory (ROM), flash memory, or another non-volatile memory.

[0024] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) to support a desired or specified capacity for data storage. Each memory die 160 may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more tiles, one or more segments), wherein each memory cell can be used to store at least one bit of data. Memory device 110 comprising two or more memory dies may be referred to as a multi-die memory or multi-die package, or a multi-chip memory or multi-chip package.

[0025] The device memory controller 155 may include circuitry, logic, or components for controlling the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations and are available to receive, transmit, or execute commands, data, or control information associated with components of the memory device 110. The device memory controller 155 may be used to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0026] In some instances, memory device 110 may receive data or commands, or both, from host device 105. For example, memory device 110 may receive a write command instructing memory device 110 to store data for host device 105 or a read command instructing memory device 110 to provide data stored in memory die 160 to host device.

[0027] A local memory controller 165 (e.g., locally on memory die 160) can be used to control the operation of memory die 160. In some instances, the local memory controller 165 can be used to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155 and local memory controller 165 or external memory controller 120, which can perform the various functions described herein. Thus, the local memory controller 165 can be used to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or combinations thereof. Examples of components that may be included in the device memory controller 155 or the local memory controller 165 or both may include: a receiver for receiving signals (e.g., from an external memory controller 120), a transmitter for transmitting signals (e.g., to an external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other circuitry or controllers that may be used to support the operation of the described device memory controller 155 or the local memory controller 165 or both.

[0028] External memory controller 120 can be used to enable the transfer of one or more of the information, data, or commands between components of system 100 or host device 105 (e.g., processor 125) and memory device 110. External memory controller 120 can translate or translate communications exchanged between components of host device 105 and memory device 110. In some instances, the functionality of external memory controller 120, or another component of system 100 or host device 105, or as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or combinations thereof, implemented by processor 125, system 100, or another component of host device 105. Although external memory controller 120 is depicted as being external to memory device 110, in some instances, the functionality of external memory controller 120, or as described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0029] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 may be used to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device. Each channel 115 may include one or more signal paths or transmission media (e.g., conductors) between ends associated with components of system 100. Signal paths may be examples of conductive paths that can be used to carry signals. For example, channel 115 may include a first end comprising one or more pins or pads at host device 105 and one or more pins or pads at memory device 110. Pins may be examples of conductive input or output points of devices of system 100, and pins may be used to serve as part of a channel.

[0030] Channel 115 (and associated signal paths and endpoints) may be dedicated to transmitting one or more types of information. For example, channel 115 may include one or more command and address (CA) channels 186, one or more clock signal (CK) channels 188, one or more data (DQ) channels 190, one or more other channels 192, or combinations thereof. In some instances, single data rate (SDR) signaling or dual data rate (DDR) signaling may be used to transmit signaling through channel 115. In SDR signaling, one modulation symbol (e.g., signal level) of the signal may be registered for each clock cycle (e.g., on the rising or falling edge of the clock signal). In DDR signaling, two modulation symbols (e.g., signal levels) of the signal may be registered for each clock cycle (e.g., on both the rising and falling edges of the clock signal).

[0031] In some instances, the logical state of one or more memory cells stored in memory array 170 can be determined for performing a refresh operation. The logical state can be written to the memory cells of memory array 170 by applying programming pulses (e.g., write pulses). The pulses can be applied by a controller, such as device memory controller 155 or local memory controller 165, and can be applied with a first polarity (e.g., positive) or a second polarity (e.g., negative). A specific voltage distribution of the memory cells can be set based on the polarity of the programming pulses. During a read operation, a read pulse can be applied with either a first polarity or a second polarity (e.g., by device memory controller 155 or local memory controller 165). Based on the polarity of the pulses (e.g., write pulses and read pulses), the logical state stored in the memory cells can be determined.

[0032] In some cases, it may be necessary to perform refresh operations on specific memory cells of memory array 170. For example, when a memory cell programmed to a specific logical state (e.g., a first logical state) undergoes a relatively large number of read operations without any write operations, its voltage distribution may shift (e.g., move towards a voltage distribution associated with a different logical state). Therefore, it may be beneficial to apply refresh pulses based on the specific logical state of the memory cell, the specific number of read operations performed on the memory cell, or both. Performing refresh operations can mitigate data loss and / or corruption attributable to programmed logical state transitions caused by performing a relatively large number of read operations on the memory cell compared to performing a smaller number of write operations on the memory cell. Additionally or alternatively, performing refresh operations in conjunction with performing read operations can reduce the overall system latency and media management complexity of memory device 110.

[0033] Figure 2 This describes an example of a memory die 200 that supports refresh operations of memory cells, as disclosed herein. The memory die 200 may be used as a reference. Figure 1 Examples of the described memory die 160. In some instances, the memory die 200 may be referred to as a memory chip, memory device, or electronic memory device. The memory die 200 may include one or more memory cells 205, each of which may be programmed to store different logical states (e.g., programmed to be one of a set of two or more possible states). For example, memory cells 205 may be used to store one bit of information at a time (e.g., logic 0 or logic 1). In some instances, memory cells 205 (e.g., multi-level memory cells 205) may be used to store more than one bit of information at a time (e.g., logic 00, logic 01, logic 10, logic 11). In some instances, memory cells 205 may be arranged in an array, as shown in the reference. Figure 1 The memory array 170 is described.

[0034] Memory cell 205 may use configurable materials to store logical states. These configurable materials may be referred to as memory elements, memory storage elements, material elements, material memory elements, material portions, or material portions with write polarity, etc. The configurable materials of memory cell 205 may relate to chalcogenide-based memory components, such as those mentioned above. Figure 3 For more detailed description, chalcogenide storage elements can be used in phase-change memory (PCM) cells, threshold processing memory cells, or self-selection memory cells.

[0035] The memory die 200 may include access lines (e.g., row lines 210 and column lines 215) arranged in a pattern such as a grid pattern. The access lines may be formed of one or more conductive materials. In some instances, row lines 210 may be referred to as word lines. In some instances, column lines 215 may be referred to as digital lines or bit lines. References to access lines, row lines, column lines, word lines, digital lines, or bit lines may be interchanged without affecting understanding or operation. Memory cells 205 may be located at the intersection of row lines 210 and column lines 215.

[0036] Read and write operations can be performed on memory cell 205 by activating or selecting one or more access lines, such as row line 210 or column line 215. A single memory cell 205 at its intersection can be accessed by applying a bias voltage to row line 210 and column line 215 (e.g., applying a voltage to row line 210 or column line 215). In a two-dimensional or three-dimensional configuration, the intersection of row line 210 and column line 215 may be referred to as the address of memory cell 205. Access lines may be conductive lines coupled to memory cell 205 and can be used to perform access operations on memory cell 205.

[0037] Access to memory cell 205 can be controlled via row decoder 220 or column decoder 225. For example, row decoder 220 can receive row addresses from local memory controller 260 and activate row line 210 based on the received row addresses. Column decoder 225 can receive column addresses from local memory controller 260 and activate column line 215 based on the received column addresses.

[0038] Sensing component 230 can be used to detect the state of memory cell 205 (e.g., material state, resistance, threshold state) and determine the logic state of memory cell 205 based on the stored state. Sensing component 230 may include one or more sensing amplifiers to amplify or otherwise convert signals generated by accessing memory cell 205. Sensing component 230 can compare the signal detected from memory cell 205 with reference 235 (e.g., reference voltage). The detected logic state of memory cell 205 can be provided as an output of sensing component 230 (e.g., provided to input / output 240) and can indicate the detected logic state to another component of the memory device including memory die 200.

[0039] The local memory controller 260 can control access to the memory cell 205 through various components (e.g., row decoder 220, column decoder 225, sensing component 230). The local memory controller 260 may be a reference. Figure 1 Examples of local memory controller 165 described herein. In some instances, one or more of row decoder 220, column decoder 225, and sensing component 230 may be co-located with local memory controller 260. Local memory controller 260 may be used to receive one or more commands or data from one or more different memory controllers (e.g., external memory controller 120 associated with host device 105, another controller associated with memory die 200), translate the commands or data (or both) into information usable by memory die 200, perform one or more operations on memory die 200, and transfer data from memory die 200 to host device 105 based on the performance of said one or more operations. Local memory controller 260 may generate row signals and column address signals to activate target row line 210 and target column line 215. Local memory controller 260 may also generate and control various voltages or currents used during operation of memory die 200. Generally, the amplitude, shape, or duration of the applied voltage or current discussed herein may vary and may differ for the various operations discussed when operating the memory die 200.

[0040] The local memory controller 260 can be used to perform one or more access operations on one or more memory cells 205 of the memory die 200. Examples of access operations may include write operations, read operations, refresh operations, precharge operations, or activation operations, etc. In some instances, access operations may be performed or otherwise coordinated by the local memory controller 260 in response to various access commands (e.g., from the host device 105). The local memory controller 260 can be used to perform other access operations not listed herein or other operations related to the operation of the memory die 200 that are not directly related to accessing the memory cells 205.

[0041] The local memory controller 260 can be used to perform write operations (e.g., programming operations) on one or more memory cells 205 of the memory die 200. During a write operation, the memory cells 205 of the memory die 200 can be programmed to store a desired logical state. The local memory controller 260 can identify the target memory cell 205 to which a write operation will be performed. The local memory controller 260 can identify target row lines 210 and target column lines 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target row lines 210 and target column lines 215 (e.g., apply voltage to row lines 210 or column lines 215) to access the target memory cell 205. The local memory controller 260 can apply a specific signal (e.g., a write pulse) to column line 215 during a write operation to store a specific state in the storage element of the memory cell 205. The pulse used as part of the write operation can contain one or more voltage levels for a duration.

[0042] The local memory controller 260 can be used to perform read operations (e.g., sensing operations) on one or more memory cells 205 of the memory die 200. During the read operation, the logical state stored in the memory cells 205 of the memory die 200 can be determined. The local memory controller 260 can identify the target memory cell 205 to which the read operation will be performed. The local memory controller 260 can identify target row lines 210 and target column lines 215 coupled to the target memory cell 205 (e.g., the address of the target memory cell 205). The local memory controller 260 can activate the target row lines 210 and target column lines 215 (e.g., apply a voltage to the row lines 210 or column lines 215) to access the target memory cell 205. The sensing component 230 can detect signals received from the memory cell 205 based on pulses applied to the row lines 210, pulses applied to the column lines, and / or the resistance or threshold characteristics of the memory cell 205. The sensing component 230 can amplify the signals. The local memory controller 260 can activate the sensing component 230 (e.g., a latching sensing component) to compare the signal received from the memory cell 205 with the reference signal 250. Based on the comparison, the sensing component 230 can determine the logic state stored in the memory cell 205. The pulse used as part of the read operation may contain one or more voltage levels over a period of time.

[0043] In some instances, a refresh operation may be performed on memory cell 205. As discussed herein, memory cell 205 may store a logical state based on an applied programming pulse (e.g., a write pulse). The programming pulse may be applied by a controller, such as a local memory controller 260. A write pulse may be applied with a specific polarity that may affect the voltage distribution of memory cell 205. During a read operation, a read pulse may be applied with a specific polarity (e.g., by the local memory controller 260). Based on the polarity of the pulses (e.g., write pulses and read pulses), the logical state stored in memory cell 205 can be determined.

[0044] The local memory controller 260 can perform refresh operations on one or more of the memory cells 205 based on the logical state sensed during a read operation. For example, when a memory cell 205 is programmed to a specific logical state (e.g., a first logical state), the distribution of the memory cells may shift as it undergoes a relatively large number of read operations without experiencing write operations. This shifted distribution may unintentionally cause a memory cell 205 programmed to the first logical state (e.g., logic "1") to be sensed as the second logical state (e.g., logic "0").

[0045] By refreshing memory cell 205, its programmed logic state can be enhanced and made less susceptible to incorrect determination (e.g., sensing). To refresh memory cell 205, the local memory controller 260 may apply a refresh pulse with a polarity different from that of a read command. Applying a refresh pulse with a different polarity may cause memory cell 205 to undergo rapid return events (e.g., rapid changes), which can enhance its initial state (e.g., stored state). Enhancing the initial state of memory cell 205 can mitigate data loss and / or corruption attributable to programmed logic state transitions caused by performing a relatively small number of write operations.

[0046] Figure 3 This describes an example of a memory array 300 as disclosed herein. The memory array 300 may be used as a reference. Figure 1 and 2 An example of a portion of the described memory array or memory die. Memory array 300 may include a first stack 305 of memory cells positioned above a substrate and a second stack 310 of memory cells located above the first array or stack 305. While an example of memory array 300 may include two stacks 305, 310, memory array 300 may include any number of stacks (e.g., one or more).

[0047] The memory array 300 may also include row lines 210-a, 210-b, 210-c, 210-d, column lines 215-a and 215-b, which may be as referenced. Figure 2 Examples of row lines 210 and column lines 215 are described. One or more memory cells in the first stack 305 and the second stack 310 may contain one or more chalcogenide materials in the pillars between the access lines. For example, a single stack between access lines may contain one or more of a first electrode, a first chalcogenide material (e.g., a selector assembly), a second electrode, a second chalcogenide material (e.g., a memory element), or a third electrode. Although Figure 3 Some of the elements included are marked with numerical indicators, while other corresponding elements are not marked, but they are the same or will be understood as similar, in order to increase the visibility and clarity of the depicted features.

[0048] One or more memory cells in the first stack 305 may include one or more of electrodes 325-a, memory elements 320-a, or electrodes 325-b. One or more memory cells in the second stack 310 may include electrodes 325-c, memory elements 320-b, and electrodes 325-d. The memory element 320 may be an example of a chalcogenide material, such as a phase change memory element, a threshold processing memory element, or a self-selecting memory element. In some instances, the memory cells in the first stack 305 and the second stack 310 may have a common conductor, such that corresponding memory cells in one or more stacks 305 and one or more stacks 310 may share column line 215 or row line 210. For example, the first electrode 325-c of the second stack 310 and the second electrode 325-b of the first stack 305 may be coupled to column line 215-a, such that column line 215-a can be shared by vertically adjacent memory cells.

[0049] In some instances, the material of the storage element 320 may comprise a chalcogenide material or other alloy, comprising selenium (Se), tellurium (Te), arsenic (As), antimony (Sb), carbon (C), germanium (Ge), silicon (Si), or indium (In), or various combinations thereof. In some embodiments, a chalcogenide material primarily comprising selenium (Se), arsenic (As), and germanium (Ge) may be referred to as a SAG alloy. In some instances, the SAG alloy may also comprise silicon (Si), and such a chalcogenide material may be referred to as a SiSAG alloy. In some instances, the SAG alloy may comprise silicon (Si) or indium (In), or combinations thereof, and such a chalcogenide material may be referred to accordingly as a SiSAG alloy or an InSAG alloy, or combinations thereof. In some instances, the chalcogenide glass may comprise additional elements, such as hydrogen (H), oxygen (O), nitrogen (N), chlorine (Cl), or fluorine (F), each in atomic or molecular form.

[0050] In some instances, storage element 320 may be an example of a self-selecting memory cell. In such instances, the material used in storage element 320 may be based on an alloy (e.g., the alloys listed above) and operable to undergo changes in different physical states during normal operation of the memory cell. For example, a self-selecting memory cell may have a high threshold voltage state and a low threshold voltage state. The high threshold voltage state may correspond to a first logic state (e.g., a RESET state), and the low threshold voltage state may correspond to a second logic state (e.g., a SET state). When a memory cell is written to, its logic state may be enhanced so that its logic state can be accurately detected (e.g., sensed). However, when a memory cell undergoes relatively few writes over a period of time, its state may slowly shift. For example, if a memory cell is programmed to a high threshold voltage state (e.g., a RESET state) and undergoes relatively few writes over a period of time, the memory cell may slowly shift toward a low threshold voltage. When a certain number of reads are performed without any write operations or a relatively small number of write operations are performed over a period of time, the shift in threshold voltage may cause errors in the data. Therefore, it may be desirable to periodically issue read refresh commands as described in this paper to improve the state of some memory cells and mitigate threshold voltage skew.

[0051] In some instances, such as for threshold processing memory cells or auto-select memory cells, some or all of the set of logic states supported by the memory cell may be associated with the amorphous states of the chalcogenide material (e.g., a material in a single state can be used to store different logic states). During programming (writing) operations of an auto-select memory cell (e.g., comprising electrode 325-a, memory element 320-a, and electrode 325-b), the polarity of the write operation may affect (determine, set, program) specific behavior or characteristics of the material of memory element 320, such as the threshold voltage of the material. Differences in the threshold voltage of the material of memory element 320 depending on the logic states stored by the material of memory element 320 (e.g., the difference between the threshold voltage when the material is storing logic state '0' and when the material is storing logic state '1') may correspond to the read window of memory element 320.

[0052] In some instances, the architecture of memory array 300 may be referred to as a crosspoint architecture, where memory cells are formed at topological intersections between row lines 210 and column lines 215. This crosspoint architecture can provide relatively high-density data storage at a lower manufacturing cost compared to other memory architectures. For example, the crosspoint architecture may have memory cells with a smaller area and thus a higher memory cell density compared to other architectures. For example, compared to other architectures with a memory cell area of ​​6F² (e.g., those with three-terminal selector elements), the architecture may have a memory cell area of ​​4F², where F is the minimum feature size. For example, DRAM may use transistors, which are three-terminal devices, as selector elements for each memory cell and may have a larger memory cell area compared to the crosspoint architecture.

[0053] Although Figure 3 The example illustrates two memory stacks, but other configurations are possible. In some instances, a single memory stack of memory cells can be constructed above a substrate, which may be referred to as a two-dimensional memory. In some instances, two or more stacks of memory cells can be configured in a similar manner in a three-dimensional cross-point architecture. Additionally, in some cases, Figure 3 The elements shown or described herein may be electrically coupled to each other as shown or described but physically rearranged (e.g., storage element 320 and possible selection element or electrode 325 may be electrically connected in series between row line 210 and column line 215, but do not need to be in a column or stack configuration).

[0054] Figure 4A This document describes an example of timing diagram 400-a supporting refresh operations on memory cells, as disclosed herein. Timing diagram 400-a illustrates various aspects of a read operation performed on a memory cell. Specifically, timing diagram 400-a illustrates the voltages applied to a first access line 405-a (e.g., a word line) and a second access line 410-a (e.g., a bit line). The logical state of a memory cell can be determined (e.g., programmed) during a write operation based on the voltages applied to the first access line 405-a and the second access line 410-a, and the voltage distribution of the memory cell set.

[0055] exist Figure 4APrior to the read operation shown, a write operation can be performed on the memory cell. To write data to one or more memory cells, a write access bias (e.g., a write pulse, write voltage) can be applied across the memory cells. For example, a write access bias of a first polarity can be applied to the memory cell to program a SET state. When the SET state is programmed, the memory cell may experience a high-threshold to low-threshold transition attributable to current (e.g., current associated with the SET state) flowing through the memory cell. In other instances, a write access bias of a second polarity (e.g., different polarity, opposite polarity) can be applied to the memory cell to program a RESET state. When the RESET state is programmed, the memory cell may experience a low-threshold to high-threshold transition attributable to current (e.g., RESET current) flowing through the memory cell. Figure 4A The memory cell associated with the read operation described herein may include a SET state (e.g., a second logic state).

[0056] When performing a read or write operation, an access bias can be applied across the memory cell. This access bias can be applied across the memory cell by applying a voltage to the first access line 405-a and / or the second access line 410-a. For example, to apply a first access bias (e.g., an access bias with a first polarity) to the memory cell, the first access line 405-a can be driven to a relatively high voltage, and the second access line 410-a can be driven to a relatively low voltage. Similarly, to apply a second access bias (e.g., an access bias with a second polarity) to the memory cell, the second access line 410-a can be driven to a relatively high voltage, and the first access line 405-a can be driven to a relatively low voltage. Figure 4A As shown, the memory cell may have been programmed (e.g., written) and read using a write access bias with a first polarity.

[0057] At t1, a read pulse can be applied to the memory cell. The read pulse can be applied with a first polarity, where the first access line 405-a is driven to a relatively high voltage and the second access line 410-a is driven to a relatively low voltage. In some instances, the access lines can be driven by a controller coupled to one or more voltage sources. For example, the controller can receive a read command (e.g., from a host device) and can initiate the application of voltage to the corresponding access line. Alternatively, the read pulse can be applied with a second polarity (not shown), which may be a design choice for determining the logic state of the memory cell.

[0058] During period t1, the voltage of the first access line 405-a may increase, and the voltage of the second access line 410-a may decrease. In some instances, the first access line 405-a and the second access line 410-a may reach corresponding threshold voltages and may remain at the corresponding threshold voltages for a period of time. While the first access line 405-a and the second access line 410-a remain at the corresponding threshold voltages and do not undergo changes (e.g., a fast return event), the memory cell may store a first logic state (e.g., a RESET state).

[0059] At t2, a memory cell may experience a fast return event based on the application of a read pulse. A fast return event is characterized by a sudden change in the bias voltage across the memory cell. For example, a fast return event can be described by a decrease in the voltage across the first access line 405-a and an increase in the voltage across the second access line 410-a, followed by a gradual increase in the voltage across the first access line 405-a and a gradual decrease in the voltage across the second access line 410-a. The occurrence of a fast return event may indicate that the memory cell is programmed into a second logic state (e.g., a SET state). A memory cell programmed into a SET state may be less susceptible to offsets in its voltage distribution. For example, a memory cell may have a high threshold voltage state and a low threshold voltage state. The low threshold voltage state may correspond to the SET state and may therefore deviate less (e.g., less towards 0V) compared to a high threshold state (e.g., a RESET state). Therefore, when it is determined that a memory cell is programmed into a SET state, the memory controller (or another device) may avoid applying a refresh pulse to the memory cell.

[0060] At t3, a read pulse can be removed from the memory cell. When the read pulse is removed, the voltage across the first access line 405-a and the second access line 410-a may dissipate over the duration of t3. Figure 4A The durations of intervals t1, t2, and t3 shown are for illustrative purposes only. In other instances (not shown), the duration of any of t1, t2, or t3 may be longer or shorter than the durations shown.

[0061] Figure 4BThis document illustrates an example of timing diagram 400-b supporting refresh operations on memory cells, as disclosed herein. Timing diagram 400-b illustrates various aspects of read and refresh operations performed on memory cells. Specifically, timing diagram 400-a illustrates the voltages applied to a first access line 405-b (e.g., a word line) and a second access line 410-b (e.g., a bit line) during read and refresh operations. During a read operation, the logic state of a memory cell can be determined (e.g., programmed) based on the voltages applied to the first access line 405-b and the second access line 410-b, and the voltage distribution of the memory cell set, during a write operation. Based on the logic state of the memory cell, a refresh pulse can be applied, which may enhance the programmed logic state of the memory cell.

[0062] exist Figure 4B A write operation can be performed on a memory cell before the read operation shown. (See reference...) Figure 4A As discussed, in order to write data to one or more memory cells, write access biases (e.g., write pulses, write voltages) can be applied across the memory cells. (The last sentence appears to be incomplete and possibly refers to a different topic.) Figure 4B The memory cell associated with the read operation described herein may include a RESET state (e.g., a first logic state).

[0063] When performing a read or write operation, an access bias can be applied across the memory cell. This access bias can be applied across the memory cell by applying a voltage to the first access line 405-b and / or the second access line 410-b. Figure 4B As shown, the memory cell may have been programmed (e.g., written) using a write access bias with a second polarity, read using a read access bias with a first polarity, and refreshed using a refresh access bias with a second polarity.

[0064] At t1, a read pulse can be applied to the memory cell. The read pulse can be applied with a first polarity, where the first access line 405-b is driven to a relatively high voltage and the second access line 410-b is driven to a relatively low voltage. In some instances, the access lines can be driven by a controller coupled to one or more voltage sources. For example, the controller can receive a read command (e.g., from a host device) and can initiate the application of voltage to the corresponding access line. Alternatively, the read pulse can be applied with a second polarity (not shown), which may be a design choice for determining the logic state of the memory cell.

[0065] During period t1, the voltage of the first access line 405-b may increase, and the voltage of the second access line 410-b may decrease. In some instances, the first access line 405-b and the second access line 410-b may reach corresponding threshold voltages and may remain at the corresponding threshold voltages for a period of time. While the first access line 405-b and the second access line 410-b remain at the corresponding threshold voltages and do not undergo changes (e.g., a fast return event), the memory cell may store a first logic state (e.g., a RESET state).

[0066] At tl, a memory cell may experience a fast return event based on the application of a read pulse. Alternatively, the voltages across the first access lines 405-b and 410-b may remain relatively constant. The absence of a fast return event may indicate that the memory cell is programmed into a first logic state (e.g., a RESET state). A memory cell programmed into a RESET state may be susceptible to voltage distribution shifts. Therefore, when it is determined that a memory cell is programmed into a RESET state, the memory controller (or another device) may apply a refresh pulse to the memory cell.

[0067] At t2, a read pulse can be removed from the memory cell. When the read pulse is removed, the voltage across the first access line 405-b and the second access line 410-b may dissipate over the duration of t2. Once the read pulse is removed (or the voltage across the first access lines 405-b and 410-b is negligible), a refresh pulse can be applied to the memory cell.

[0068] At t3, a refresh pulse may be applied to the memory cell. A read pulse may be applied with a second polarity, wherein the second access line 410-b is driven to a relatively high voltage and the first access line 405-b is driven to a relatively low voltage. The refresh pulse may be applied by a controller coupled to a voltage source described herein. For example, the controller may receive a refresh command (e.g., from a host device) and may initiate the application of voltage to the respective access line. In some instances, each of the write pulse, read pulse, and refresh pulse may have different magnitudes (e.g., be applied with different magnitudes). For example, the read pulse may have a first magnitude, the write pulse may have a second magnitude different from the first magnitude, and the refresh pulse may have a third magnitude different from the first and second magnitudes.

[0069] Alternatively, write pulses, read pulses, and refresh pulses can be applied with different polarities. For example, a refresh pulse can be applied with a first polarity (not shown), which may be a design choice for determining the logic state of a memory cell. In this example, a write pulse can also be applied with a first polarity such that a fast return event occurs when a read pulse is applied. When using such polarities, the detection of a fast return event can indicate that the memory cell is programmed to a RESET state, which indicates that the memory cell may have undergone a refresh operation.

[0070] During t3, the voltage across the second access line 410-b may increase, and the voltage across the first access line 405-a may decrease. In some instances, the first access line 405-a and the second access line 410-a may reach corresponding threshold voltages, and the memory cell may experience a fast return event. A fast return event may be characterized by a decrease in voltage across the second access line 410-b and an increase in voltage across the first access line 405-b, followed by a gradual increase in voltage across the second access line 410-b and a gradual decrease in voltage across the first access line 405-b. The occurrence of a fast return event can enhance the logical state programmed into the memory cell (e.g., a RESET state). Enhancing the logical state of the memory cell can mitigate the voltage distribution shift of the memory cell, which can reduce the likelihood of errors occurring when reading (e.g., sensing) the memory cell during subsequent read operations.

[0071] In some instances, the frequency of refresh operations can be configurable. For example, a refresh operation can be performed whenever a read operation is performed on a memory cell programmed to the RESET state. Alternatively, a refresh operation can be performed after a certain duration. For example, a refresh operation can be performed on a memory cell programmed to the RESET state after N seconds, where N is a positive real number. Performing refresh operations at this frequency can improve the overall reliability of the system, but may increase the power consumption and latency associated with access operations.

[0072] In other instances, the associated memory device can be configured to track the number of access operations (e.g., read operations) performed on memory cells, rows of memory cells, banks of memory cells, or any number of memory cells. Once the number of access operations meets a threshold, a refresh operation can be performed on the memory cell. In some instances, a counter can be used to track the number of access operations, or the number of access operations can be tracked by the controller or other logic of the associated memory device. Performing refresh operations at this frequency can reduce the power consumption and latency associated with access operations compared to performing a refresh operation whenever a RESET state is sensed.

[0073] In another example, the associated memory device can be configured to track the number of access operations (e.g., read and write operations) performed on memory cells, rows of memory cells, banks of memory cells, or any number of memory cells. A refresh operation can be performed when a memory cell has undergone a threshold number of read operations without any write operations. In some instances, a counter can be used to track the number of access operations, or the number of access operations can be tracked by the controller or other logic of the associated memory device. Performing refresh operations at this frequency can further reduce the power consumption and latency associated with access operations after performing a threshold number of read operations, relative to performing a refresh operation.

[0074] At t4, a refresh pulse can be removed from the memory cell. When the refresh pulse is removed, the voltage across the first access line 405-b and the second access line 410-b may dissipate over the duration of t4. Figure 4B The durations of intervals t1, t2, t3, and t4 shown are for illustrative purposes only. In other instances (not shown), the duration of any of t1, t2, t3, or t4 may be longer or shorter than the durations shown.

[0075] Figure 5 A block diagram 500 illustrates a memory device 505 supporting refresh operations of memory cells according to an example disclosed herein. The memory device 505 may be as described in the reference... Figure 1 Examples of various aspects of the memory device described in section 4. Memory device 505 may include signal component 510, logic component 515, and counter 520. Each of these components may communicate with each other directly or indirectly (e.g., via one or more buses).

[0076] Signal component 510 may apply a read pulse of first polarity to a memory cell to perform a read operation on the memory cell. In some instances, signal component 510 may apply a refresh pulse of a second polarity different from the first polarity to the memory cell based on determining that the memory cell stores a first logic state. In some instances, signal component 510 may avoid applying a refresh pulse based on determining that the value of a counter fails to meet a threshold.

[0077] In some instances, signal component 510 may apply a first write pulse having a second polarity to a memory cell, wherein the memory cell contains a first logic state having a first distribution based on the applied first write pulse, wherein a read pulse is applied based on the applied first write pulse. In some instances, signal component 510 may apply a second write pulse having a first polarity to a memory cell, wherein the memory cell contains a second logic state having a second distribution different from the first distribution based on the applied second write pulse.

[0078] In some cases, the read pulse contains a first value, the write pulse contains a second value different from the first value, and the refresh pulse contains a third value different from the first and second values. In some cases, the first and second polarities are opposite.

[0079] Logic component 515 can determine whether a memory cell stores a first logic state or a second logic state based on an applied read pulse, wherein the first logic state is associated with a write pulse having a second polarity different from the first polarity of the read pulse. In some instances, logic component 515 can determine that the memory cell stores a second logic state based on an applied read pulse, wherein the second logic state is associated with a write pulse having a first polarity. In some instances, logic component 515 can avoid applying a refresh pulse based on determining that the memory cell stores a second logic state. In some instances, logic component 515 can detect a fast return event associated with the memory cell based on an applied read pulse.

[0080] In some instances, a device such as a controller (e.g., a local memory controller) may determine whether the value of counter 520 meets a threshold based on a read pulse applied to signal component 510. The value of the counter may be associated with the number of access operations performed on the memory cell. In some instances, a refresh pulse is applied based on determining that the counter value meets the threshold. In some instances, counter 520 may be incremented based on a read pulse applied to the memory cell, wherein determining that the counter value meets the threshold is based on incrementing.

[0081] Figure 6 A flowchart illustrating one or more methods 600 for refreshing memory cells according to examples disclosed herein is shown. The operation of method 600 can be implemented by a memory device or its components as described herein. For example, the operation of method 600 can be implemented by, as referenced herein... Figure 5 The described memory device performs the function. In some instances, the memory device can execute a set of instructions to control the functional elements of the memory device, thereby performing the described function. Alternatively, the memory device can use dedicated hardware to perform aspects of the described function.

[0082] At 605, the memory device may apply a read pulse of first polarity to a memory cell to perform a read operation on the memory cell. The operation at 605 may be performed according to the method described herein. In some instances, it may be performed as described in the reference... Figure 5 The described signal components are used to perform various aspects of the operation of 605.

[0083] At 610, the memory device can determine whether a memory cell stores a first logic state or a second logic state based on an applied read pulse, wherein the first logic state is associated with a write pulse having a second polarity different from the first polarity of the read pulse. The operation of 610 can be performed according to the method described herein. In some instances, it can be performed as described in the reference... Figure 5 The described logical component performs various aspects of the operation of 610.

[0084] At 615, the memory device may apply a refresh pulse with a second polarity different from the first polarity to the memory cell based on determining that the memory cell stores a first logic state. The operation at 615 can be performed according to the method described herein. In some instances, it can be performed as described in reference... Figure 5 The described signal components are used to perform various aspects of the operation of 615.

[0085] In some instances, the device as described herein may perform one or more methods, such as method 600. The device may include features, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) for: applying a read pulse having a first polarity to a memory cell to perform a read operation on the memory cell; determining, based on the applied read pulse, whether the memory cell stores a first logical state or a second logical state, wherein the first logical state is associated with a write pulse having a second polarity different from the first polarity of the read pulse; and applying a refresh pulse having a second polarity different from the first polarity to the memory cell based on the determination that the memory cell stores the first logical state.

[0086] Some examples of the method 600 and device described herein may further include operations, features, components, or instructions for: determining, based on the application of a read pulse, that a memory cell stores a second logic state, wherein the second logic state may be associated with a write pulse having a first polarity, the method further comprising the following.

[0087] In some instances of the method 600 and device described herein, determining whether a memory cell stores a first logic state or a second logic state may include operations, features, components, or instructions for: detecting a fast return event associated with the memory cell based on the application of a read pulse.

[0088] Some instances of the method 600 and apparatus described herein may further include operations, features, components, or instructions for: determining, based on the application of a read pulse, whether the value of a counter associated with an access operation performed on a memory cell satisfies a threshold, wherein the application of a refresh pulse may be based on the determination that the value of the counter satisfies the threshold.

[0089] Some instances of the method 600 and device described herein may further include operations, features, components, or instructions for: incrementing a counter based on applying a read pulse to a memory cell, wherein determining that the value of the counter satisfies a threshold may be based on the increment.

[0090] Some instances of the method 600 and device described herein may further include operations, features, components, or instructions for: avoiding the application of a refresh pulse based on determining that the value of a counter has failed to meet a threshold.

[0091] Some instances of the method 600 and device described herein may further include operations, features, components, or instructions for: applying a first write pulse having a second polarity to a memory cell, wherein the memory cell contains a first logic state having a first distribution based on the application of the first write pulse, wherein the application of a read pulse may be based on the application of the first write pulse.

[0092] Some instances of the method 600 and device described herein may further include operations, features, components, or instructions for: applying a second write pulse having a first polarity to a memory cell, wherein the memory cell contains a second logic state having a second distribution based on the application of the second write pulse, which is different from the first distribution.

[0093] In some instances of the method 600 and device described herein, the read pulse contains a first value, the write pulse contains a second value different from the first value, and the refresh pulse contains a third value different from the first and second values.

[0094] In some instances of the method 600 and device described herein, the first polarity and the second polarity may be opposite polarities.

[0095] Figure 7 A flowchart illustrating one or more methods 700 for refreshing memory cells according to examples disclosed herein is shown. The operation of method 700 can be implemented by a memory device or its components as described herein. For example, the operation of method 700 can be implemented by, as referenced herein... Figure 5 The described memory device performs the function. In some instances, the memory device can execute a set of instructions to control the functional elements of the memory device, thereby performing the described function. Alternatively, the memory device can use dedicated hardware to perform aspects of the described function.

[0096] At 705, the memory device may apply a read pulse of first polarity to a memory cell to perform a read operation on the memory cell. The operation at 705 may be performed according to the method described herein. In some instances, it may be performed as described in the reference... Figure 5 The described signal components are used to perform various aspects of the operation of 705.

[0097] At 710, the memory device can determine whether the value of a counter associated with an access operation performed on a memory cell meets a threshold based on the application of a read pulse, wherein the application of a refresh pulse is based on the determination that the value of the counter meets the threshold. The operation at 710 can be performed according to the method described herein. In some instances, it can be performed as described in the reference... Figure 5 The counter described is used to perform various aspects of the operation of 710.

[0098] At 715, the memory device can determine whether a memory cell stores a first logic state or a second logic state based on an applied read pulse, wherein the first logic state is associated with a write pulse having a second polarity different from the first polarity of the read pulse. The operation of 715 can be performed according to the method described herein. In some instances, it can be done as described in the reference... Figure 5 The described logical components are used to perform various aspects of the 715 operation.

[0099] At 720, the memory device may apply a refresh pulse with a second polarity different from the first polarity to the memory cell based on determining that the memory cell stores a first logic state. The operation at 720 can be performed according to the method described herein. In some instances, it can be performed as described in reference... Figure 5 The described signal components are used to perform various aspects of the operation of the 720.

[0100] It should be noted that the methods described above describe possible implementations, and the operations and steps can be rearranged or otherwise modified, and other implementations are also possible. Furthermore, two or more parts from the methods described can be combined.

[0101] An apparatus is described. The apparatus may include: a memory array comprising a collection of memory cells, each comprising a chalcogenide memory element; a logic component coupled to the memory array and configured to determine whether a memory cell in the collection of memory cells stores a first logic state or a second logic state; and a signal component coupled to the logic component and the memory array, wherein the signal component is configured to apply a read pulse of a first polarity to one or more memory cells in the collection of memory cells, and to apply a refresh pulse of a second polarity different from the first polarity to one or more memory cells in the collection of memory cells based on the fact that one or more memory cells contain the first logic state.

[0102] Some instances of the device may include: a counter associated with an access operation performed on a memory cell and coupled to a signaling component, wherein the counter may be configured to increment based on a read pulse applied to the memory cell, and wherein a refresh pulse may be applied based on whether the value of the counter meets a threshold.

[0103] In some instances, signal components can be configured to avoid applying refresh pulses based on a counter value being less than a threshold.

[0104] In some instances, logic components may be configured to determine that a memory cell stores a second logic state based on the application of a read pulse, and signal components may be configured to avoid applying a refresh pulse based on the memory cell containing the second logic state.

[0105] In some instances, logic components can be configured to determine that a memory cell stores a first logic state by detecting a fast return event associated with the memory cell after a read pulse can be applied.

[0106] In some instances, the signal components may be configured to apply a first write pulse containing a second polarity to a memory cell, wherein the memory cell contains a first logic state having a first distribution based on the application of the first write pulse.

[0107] In some instances, the signal component may be configured to apply a second write pulse containing a first polarity to a memory cell, wherein the memory cell contains a second logic state having a second distribution based on the application of the second write pulse, which is different from the first distribution.

[0108] In some instances, the read pulse contains a first value, the write pulse contains a second value different from the first value, and the refresh pulse contains a third value different from the first and second values.

[0109] An apparatus is described. The apparatus may include: a memory array comprising a collection of memory cells, each comprising a chalcogenide storage element; and a controller coupled to the memory array and configured such that the apparatus: applies a read pulse of a first polarity to a memory cell of the memory array to perform a read operation on the memory cell; determines, based on the applied read pulse, whether the memory cell stores a first logic state or a second logic state, wherein the first logic state is associated with a write pulse of a second polarity different from the first polarity of the read pulse; and applies a refresh pulse of a second polarity different from the first polarity to the memory cell based on the determination that the memory cell stores the first logic state.

[0110] Some examples may further include: determining that a memory cell stores a second logic state based on the application of a read pulse, wherein the second logic state may be associated with a write pulse having a first polarity; and avoiding the application of a refresh pulse based on the determination that the memory cell stores a second logic state.

[0111] Some instances may further include detecting fast return events associated with memory cells based on the application of a read pulse.

[0112] Some examples may further include: incrementing a counter associated with an access operation performed on a memory cell based on applying a read pulse to the memory cell; and determining whether a value meets a threshold based on incrementing the counter, wherein applying a refresh pulse may be based on the value of the counter meeting the threshold.

[0113] Some instances may further include: avoiding applying a refresh pulse based on the determination that the value of a counter fails to meet a threshold.

[0114] Some examples may further include: applying a first write pulse having a second polarity to a memory cell, wherein the memory cell contains a first logic state having a first distribution based on the application of the first write pulse, wherein the application of a read pulse may be based on the application of the first write pulse; and applying a second write pulse having a first polarity to a memory cell, wherein the memory cell contains a second logic state having a second distribution different from the first distribution based on the application of the second write pulse.

[0115] In some instances, the first polarity contains either a positive or a negative polarity, and the second polarity contains the opposite polarity of the first polarity.

[0116] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description. Some diagrams may show signals as single signals; however, those skilled in the art will understand that the signals may represent signal buses, where the buses may have various bit widths.

[0117] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to the relationship between components that enable the flow of signals between them. Components are considered to be in electronic communication (or in conductive contact, connected, or coupled) with each other if there exists any conductive path between them that enables the flow of signals at any given time. At any given time, the conductive path between components that are in electronic communication (or in conductive contact, connected, or coupled) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path or an indirect conductive path, which may include intermediate components such as switches, transistors, or other components. In some instances, one or more intermediate components, such as switches or transistors, can be used to interrupt the flow of signals between connected components for a period of time.

[0118] The term "coupling" refers to the condition that shifts from an open-circuit relationship between components to a closed-circuit relationship, in which a signal is currently unable to travel between the components via a conductive path, and in which a signal can travel between the components via the conductive path. When a component, such as a controller, couples other components together, the component initially allows a change in the flow of signals between the other components via conductive paths that were previously not permitted.

[0119] The term "isolation" refers to a relationship between components in which signals are currently unable to flow between them. Components are isolated from each other if there is an open circuit between them. For example, components isolated by a switch positioned between two components are isolated from each other when the switch is open. When a controller isolates two components, it prevents signals from flowing between the components using previously permitted conductive paths.

[0120] As used herein, the term "electrode" can refer to an electrical conductor and, in some instances, can be used as an electrical contact to a memory cell or other component of a memory array. An electrode may comprise traces, wires, conductive lines, conductive layers, etc., that provide a conductive path between elements or components of the memory array.

[0121] The devices containing memory arrays discussed herein can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, and gallium nitride. In some instances, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by using doping with various chemical species including, but not limited to, phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate, either by ion implantation or by any other doping method.

[0122] The switching components or transistors discussed herein may represent field-effect transistors (FETs) and include a three-terminal device comprising a source, drain, and gate. These terminals may be connected to other electronic components via a conductive material, such as a metal. The source and drain may be conductive and may comprise heavily doped (e.g., degenerate) semiconductor regions. The source and drain may be separated by lightly doped semiconductor regions or channels. If the channel is n-type (i.e., most carriers are signals), the FET may be called an n-type FET. If the channel is p-type (i.e., most carriers are holes), the FET may be called a p-type FET. The channel may be end-capped with an insulating gate oxide. The channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can make the channel conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "off" or "deactivated."

[0123] The description herein, illustrated with reference to the accompanying drawings, describes an example configuration and does not represent all instances that can be implemented or that are within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" and is not "preferred" or "superior" to other instances. The detailed description includes specific details to provide an understanding of the described techniques. However, these techniques can be practiced without these specific details. In some cases, well-known structures and apparatuses are shown in block diagram form to avoid obscuring the concepts of the described instances.

[0124] In the accompanying drawings, similar components or features may have the same reference numerals. Additionally, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral used to differentiate them among similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components that have the same first reference numeral but are independent of the second reference numeral.

[0125] The information and signals described herein can be represented using any of a variety of different techniques and methods. For example, voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or light particles, or any combination thereof, can be used to represent data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description.

[0126] The various illustrative blocks and components described in connection with the disclosure herein can be implemented or executed using a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic, discrete hardware component or any combination thereof designed to perform the functions described herein. The general-purpose processor may be a microprocessor, but alternatively, the processor may be any processor, controller, microcontroller or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0127] The functionality described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functionality can be stored on or transmitted via a computer-readable medium as one or more instructions or code. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functionality described above can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functionality can also be physically located in various locations, including distributions such that portions of the functionality are implemented in different physical locations. Similarly, as used herein (included in the claims), "or" as used in a list of items (e.g., a list of items ending with phrases such as "at least one of" or "one or more of") indicates an inclusive list, such that a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Similarly, as used herein, the phrase "based on" should not be construed as referring to a set of closing conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same way as the phrase "at least partially based on".

[0128] The description herein is provided to enable those skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein may be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but is given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method comprising: A read pulse of first polarity is applied to the memory cell to perform a read operation on the memory cell; The determination of whether the memory cell stores a first logic state or a second logic state is based at least in part on the application of the read pulse, wherein the first logic state is associated with a write pulse having a second polarity different from the first polarity of the read pulse; as well as The refresh pulse having a second polarity different from the first polarity is applied to the memory cell for a period of time, at least in part based on determining that the memory cell stores the first logical state, wherein the refresh pulse is applied for at least part of the period of time, and a fast return event associated with the memory cell occurs during at least a portion of the period of time.

2. The method according to claim 1, wherein determining whether the memory cell stores the first logical state or the second logical state comprises: The method further includes determining that the memory cell stores the second logic state based at least in part on the application of the read pulse, wherein the second logic state is associated with a write pulse having the first polarity: The refresh pulse is avoided at least in part based on the determination that the memory cell stores the second logic state.

3. The method according to claim 1, wherein determining whether the memory cell stores the first logical state or the second logical state comprises: The fast return event associated with the memory cell is detected at least in part based on the application of the read pulse.

4. The method of claim 1, further comprising: The value of a counter associated with an access operation performed on the memory cell is determined at least in part based on the application of the read pulse, wherein the refresh pulse is applied at least in part based on the determination that the value of the counter satisfies the threshold.

5. The method of claim 4, further comprising: The counter is incremented at least in part based on applying the read pulse to the memory cell, wherein determining that the value of the counter satisfies the threshold is at least in part based on the increment.

6. The method of claim 5, further comprising: The refresh pulse is avoided at least in part based on the determination that the value of the counter fails to meet the threshold.

7. The method of claim 1, further comprising: A first write pulse having the second polarity is applied to the memory cell, wherein the memory cell includes a first logic state having a first distribution at least partially based on the application of the first write pulse, wherein the read pulse is applied at least partially based on the application of the first write pulse.

8. The method of claim 7, further comprising: A second write pulse having the first polarity is applied to the memory cell, wherein the memory cell includes a second logic state having a second distribution that is at least partially based on the second distribution based on the application of the second write pulse, different from the first distribution.

9. The method of claim 1, wherein the read pulse includes a first value, the write pulse includes a second value different from the first value, and the refresh pulse includes a third value different from the first value and the second value.

10. The method of claim 1, wherein the first polarity and the second polarity are opposite polarities.

11. An apparatus comprising: A memory array comprising multiple memory cells, each including a chalcogenide memory element; A logic component coupled to the memory array and configured to determine whether a memory cell among the plurality of memory cells stores a first logic state or a second logic state; as well as A signal component coupled to the logic component and the memory array, wherein the signal component is configured to apply a read pulse of a first polarity to one or more of the plurality of memory cells, and to apply a refresh pulse of a second polarity different from the first polarity to one or more of the plurality of memory cells for a duration based on the one or more memory cells including the first logic state, wherein a fast return event associated with the one or more memory cells occurs during at least a portion of the duration based on the application of the refresh pulse during the duration.

12. The device according to claim 11, further comprising: A counter associated with and coupled to the signal component of an access operation performed on the memory cell, wherein the counter is configured to increment at least in part based on the read pulse applied to the memory cell, wherein the refresh pulse is applied at least in part based on whether the value of the counter meets a threshold.

13. The device of claim 12, wherein the signal component is configured to avoid applying the refresh pulse, at least in part based on the fact that the value of the counter is less than the threshold.

14. The device according to claim 11, wherein: The logic component is configured to determine, at least in part, that the memory cell stores the second logic state based on the applied read pulse; and The signal components are configured to avoid applying the refresh pulse, at least in part, based on the memory cell including the second logic state.

15. The device of claim 11, wherein the logic component is configured to determine that the memory cell stores the first logic state by detecting a fast return event associated with the memory cell after the read pulse is applied.

16. The device of claim 11, wherein the signal component is configured to apply a first write pulse including the second polarity to the memory cell, wherein the memory cell includes the first logic state having at least in part based on a first distribution based on the application of the first write pulse.

17. The device of claim 16, wherein the signal component is configured to apply a second write pulse including the first polarity to the memory cell, wherein the memory cell includes a second logic state having a second distribution that is at least partially based on the second write pulse, different from the first distribution.

18. The device of claim 16, wherein the read pulse includes a first value, the first write pulse includes a second value different from the first value, and the refresh pulse includes a third value different from the first value and the second value.

19. An apparatus comprising: A memory array comprising multiple memory cells, each containing a chalcogenide memory element; as well as A controller, coupled to the memory array and configured such that the device: A read pulse of first polarity is applied to a memory cell of the memory array to perform a read operation on the memory cell; The determination of whether the memory cell stores a first logic state or a second logic state is based at least in part on the application of the read pulse, wherein the first logic state is associated with a write pulse having a second polarity different from the first polarity of the read pulse; as well as The refresh pulse having a second polarity different from the first polarity is applied to the memory cell for a period of time, at least in part based on determining that the memory cell stores the first logical state, wherein the refresh pulse is applied for at least part of the period of time, and a fast return event associated with the memory cell occurs during at least a portion of the period of time.

20. The device of claim 19, wherein the controller is configured such that the device: The memory cell stores the second logic state based at least in part on the application of the read pulse, wherein the second logic state is associated with a write pulse having the first polarity; and The refresh pulse is avoided at least in part based on the determination that the memory cell stores the second logic state.

21. The device of claim 19, wherein the controller is configured such that the device determines that the memory cell stores the first logical state by: The fast return event associated with the memory cell is detected at least in part based on the application of the read pulse.

22. The device of claim 19, wherein the controller is configured such that the device: At least in part, based on incrementing a counter associated with an access operation performed on the memory cell by applying the read pulse to the memory cell; and The value of the counter is determined at least in part based on incrementing the counter to determine whether the value of the counter meets a threshold, wherein the refresh pulse is applied at least in part based on the value of the counter meeting the threshold.

23. The device of claim 22, wherein the controller is configured such that the device: The refresh pulse is avoided at least in part based on the determination that the value of the counter fails to meet the threshold.

24. The device of claim 19, wherein the controller is configured such that the device: A first write pulse having the second polarity is applied to the memory cell, wherein the memory cell includes a first logic state having a first distribution at least partially based on the application of the first write pulse, wherein the read pulse is applied at least partially based on the application of the first write pulse; and A second write pulse, including the first polarity, is applied to the memory cell, wherein the memory cell includes a second logic state having a second distribution that is at least partially based on the second distribution, different from the first distribution.

25. The device of claim 19, wherein the first polarity comprises a positive polarity or a negative polarity, and wherein the second polarity comprises the opposite polarity of the first polarity.

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