Memory array including strings of memory cells and method for forming memory array including strings of memory cells

Abstract

A method for forming a memory array including strings of memory cells includes forming a conductor layer including a conductor material on a substrate. Laterally spaced-apart memory block regions are formed and individually include a vertical stack including alternating first and second tiers directly above the conductor layer. Strings of channel material of memory cells extend through the first and second tiers. Horizontally elongated lines are formed in the conductor material between the laterally spaced-apart memory block regions. The horizontally elongated lines have a different composition than an upper portion of the conductor material laterally between the horizontally elongated lines. After the horizontally elongated lines are formed, conductive material of a lowermost of the first tiers is formed that directly electrically couples together channel material of individual of the strings of channel material and the conductor material of the conductor layer. Other embodiments are disclosed herein, including structures independent of methods.

Description

TECHNICAL FIELD

[0001] Embodiments disclosed herein relate to memory arrays and to methods for forming memory arrays. BACKGROUND

[0002] Memory is a type of integrated circuitry and is used in computer systems to store data. Memory can be fabricated in one or more arrays of individual memory cells. Memory cells can be written to or read from using digit lines (which can also be referred to as bit lines, data lines, or sense lines) and access lines (which can also be referred to as word lines). Sense lines can conductively interconnect memory cells along columns of the array, and access lines can conductively interconnect memory cells along rows of the array. Each memory cell can be uniquely addressed by a combination of a sense line and an access line.

[0003] Memory cells can be volatile, semi-volatile, or non-volatile. Non-volatile memory cells can store data for a long period of time without being powered. Non-volatile memory is typically designated as memory having a retention time of at least about 10 years. Volatile memory dissipates, and thus is refreshed / re-written to maintain data storage. Volatile memory can have a retention time of milliseconds or less. Regardless, memory cells are configured to hold or store memory in at least two different, selectable states. In binary systems, the states are considered a "0" or a "1." In other systems, at least some individual memory cells can be configured to store more than two bits or states of information.

[0004] A field effect transistor is a type of electronic component that can be used in memory cells. These transistors include a pair of conductive source / drain regions with a semiconductive channel region therebetween. A conductive gate is adjacent to the channel region and separated from the channel region by a thin gate insulator. Application of a suitable voltage to the gate allows current to flow through the channel region from one of the source / drain regions to the other. When the voltage is removed from the gate, current flow through the channel region is largely prevented. Field effect transistors can also include additional structures, such as a charge storage region that can be reversibly programmed, as part of a gate structure between the gate insulator and the conductive gate.

[0005] Flash memory is a type of memory and is used extensively in modern computers and devices. For example, modern personal computers can store the BIOS on a flash memory chip. As another example, it is increasingly common for computers and other devices to utilize flash memory in solid state drives in place of conventional hard disk drives. As yet another example, flash memory is popular in wireless electronic devices because it enables manufacturers to support new communication protocols as they become standardized, and provides the ability to remotely upgrade devices for enhanced features.

[0006] NAND can be the basic architecture of an integrated flash memory. NAND cell components include at least one select device coupled in series to a series combination of memory cells, where the series combination is commonly referred to as a NAND string. NAND architecture can be configured in a three-dimensional arrangement that includes vertically stacked memory cells that individually include a vertical transistor that can be programmed in a reversible manner. Control circuitry or other circuitry can be formed below the vertically stacked memory cells. Other volatile or non-volatile memory array architectures can also include vertically stacked memory cells that individually include a transistor.

[0007] Memory arrays can be arranged in memory pages, memory blocks, and partial blocks (e.g., sub-blocks), and memory planes, for example, as shown and described in any of U.S. Patent Application Publication Nos. 2015 / 0228651, 2016 / 0267984, and 2017 / 0140833. A memory block can at least partially define a longitudinal profile of individual word lines in individual word line layers of vertically stacked memory cells. Connections to these word lines can occur in so-called “staircase structures” at the ends or edges of an array of vertically stacked memory cells. The staircase structures include individual “steps” (alternatively referred to as “stages” or “terraces”) that define contact regions for individual word lines, which are contacted by vertically extending conductive vias to provide electrical access to the word lines. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 is a diagrammatic cross-sectional view of a portion of a substrate in processing according to embodiments of the present invention and is taken through line 1-1 in Figure 2 .

[0009] Figure 2 is a diagrammatic cross-sectional view taken through line 2-2 in Figure 1 .

[0010] Figures 3 to 25 is a diagrammatic sequential cross-sectional, exploded, enlarged, and / or partial view of a construction of Figure 1 and 2 in processing according to some embodiments of the present invention, or portions thereof. DETAILED DESCRIPTION

[0011] Embodiments of the invention encompass methods for forming memory arrays, such as arrays of NAND or other memory cells, which can have at least some peripheral under-array circuitry (e.g., under-array CMOS). Embodiments of the invention encompass so-called "gate-last" or "replacement gate" processes, so-called "gate-first" processes, and other processes that are independent of the timing of the formation of the transistor gates, whether existing or future-developed. Embodiments of the invention also encompass memory arrays (e.g., NAND architectures) that are independent of the fabrication method. Reference is made to Figures 1 to 25 A first example method embodiment is described, which can be considered a "gate-last" or "replacement gate" process, and proceeds from Figure 1 and 2 .

[0012] Figure 1 and 2 A construction 10 is shown, having an array or array region 12 of vertically- extending strings in which transistors and / or memory cells will be formed. The construction 10 includes a base substrate 11 of any one or more of an electrically-conductive / conductor / conducting, semi-electrically-conductive / semiconductor / semi-conducting, or insulative / insulator / insulating (i.e., electrically, herein) material. Various materials have been formed vertically above the base substrate 11. The materials can be to the side, vertically-inward, or vertically-outward of the depicted materials. For example, other partially or fully fabricated components of the integrated circuitry can be disposed somewhere above, around, or within the base substrate 11. Control circuitry and / or other peripheral circuitry for operating components within the array of vertically-extending strings of memory cells (e.g., array 12) can also be fabricated, and can or can not be fully or partially within the array or sub-array. Further, multiple sub-arrays can also be fabricated and operated independently, sequentially, or otherwise with respect to one another. In this document, a "sub-array" can also be considered an array. Figures 1 to 5 A conductor layer 16, including a conductor material 17, has been formed above the substrate 11. In one embodiment, the conductor material 17 includes an electrically-conductive doped semi-conductive material 13 (e.g., n-type conductively-doped polysilicon) atop (directly above, and for example directly against) a metallic material 15 (e.g., WSi x ). The conductor layer 16 can include portions of control circuitry (e.g., peripheral under-array circuitry and / or common source lines or plates) for controlling read and write access to the transistors and / or memory cells to be formed within the array 12.

[0013] A conductor layer 16, including a conductor material 17, has been formed above the substrate 11. In one embodiment, the conductor material 17 includes an electrically-conductive doped semi-conductive material 13 (e.g., n-type conductively-doped polysilicon) atop (directly above, and for example directly against) a metallic material 15 (e.g., WSi x ). The conductor layer 16 can include portions of control circuitry (e.g., peripheral under-array circuitry and / or common source lines or plates) for controlling read and write access to the transistors and / or memory cells to be formed within the array 12.

[0014] Reference is made to Figure 3 and 4 , and in one embodiment, a patterned masking material 66, having mask openings 67, has been formed atop the conductor layer 16.

[0015] refer to Figures 5 to 7 Construction 10 was subsequently subjected to ion implantation (by...) Figure 2 (As indicated by the downward guide arrow 68) to form horizontal extensions 72 in the conductor material 17 between objects (not yet shown) that will include laterally spaced memory block areas above it. The horizontal extensions 72 have a different composition from the upper portion (at least the upper portion) of the conductor material 17 laterally located between the horizontal extensions 72. In one embodiment, and as shown, the horizontal extensions 72 are not as thick as the conductor layer 16 in the vertical direction. In one embodiment, the horizontal extensions 72 have a greater content of one or more of C, N, B, As, Sb, Bi, Li, Al, In, or metallic materials than is present (if present) in the conductor material 17 laterally located between the horizontal extensions 72. In one embodiment, the horizontal extensions 72 are non-conductive (i.e., they are insulating or semi-conductive), and in another embodiment they are conductive.

[0016] In one embodiment, the uppermost portion 77 (at least the uppermost portion) of the horizontal extension 72 comprises a conductive-doped semiconducting material (e.g., conductive-doped polysilicon) having a conductive dopant having one of a primary n-type or p-type conductivity-generating dopant (e.g., 31). In this context, a primary n-type or primary p-type dopant makes the otherwise semiconducting material conductive due to the concentration of such primary dopant type. The uppermost portion of the horizontal extension 72 comprises a secondary dopant (e.g., 33) having a composition different from the primary dopant. In one embodiment, one is a primary n-type conductivity-generating dopant, and in another embodiment, one is a primary p-type conductivity-generating dopant. In one embodiment, the different primary and secondary dopants are the same n-type or p-type, and in another embodiment, they are different n-type or p-type. In one embodiment, the secondary dopant is one or more of C, N, B, As, or a metallic material. In one embodiment, the secondary dopant is one or more of Sb, Bi, Li, Al, or In. In one embodiment, the concentration of the minor dopant in the uppermost portion of the horizontal extension is at least 1 × 10⁻⁶. 14 atoms / cm 3 In one embodiment, this includes multiple minor dopants of different compositions.

[0017] The above processing is just one example of forming horizontally elongated lines 72 and having one or more of the above example properties. Any alternative existing or future developed ways and properties can be used or produced. For example, and by way of example only, where masking material 66 having openings 67 can be used as an etch mask while timed etching is performed into conductor material 17 to form trenches (not shown) therein. Such trenches can be filled with material having a different composition than material 13, and then such material is planarized at least back to the top surface of material 13 to form lines 72.

[0018] With reference to Figures 8 to 11 A stack 18 of vertically alternating insulating layers 20* and conductive layers 22* has been formed over conductor layer 16 (* as a suffix for including all such components that can or can not have other suffixes designated with the same numerical value). Example thicknesses of each of layers 20* and 22* are 22 nanometers to 60 nanometers. Only a small number of layers 20* and 22* are shown, but stack 18 more likely includes tens, hundreds, or more of layers 20* and 22*. Other circuitry, which can or can not be part of peripheral and / or control circuitry, can be located between conductor layer 16 and stack 18. For example, multiple vertically alternating layers of conductive and insulating materials of such circuitry can be below the lowermost of conductive layers 22* and / or above the uppermost of conductive layers 22*. For example, one or more select gate layers (not shown) can be between conductor layer 16 and the lowermost conductive layer 22*, and one or more select gate layers can be above the uppermost of conductive layers 22*. Alternatively or additionally, at least one of the depicted uppermost and lowermost conductive layers 22* can be a select gate layer. Regardless, conductive layers 22* (alternatively referred to as first layers) can not include a conductive material, and insulating layers 20* (alternatively referred to as second layers) can not include an insulating material or be insulating in connection with the “gate-last” or “replacement gate” example method embodiment processing described herein initially. Example conductive layers 22* include a first material 26 (e.g., silicon nitride) that can be fully or partially sacrificial. Example insulating layers 20* include a second material 24 (e.g., silicon dioxide) that has a different composition than first material 26 and can be fully or partially sacrificial. In an embodiment, the lowermost first layer 22z includes a sacrificial material having a different composition than the uppermost portion of horizontally elongated lines 72 in conductor material 17.

[0019] In some embodiments, the lowermost first layer 22z is thicker than the first layer 22* above it, and in one such embodiment is at least 1.5 times as thick as the first layer 22* above it. In one embodiment and as shown, the lowermost first layer 22z is not directly against the conductor material 17 of the conductor layer 16, e.g., with the lowermost second layer 20z vertically between the conductor material 17 of the conductor layer 16 and the lowermost first layer 22z. Alternatively, the lowermost first layer can be directly against the conductor material of a conductor layer (not shown). In one embodiment, the lowermost second layer 20z is directly against the top 19 of the conductor material 17 of the conductor layer 16. In one embodiment, the lowermost second layer 20z is thinner than the second layer 20* above it. In one embodiment, the second layer 20x immediately above the lowermost first layer 22z (e.g., the next highest second layer 20x) is thicker than the second layer 20* above it.

[0020] The second layer material of the second layer 20x immediately above the lowermost first layer 22z (i.e., with no other second layer vertically between the lowermost first layer 22z and the second layer 20x immediately above it) includes the upper first insulative material 21 and a lower second material 23 below the upper first insulative material 21, where the lower second material 23 has a different composition than the upper first insulative material 21. The upper insulative material 21 can have the same composition as the material 24. In some embodiments, the second layer material of the second layer 20x immediately above the lowermost first layer 22z can be considered to include the upper insulative material 21, a lower material 27, and an intermediate material 23 vertically between the upper insulative material 21 and the lower material 27, where the intermediate material 23 has a different composition than the lower material 27 and a different composition than the upper insulative material 21 (in some embodiments, the lower material 27 is optional). The upper insulative material 21 and the lower material 27 can have the same thickness as each other or different thicknesses. The lower second material 23 can be thinner than each of the upper first insulative material 21 and the lower material 27 (as shown), or can be thicker than each of the upper first insulative material 21 and the lower material 27 (not shown). Regardless, in some embodiments the upper insulative material 21 and the lower material 27 have the same composition relative to each other (e.g., and have the same composition as the material 24), and in other embodiments have different compositions relative to each other. In some embodiments, the lower second material 23 / intermediate material 23 includes at least one of: conductively-doped polysilicon, polysilicon that is not conductively-doped, carbon-doped polysilicon, silicon nitride, undoped silicon nitride, carbon-doped silicon nitride, and a metallic material.

[0021] A trench opening 25 has been formed (e.g., by etching) through the insulative layers 20* and the conductive layers 22* to the conductor layer 16. The trench opening 25 can taper radially inwardly as it moves deeper in the stack 18 (not shown). In some embodiments, the trench opening 25 can enter the conductor material 17 of the conductor layer 16 as shown, or can stop at a top thereof (not shown). Alternatively, as an example, the trench opening 25 can stop on or within the topmost insulative layer 20. The reason for extending the trench opening 25 at least into the conductor material 17 of the conductor layer 16 is to provide an anchoring effect to the material within the trench opening 25. An etch stop material (not shown) can be within or on top of the conductor material 17 of the conductor layer 16 to facilitate stopping the etching of the trench opening 25 relative to the conductor layer 16 when desired. Such an etch stop material can be sacrificial or non-sacrificial.

[0022] Horizontally elongated trenches 40 have been formed (e.g., by anisotropic etching) into the stack 18 to form laterally spaced apart memory block regions 58. The horizontally elongated trenches 40 are individually located directly above individual horizontally elongated lines 72. In one embodiment and as shown, the horizontally elongated lines 72 extend laterally into the area of the memory blocks 58 above them. The horizontally elongated lines 72 can be formed before or after the vertical stack 18 is formed. By way of example and for brevity only, the trench openings 25 are shown arranged in groups or columns of alternating rows of four and five trench openings 25 per row, and are arrayed in laterally spaced apart memory block regions 58 that will comprise laterally spaced apart memory blocks 58 in the finished circuitry construction. In this document, a "block" generally includes a "sub-block." The trenches 40 will generally be wider than the trench openings 25 (e.g., 10 to 20 times wider, but such greater degrees of width are not shown for brevity). The memory block regions 58 and resulting memory blocks 58 (not yet shown) can be considered to be longitudinally elongated and oriented, for example, along the direction 55. Any alternative existing or future developed arrangements and constructions can be used. The trenches 40 can have respective bottoms directly against the first material 26 of the lowermost first layer 22z (on top or within).

[0023] The trenches 40 have been lined with a thin lining material 35 (e.g., doped or undoped polysilicon or a metallic material) that can be partially or entirely sacrificial and desirably of a composition other than that of the materials 24 and 26. This can be conformally deposited and thereafter removed substantially from above the horizontal surfaces, such as by a maskless anisotropic spacer-like etch thereof or by a short wet etch. This at least in part drives some aspects of the present disclosure in overcoming issues associated with removing the lining material 35 from the bottoms of the trenches 40. In particular, this removal of the lining material 35 can be performed using an etch chemistry that can undesirably etch through the materials 26 and 24 of the layers 22z and 20z, respectively, exposing the conductor material 17 thereunder. Such an etch chemistry can then also undesirably etch the conductor material 17, which can ultimately result in damage to the circuitry being fabricated. Having the horizontally elongated lines 72 of a different and etch-resistant composition than the material 13 laterally adjacent thereto can reduce or eliminate such undesired etching of such material 13 in the event that it is exposed in etching the material 35.

[0024] Transistor channel materials can be formed vertically along the insulative and conductive layers in the individual channel openings, thus including individual strings of channel material directly electrically coupled with conductive material in the conductor layers. Individual memory cells of an example memory array being formed can include a gate region (e.g., a control gate region) and a memory structure laterally between the gate region and the channel material. In one such embodiment, the memory structure is formed to include a charge blocking region, a storage material (e.g., a charge storage material), and an insulative charge transport material. The storage material (e.g., a floating gate material such as doped or undoped silicon, or a charge trapping material such as silicon nitride, metal dots, etc.) of the individual memory cells is vertically along the individual charge blocking regions. The insulative charge transport material (e.g., a bandgap engineered structure having a nitrogen-containing material such as silicon nitride sandwiched between two insulator oxides such as silicon dioxide) is laterally between the channel material and the storage material.

[0025] Figures 8 to 11 One embodiment is shown in which the charge blocking material 30, the storage material 32, and the charge transport material 34 have been formed vertically along the insulative and conductive layers 20* and 22* in the individual channel openings 25. The transistor materials 30, 32, and 34 (e.g., memory cell materials) can be formed by, for example, depositing respective thin layers thereof over the stack 18 and within the individual openings 25 and then planarizing such transistor materials back at least to the top surface of the stack 18.

[0026] The channel material 36 has also been formed vertically in the channel openings 25 along the insulating layers 20* and the conductive layers 22*, thus including individual operative channel material strings 53 in the channel openings 25. The channel material 36 can be considered to have its lowermost surface 71. In one embodiment, the channel material strings 53 along which have memory cell material (e.g., 30, 32, and 34), and in which the second layer material (e.g., 24) is horizontally located between immediately adjacent channel material strings 53. Due to the scale, the materials 30, 32, 34, and 36 are collectively shown as and designated only as material 37 in Figure 1 and 2 material 37. Example channel material 36 includes suitably doped crystalline semiconductor material, such as one or more of silicon, germanium, and so-called III / V semiconductor materials (e.g., GaAs, InP, GaP, and GaN). Example thicknesses for each of the materials 30, 32, 34, and 36 are 25 Angstroms to 100 Angstroms. Stamped etching can be performed to remove the materials 30, 32, and 34 from the base of the channel openings 25 (not shown) to expose the conductor layer 16, so that the channel material 36 is directly against the conductor material 17 of the conductor layer 16. Such stamped etching can occur separately with respect to each of the materials 30, 32, and 34 (as shown), or can occur only with respect to some (not shown). Alternatively, and by way of example only, no stamped etching can be performed, and the channel material 36 can be directly electrically coupled to the conductor material 17 of the conductor layer 16 only by separate conductive interconnects (not yet shown). The channel openings 25 are shown to include a radially central solid dielectric material 38 (e.g., spin-on dielectric, silicon dioxide, and / or silicon nitride). Alternatively, and by way of example only, the radially central portion within the channel openings 25 can include void space (not shown) and / or be free of solid material (not shown).

[0027] Referring to Figure 12 and 13 , the first layer material 26 (e.g., using liquid or vapor H3PO4 as the primary etchant, where the material 26 is silicon nitride and the other material exposed includes one or more oxides or polysilicon) in the lowermost first layer 22z (not shown) has been selectively isotropically etched with respect to the second layer material 24, the liner material 35, and the lower material 27. If the material 24 of the lowermost second layer 20z was previously etched through to the conductor layer 16 (not shown), as identified in the issues set forth above, the horizontally elongated lines 72 can eliminate or at least reduce etching of the material of the conductor layer 16.

[0028] Figure 14 and 15A post-exhibit processing is shown in which material 30 (e.g., silicon dioxide), material 32 (e.g., silicon nitride), and material 34 (e.g., silicon dioxide or a combination of silicon dioxide and silicon nitride) have been etched to expose the sidewall 41 of the channel material 36 of the string of channel materials 53. Regardless, and in one embodiment, the lower material 27 is present, as shown in Figure 12 and 13 The lower material 27 (not shown in Figure 14 and 15 ) in the second layer 20x immediately above the lowermost first layer 22z has been selectively etched or exposed the lower surface 31 of the intermediate material 23. As an example, consider an embodiment in which material 23 is polysilicon, materials 21, 24, and 27 are silicon dioxide, and memory cell materials 30, 32, and 34 are one or more of layers of silicon dioxide and silicon nitride, respectively. In such an example, the depicted construction can be produced by using modified or different chemicals to selectively etch silicon dioxide and silicon nitride sequentially with respect to the other. As an example, a 100: 1 (by volume) solution of water to HF will selectively etch silicon dioxide with respect to silicon nitride, while a 1000: 1 (by volume) solution of water to HF will selectively etch silicon nitride with respect to silicon dioxide. Thus, and in such an example, such etching chemicals can be used in an alternating fashion in which the example construction shown by Figure 14 and 15 is desired to be achieved. Those skilled in the art are able to select other chemicals for etching other different materials in which the construction shown by Figure 14 and 15 is desired to be achieved. The lower material 27 (not shown) is shown as having been removed in the processing of Figure 14 and 15 but this can not be removed until later in some embodiments. The material 24 of the lowermost second layer 20z, as shown in Figure 12 and 13 has also been removed (not shown) in Figure 14 and 15 .

[0029] Reference is made to Figure 16 and 17, conductive material 42 has been formed in the lowermost first tier 22z to directly electrically couple together the channel material 36 of individual ones of the channel material strings 53 and the conductor material 17 of the conductor layer 16. Example conductive materials include conductively doped semiconductor materials (e.g., conductively doped polysilicon, e.g., including dopants 31 in sufficient amount / concentration to make the polysilicon conductive) and metallic materials. In one embodiment, the conductive material 42 in the lowermost first tier 22z is directly against sidewalls 41 of the channel material 36 of the channel material strings 53, and in one embodiment, the conductive material 42 in the lowermost first tier 22z is directly against an uppermost surface (e.g., 19) of an uppermost portion of the conductor material 17 of the conductor layer 16.

[0030] Referring to Figure 18 and 19 , the conductive material 42 has been removed from the trenches 40, e.g., by anisotropic etching or by timed isotropic etching that is selective with respect to the materials 35 and 13 and the horizontally elongated lines 72. Those skilled in the art are able to select any suitable etching chemistry.

[0031] Referring to Figures 20 to 25 , the lining material 35 (not shown) has been removed. Thereafter, the material 26 (not shown) of the conductive layer 22 has been removed, e.g., isotropically etched away, desirably through the trenches 40, selectively with respect to other exposed materials (e.g., using liquid or vapor H3PO4 as the primary etchant, where the material 26 is silicon nitride and the other materials include one or more oxides or polysilicon). In example embodiments, the material 26 (not shown) in the conductive layer 22 is sacrificial and has been replaced by the conductive material 48, and thereafter has been removed from the trenches 40, thus forming individual conductive lines 29 (e.g., word lines) and individual vertically extending strings 49 of transistors and / or memory cells 56.

[0032] A thin insulating liner (e.g., Al2O3 and not shown) can be formed prior to forming the conductive material 48. The approximate locations of the transistors and / or memory cells 56 are indicated in Figure 25 with brackets, while some are indicated in Figure 20 , 21 , 23 and 24 with dashed outlines, where the transistors and / or memory cells 56 are substantially annular or ring-shaped in the depicted example. Alternatively, the transistors and / or memory cells 56 can not be completely annular with respect to the individual channel openings 25, such that each channel opening 25 can have two or more vertically extending strings 49 (e.g., multiple transistors and / or memory cells in individual conductive layers surrounding individual channel openings, where there can be multiple word lines per channel opening in individual conductive layers, and not shown). The conductive material 48 can be considered to have ends 50 corresponding to control gate regions 52 of individual transistors and / or memory cells 56.Figure 25 ). In the depicted embodiment, the control gate region 52 includes individual portions of the individual conductive lines 29. The materials 30, 32, and 34 can be considered a memory structure 65 laterally between the control gate region 52 and the channel material 36. In one embodiment and as shown with respect to the example "gate-last" process, the conductive material 48 of the conductive layer 22 is formed after the formation of the channel opening 25 and / or the trench 40. Alternatively, for example with respect to a "gate-first" process, the conductive material of the conductive layer can be formed prior to the formation of the channel opening 25 and / or the trench 40 (not shown).

[0033] A charge-blocking region (e.g., charge-blocking material 30) is between the storage material 32 and the individual control gate region 52. The charge blocker can have the following function in a memory cell: in a program mode, the charge blocker can prevent charge carriers from flowing out of the storage material (e.g., floating gate material, charge-trapping material, etc.) to the control gate, and in an erase mode, the charge blocker can prevent charge carriers from flowing from the control gate into the storage material. Thus, the charge blocker can be used to block charge migration between the control gate region and the storage material of an individual memory cell. The example charge-blocking region as shown includes an insulator material 30. As a further example, the charge-blocking region can include a laterally (e.g., radially) outer portion of the storage material (e.g., material 32), where such storage material is insulative (e.g., without any different composition material between the insulative storage material 32 and the conductive material 48). Regardless, as an additional example, the intersection of the storage material and the conductive material of the control gate can be sufficient to act as a charge-blocking region without any separate composition insulator material 30. Further, the intersection of the conductive material 48 and material 30 (if present) in conjunction with the insulator material 30 can together act as a charge-blocking region, and alternatively or additionally can act as a laterally outer region of insulative storage material (e.g., silicon nitride material 32). The example material 30 is one or more of hafnium silicon oxide and silicon dioxide.

[0034] In one embodiment and as shown, the lowermost surface 71 of the channel material 36 of the channel material string 53 does not directly abut any of the conductor material 17 of the conductor layer 16.

[0035] Intervening material 57 has been formed in trenches 40 and thereby laterally between and longitudinally along laterally-adjacent memory blocks 58. Intervening material 57 can provide lateral electrical isolation between laterally-adjacent memory blocks. This can include one or more of insulative, semiconductive, and conductive materials, and in any event can facilitate conductive layer 22* from shorting against one another in a finished circuitry construction. Example insulative materials are one or more of SiO2, Si3N4, Al2O3, and undoped polysilicon. Intervening material 57 can include through-array vias (not shown). Some material in trenches 40 formed prior to the material designated as intervening material 57 can be left in place and thereby included as part of intervening material 57.

[0036] Any other property or aspect as shown and / or described herein with respect to other embodiments can be used in the embodiments shown and described with reference to the above embodiments.

[0037] In one embodiment, a method for forming a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes forming a conductor layer (e.g., 16) including a conductor material (e.g., 17) on a substrate (e.g., 11). Laterally-spaced-apart memory block regions (e.g., 58) are formed that individually include a vertical stack (e.g., 18) including alternating first layers (e.g., 22) and second layers (e.g., 20) directly above the conductor layer. Strings (e.g., 53) of channel material of the memory cells extend through the first and second layers. Horizontally-elongated lines (e.g., 72) are formed in the conductor material between the laterally-spaced-apart memory block regions. The horizontally-elongated lines have a different composition than an upper portion (at least an upper portion; e.g., 77) of the conductor material laterally between the horizontally-elongated lines. After forming the horizontally-elongated lines, conductive material (e.g., 42) in a lowermost of the first layers (e.g., 22z) is formed that directly electrically couples together channel material of individual ones of the strings of channel material with the conductor material of the conductor layer. Any other property or aspect as shown and / or described herein with respect to other embodiments can be used.

[0038] Alternative embodiment constructions can be implemented by or otherwise result from the method embodiments described above. In any event, embodiments of the invention encompass memory arrays independent of the method of manufacture. However, such memory arrays can have any of the properties as described herein in the method embodiments. Likewise, the method embodiments described above can incorporate, form, and / or have any of the properties described with respect to the device embodiments.

[0039] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) including a conductor material (e.g., 17). The memory array includes laterally spaced-apart memory blocks (e.g., 58) individually including a vertical stack (e.g., 18) including alternating insulative layers (e.g., 20) and conductive layers (e.g., 22). Strings (e.g., 53) of channel material of the memory cells (e.g., 56) extend through the insulative layers and the conductive layers. Conduction material (e.g., 42) of a lowermost of the conductive layers (e.g., 22z) directly electrically couples together channel material (e.g., 36) of individual ones of the strings of channel material and the conductor material of the conductor layer. An intervening material (e.g., 57) is laterally between laterally-adjacent memory blocks and longitudinally along the memory blocks. The intervening material includes an insulative material. A horizontally-elongated line (e.g., 72) is in the conductor material between laterally-spaced-apart memory blocks. The horizontally-elongated line has a different composition than the conductor material laterally between the horizontally-elongated line. Any other property or aspect as shown and / or described herein with respect to other embodiments can be used.

[0040] In one embodiment, a memory array (e.g., 12) including strings (e.g., 49) of memory cells (e.g., 56) includes a conductor layer (e.g., 16) including n-type conductively-doped polysilicon (e.g., 13) having primary n-type conductivity-creating dopants (e.g., 31) therein. The memory array includes laterally spaced-apart memory blocks (e.g., 58) individually including a vertical stack (e.g., 18) including alternating insulative layers (e.g., 20) and conductive layers (e.g., 22) directly above the conductor layer. Strings (e.g., 53) of channel material of the memory cells (e.g., 56) extend through the insulative layers and the conductive layers. A lowermost of the conductive layers (e.g., 22z) includes the n-type conductively-doped polysilicon directly against the n-type conductively-doped polysilicon of the conductor layer and directly against sidewalls (e.g., 41) of channel material (e.g., 36) of the strings of channel material in the lowermost conductive layer. An intervening material (e.g., 57) is laterally between laterally-adjacent memory blocks and longitudinally along the memory blocks. The intervening material includes an insulative material. A horizontally-elongated line (e.g., 72) is in the conductor material between laterally-spaced-apart memory blocks. The horizontally-elongated line includes the n-type conductively-doped polysilicon including secondary dopants (e.g., 33) having a different composition than the primary dopants. Any other property or aspect as shown and / or described herein with respect to other embodiments can be used.

[0041] The above processing or construction can be considered with respect to an array of components, which are formed as a single stack or single deck of such components, or within a single stack or single deck, which stack or deck is over or part of an underlying base substrate (but a single stack / deck can have multiple layers). Control circuitry and / or other peripheral circuitry for operating or accessing such components within the array can also be formed as part of the finished construction at any location, and in some embodiments can be located under the array (e.g., array-under-CMOS). Regardless, one or more additional such stacks / decks can be provided or fabricated over and / or under the stack / deck shown in the figures or described above. Moreover, the arrays of components can be the same or different with respect to each other in different stacks / decks, and different stacks / decks can have the same or different thicknesses with respect to each other. Intervening structures can be provided between vertically-adjacent stacks / decks (e.g., additional circuitry and / or dielectric layers). Also, different stacks / decks can be electrically coupled with respect to each other. Multiple stacks / decks can be fabricated individually and sequentially (e.g., one on top of the other), or two or more stacks / decks can be fabricated substantially simultaneously.

[0042] The assemblies and structures discussed above can be used in integrated circuits / circuitry and can be incorporated into electronic systems. Such electronic systems can be used in, for example, memory modules, device drivers, power modules, communication modems, processor modules, and application-specific modules, and can include multilayer, multichip modules. The electronic systems can be any of a broad range of systems, such as, for example, cameras, wireless devices, displays, chip sets, set top boxes, games, lighting, vehicles, clocks, televisions, cell phones, personal computers, automobiles, industrial control systems, aircraft, etc.

[0043] In this document, unless otherwise indicated, "vertical," "higher," "upper," "lower," "top," "topmost," "bottom," "above," "below," "under," "down," and "up" refer generally to vertical directions. "Horizontal" refers to a general direction along a major substrate surface (i.e., within 10 degrees), and can be with respect to which a substrate is handled during fabrication, and vertical is a direction generally orthogonal to horizontal. Reference to "exactly horizontal" refers to a direction along a major substrate surface (i.e., no degrees from the surface), and can be with respect to which a substrate is handled during fabrication. Also, as used herein, "vertical" and "horizontal" are generally perpendicular directions with respect to each other, and are independent of the orientation of a substrate in three-dimensional space. Additionally, "vertically-extending" and "vertically-extend" refer to a direction that is at least 45° from exactly horizontal. Furthermore, "vertically-extend," "vertically-extending," "horizontally-extend," "horizontally-extending," and the like with respect to a field effect transistor refer to the orientation of the channel length of the transistor, along which current flows between source / drain regions in operation. For bipolar junction transistors, "vertically-extend," "vertically-extending," "horizontally-extend," "horizontally-extending," and the like refer to the orientation of the base length, along which current flows between the emitter and collector in operation. In some embodiments, any component, feature, and / or region that extends vertically extends vertically or within 10° of vertical.

[0044] Furthermore, "directly above," "directly below," and "directly under" require at least some lateral overlap (i.e., horizontally) of the two stated regions / materials / components with respect to each other. Also, use of "above" without the "directly" preceding it only requires that some portion of the stated region / material / component above the other stated region / material / component be vertically outside the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components). Similarly, use of "below" and "under" without the "directly" preceding it only requires that some portion of the stated region / material / component below / under the other stated region / material / component be vertically inside the other stated region / material / component (i.e., independent of whether there is any lateral overlap of the two stated regions / materials / components).

[0045] Any of the materials, regions, and structures described herein can be homogeneous or inhomogeneous, and can be continuous or discontinuous over any material on which it is overlying, regardless of how. When one or more example compositions are provided for any material, the material can comprise, consist essentially of, or consist of the one or more compositions. Additionally, each material can be formed using any suitable existing or future-developed technique, unless otherwise specified, with atomic layer deposition, chemical vapor deposition, physical vapor deposition, epitaxial growth, diffusion doping, and ion implantation being examples.

[0046] In addition, "thickness" (without a directional adjective preceding it) used alone is defined as the average straight-line distance normal through a given material or region from the closest surface of an immediately adjacent material or region of different composition. In addition, various materials or regions described herein can have a substantially constant thickness or a variable thickness. If having a variable thickness, the thickness refers to the average thickness unless otherwise indicated, and such material or region will have some minimum thickness and some maximum thickness as a result of the variable thickness. As used herein, "different composition" requires only that those portions of two stated materials or regions that can be directly against each other be chemically and / or physically different if such materials or regions are not homogeneous. If the two stated materials or regions are not directly against each other, "different composition" requires only that those portions of two stated materials or regions that are closest to each other be chemically and / or physically different if such materials or regions are not homogeneous. In this document, stated materials, regions, or structures are "directly against" another material, region, or structure when there is at least some physical contact of the stated materials, regions, or structures relative to each other. In contrast, "over," "on," "adjacent," "along," and "against" without the "directly" encompass both "directly against" and configurations in which intervening materials, regions, or structures are such that the stated materials, regions, or structures are not in physical contact relative to each other.

[0047] In this document, zone-material-assemblies are "electrically coupled" relative to each other if, in normal operation, current is able to flow continuously from one zone-material-assembly to another and the flow is primarily through movement of subatomic positive and / or negative charges when sufficient to create the subatomic positive and / or negative charges. Another electronic assembly can be between and electrically coupled to the zone-material-assemblies. Conversely, when zone-material-assemblies are referred to as being "directly electrically coupled," there is no intervening electronic assembly (e.g., no diode, transistor, resistor, transducer, switch, fuse, etc.) between the directly electrically coupled zone-material-assemblies.

[0048] Any use of "row" and "column" in this document is to facilitate distinguishing one series or orientation of features from another series or orientation of features, and assemblies have been or can be formed along the "rows" and "columns." "Row" and "column" are used synonymously with respect to any series of zones, assemblies, and / or features, regardless of function. Regardless, rows can be straight and / or curved and / or parallel and / or non-parallel relative to each other, as can columns. In addition, rows and columns can intersect relative to each other at 90° or at one or more other angles (i.e., other than a right angle).

[0049] The composition of any of the conductive / conductor / conducting materials herein can be a metallic material and / or an electrically conductively-doped semiconductive / semiconductor / semiconducting material. A "metallic material" is any one or combination of an elemental metal, a mixture or alloy of two or more elemental metals, and any one or more electrically conductive metal compounds.

[0050] In this document, any use of "or" covers any one and all of the possible combinations. In other words, if a disjunctive phrase is used herein such as "A or B," it is to be understood that the phrase means "A or B or both." In other words, the use of "or" in this document covers any one and all of the possible combinations.

[0051] Unless otherwise indicated, the use herein of "or" encompasses any one and both of the stated alternatives.

[0052] Conclusion

[0053] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductor layer including a conductor material on a substrate. Laterally spaced apart memory block regions are formed and individually include a vertical stack including alternating first and second tiers directly above the conductor layer. Strings of channel material of memory cells extend through the first and second tiers. Horizontally elongated lines are formed in the conductor material between the laterally spaced apart memory block regions. The horizontally elongated lines have a different composition than an upper portion of the conductor material laterally between the horizontally elongated lines. After the horizontally elongated lines are formed, conductive material of a lowermost of the first tiers is formed that directly electrically couples together channel material of individual ones of the strings of channel material with the conductor material of the conductor layer.

[0054] In some embodiments, a method for forming a memory array including strings of memory cells includes forming a conductor layer including a conductor material on a substrate. Horizontally elongated lines are formed in the conductor material between objects that will include laterally spaced apart memory block regions thereover. The horizontally elongated lines have a different composition than an upper portion of the conductor material that is laterally between the horizontally elongated lines. After the horizontally elongated lines are formed, a stack including vertically alternating first and second tiers is formed over the conductor layer. A lowermost one of the first tiers includes a sacrificial material having a different composition than an uppermost portion of the horizontally elongated lines in the conductor material. The stack includes the laterally spaced apart memory block regions with horizontally elongated trenches therebetween that are individually located directly over an individual one of the horizontally elongated lines in the conductor material in the conductor layer. Strings of channel material extend through the first and second tiers. The material of the first tiers has a different composition than the material of the second tiers. The sacrificial material is etched isotropically from the lowermost first tier. After the isotropic etching, conductive material is formed in the lowermost first tier that directly electrically couples together channel material of an individual one of the strings of channel material and the conductor material of the conductor layer.

[0055] In some embodiments, a memory array including strings of memory cells includes a conductor layer with a conductor material. Laterally spaced apart memory blocks individually include a vertical stack of alternating insulative and conductive tiers directly over the conductor layer. Strings of channel material of memory cells extend through the insulative and conductive tiers. A conductive material of a lowermost one of the conductive tiers directly electrically couples together channel material of an individual one of the strings of channel material and the conductor material of the conductor layer. An intervening material is laterally between and longitudinally along the memory blocks that are immediately laterally adjacent. The intervening material includes an insulative material. Horizontally elongated lines in the conductor material are between the laterally spaced apart memory blocks. The horizontally elongated lines have a different composition than the conductor material that is laterally between the horizontally elongated lines.

[0056] In some embodiments, a memory array including strings of memory cells includes a conductor layer including n-type conductively-doped polysilicon having primary n-type conductivity generating dopants therein. Laterally-spaced-apart memory blocks individually include a vertical stack including alternating insulative layers and conductive layers directly above the conductor layer. Strings of channel materials of memory cells extend through the insulative layers and the conductive layers. A lowermost one of the conductive layers includes n-type conductively-doped polysilicon directly against the n-type conductively-doped polysilicon of the conductor layer and directly against sidewalls of channel materials of the strings of channel materials in the lowermost conductive layer. Intervening material is laterally between the laterally-adjacent memory blocks and longitudinally along the memory blocks. The intervening material includes insulative material. A horizontally-elongated line of conductor material is between the laterally-spaced-apart memory blocks. The horizontally-elongated line of conductor material includes n-type conductively-doped polysilicon including secondary dopants having a different composition than the primary dopants.

Claims

1. A method for forming a memory array comprising strings of memory cells, comprising: A conductor layer comprising a conductor material is formed on a substrate; Forming laterally spaced memory block regions, which individually comprise vertically stacked alternating first and second layers directly above the conductor layer, with channel material strings of memory cells extending through the first and second layers; Horizontal extension lines are formed in the conductor material between the laterally spaced memory block regions, the horizontal extension lines having a different composition from the upper portion of the conductor material laterally located between the horizontal extension lines; and After the horizontal extension lines are formed, the conductive material of the lowest one in the first layer is formed, which directly electrically couples the channel material of the individual channel material strings to the conductor material of the conductor layer.

2. The method of claim 1, wherein the horizontal extension line is formed prior to forming the vertical stack.

3. The method of claim 1, wherein the horizontal extension line is formed after the vertical stack is formed.

4. The method of claim 1, wherein the horizontal extension line extends laterally into the region of the memory block area above it.

5. The method of claim 1, wherein the horizontal extension line is not as thick as the conductor layer in the vertical direction.

6. The method of claim 1, wherein the horizontal extension has a greater content of one or more of C, N, B, As, Sb, Bi, Li, Al, In or metallic materials than is present in the conductor material transversely located between the horizontal extensions.

7. The method of claim 1, wherein the horizontal extension wire is non-conductive.

8. The method of claim 1, wherein the horizontal extension wire is conductive.

9. The method of claim 1, wherein the horizontal elongation is formed by ion implantation into the conductor material via a mask opening in the masking material.

10. The method of claim 1, wherein the lowest surface of the channel material in the channel material string never directly abuts against any of the conductor materials of the conductor layer.

11. A method for forming a memory array comprising strings of memory cells, comprising: A conductor layer comprising a conductor material is formed on a substrate; A horizontal extension line is formed in the conductor material between objects comprising laterally spaced memory block areas above it, the horizontal extension line having a different composition from the upper portion of the conductor material laterally located between the horizontal extension lines; After the horizontal extension lines are formed, a stack comprising vertically alternating first and second layers is formed above the conductor layer. The lowest portion of the first layer includes a sacrificial material having a composition different from that of the uppermost portion of the horizontal extension lines in the conductor material. The stack includes laterally spaced memory block regions having horizontally extending trenches therebetween. The horizontally extending trenches are individually located directly above each of the horizontal extension lines in the conductor material of the conductor layer. A channel material string extends through the first and second layers. The material of the first layer has a composition different from that of the material of the second layer. The sacrificial material is etched isotropically from the lowest part of the first layer; as well as After the isotropic etching, a conductive material is formed in the lowest part of the first layer, which directly electrically couples the channel material of each individual in the channel material string to the conductor material of the conductor layer.

12. A memory array comprising a string of memory cells, comprising: A conductor layer, comprising a conductor material; Horizontally spaced memory blocks, each comprising a vertical stack of alternating insulating and conductive layers directly above the conductor layer, with a channel material string of memory cells extending through the insulating and conductive layers, the conductive material of the lowest of the conductive layers directly electrically coupling the channel material of each individual in the channel material string to the conductor material of the conductor layer; An interventional material, laterally located between laterally adjacent memory blocks and longitudinally along the memory blocks, the interventional material comprising an insulating material; and A horizontal extension line, which, in the conductor material between the laterally spaced memory blocks, has a different composition from the conductor material laterally located between the horizontal extension lines.

13. The memory array of claim 12, wherein the horizontal extension line extends laterally into the region of the memory block above it.

14. The memory array of claim 12, wherein the horizontal extension line is not as thick as the conductor layer in the vertical direction.

15. The memory array of claim 12, wherein the horizontal extensions have a greater content of one or more of C, N, B, As, Sb, Bi, Li, Al, In or metallic materials than is present in the conductor material laterally located between the horizontal extensions.

16. The memory array of claim 12, wherein the horizontal extension lines are non-conductive.

17. The memory array of claim 12, wherein the horizontal extension lines are conductive.

18. The memory array of claim 17, wherein the uppermost portion of the horizontal extension line comprises a semiconductive material having a conductive dopant having one of a primary n-type or p-type conductivity-generating dopant, and at least the uppermost portion of the horizontal extension line comprises a secondary dopant having a composition different from the primary n-type or p-type conductivity-generating dopant.

19. The memory array of claim 18, wherein one of them is the dopant that generates the primary n-type conductivity.

20. The memory array of claim 18, wherein one of them is the dopant that generates the primary p-type conductivity.

21. The memory array of claim 18, wherein the different primary and secondary dopants are the same n-type or p-type.

22. The memory array of claim 18, wherein the different primary and secondary dopants are different n-type or p-type.

23. The memory array of claim 18, wherein the secondary dopant is one or more of C, N, B, As or a metallic material.

24. The memory array of claim 18, wherein the minor dopant is one or more of Sb, Bi, Li, Al or In.

25. The memory array of claim 18, wherein the uppermost portion of the horizontal extension line comprises polysilicon.

26. The memory array of claim 18, wherein the concentration of the secondary dopant in the uppermost portion of the horizontal extension is at least 1 × 10⁻⁶. 14 atoms / cm 3 .

27. The memory array of claim 18, comprising a plurality of minor dopants of different compositions.

28. A memory array comprising a string of memory cells, comprising: A conductor layer comprising an n-type conductive doped polysilicon in which a dopant having predominant n-type conductivity is generated; The memory blocks are spaced apart laterally, each comprising a vertical stack of alternating insulating and conductive layers directly above the conductor layer. Channel material strings of the memory cells extend through the insulating and conductive layers. The lowest of the conductive layers comprises n-type conductive doped polysilicon, which directly abuts the n-type conductive doped polysilicon of the conductor layer and directly abuts the sidewall of the channel material string of the lowest of the conductive layers. An interventional material, laterally located between laterally adjacent memory blocks and longitudinally along the memory blocks, the interventional material comprising an insulating material; and A horizontal extension line in the conductor material between the laterally spaced memory blocks, the horizontal extension line comprising n-type conductive doped polysilicon, the n-type conductive doped polysilicon comprising a secondary dopant having a composition different from that of the primary dopant.

29. The memory array of claim 28, wherein the primary dopant is p and the secondary dopant is one or more of C, N, B, As, Sb, Bi, Li, Al, In or a metallic material.

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