Samples for measuring dopant elements in semiconductor devices and their preparation methods

Abstract

This invention provides a sample for measuring doped elements in semiconductor devices and a method for preparing the same, comprising: providing a semiconductor substrate with a word line structure, the word line structure including a metal layer; polishing the semiconductor substrate to expose the metal layer; etching away the metal layer to form word line grooves; filling the word line grooves with a silicate compound; depositing a Pt layer on the semiconductor substrate filled with the silicate compound; cutting the semiconductor substrate using a focused ion beam to form a sample strip; transferring the sample strip to a silicon substrate of a three-dimensional atomic probe and connecting it to the silicon substrate; cutting the sample strip near the silicon substrate, leaving a portion of the sample strip on the silicon substrate as the sample to be circumcised; and circumcising the sample to be circumcised to form a conical sample. The sample prepared by the method of this invention avoids the influence of metal elements during three-dimensional atomic probe measurements, enabling the formation of clearer three-dimensional images and improving measurement accuracy.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing technology, and in particular to a sample for measuring doping elements in semiconductor devices and a method for preparing the same. Background Technology

[0002] Three-dimensional atomic probe microanalysis (3D ATEM) is a measurement and analysis method with atomic-level spatial resolution. In 3D ATEM measurements, the sample must be conical, with the sample acting as the anode under a positive high voltage. The atoms at the sample tip are in a state of ionization. When a pulsed voltage or pulsed laser is applied to the sample tip, the surface atoms ionize and evaporate, thus precipitating the element. Time-of-flight mass spectrometry (TOF-MS) is used to determine the mass-to-charge ratio of the evaporated ions, thereby obtaining the ion's mass spectrum peak and identifying the elemental type. A position-sensitive probe records the two-dimensional coordinates of the flying ions on the sample tip surface. By observing the layer-by-layer accumulation of ions in the longitudinal direction, the longitudinal coordinates of the ions are determined, thus generating a three-dimensional spatial distribution image of different types of atoms in the sample.

[0003] Semiconductor substrates include doped regions, and in semiconductor substrates with word line structures, these word line structures are formed within the doped regions. To analyze the distribution of doped elements in the semiconductor substrate, samples of these doped regions for three-dimensional atom probe microanalysis (3D ATM) are prepared. The word line structures contain a metal layer, introducing metal elements into the sample. During 3D ATM measurements, at the same energy, the rate of silicon atom deposition in the doped regions is greater than the rate of metal element deposition, which affects the final 3D imaging and leads to inaccurate measurements.

[0004] The information disclosed in the background section is only for enhancing the understanding of the background of the present invention, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] A primary objective of this invention is to provide a method for preparing a sample for measuring doping elements in semiconductor devices. After measuring the sample using a three-dimensional atomic probe, a clear three-dimensional image can be formed, thereby improving the accuracy of the measurement.

[0006] Another object of the present invention is to provide a sample for measuring dopant elements in semiconductor devices. The distribution of dopant elements in the sample is measured using a three-dimensional atomic probe, which can form a clear three-dimensional image and improve the accuracy of the measurement.

[0007] According to one aspect of the present invention, a method for preparing a sample for measuring doped elements in a semiconductor device is provided, comprising: providing a semiconductor substrate having a word line structure, the word line structure including a metal layer; polishing the semiconductor substrate to expose the metal layer; etching away the metal layer to form word line grooves; filling the word line grooves with a silicate compound; depositing a Pt layer on the semiconductor substrate filled with the silicate compound; cutting the semiconductor substrate using a focused ion beam to form a sample strip; transferring the sample strip to a silicon substrate of a three-dimensional atom probe and connecting it to the silicon substrate; cutting the sample strip near the silicon substrate, leaving a portion of the sample strip on the silicon substrate as a sample to be circumcised; and circumcising the sample to be circumcised to form a conical sample.

[0008] According to an exemplary embodiment of the present invention, polishing the semiconductor substrate to expose the metal layer includes: defining a sample region on the semiconductor substrate, polishing the semiconductor substrate of the sample region to expose the metal layer.

[0009] According to an exemplary embodiment of the present invention, the process used for polishing the semiconductor substrate is chemical mechanical polishing.

[0010] According to an exemplary embodiment of the present invention, the etching solution used to etch the metal layer is at least one of concentrated nitric acid and hydrofluoric acid.

[0011] According to an exemplary embodiment of the present invention, the thickness of the Pt layer is 0.2 to 0.5 μm.

[0012] According to an exemplary embodiment of the present invention, the sample strip is a cantilever structure, and the sample strip has a first end and a second end, the first end being connected to the semiconductor substrate, and the second end being a free end.

[0013] According to an exemplary embodiment of the present invention, the step of transferring the sample strip to the silicon substrate of the three-dimensional atom probe and connecting it to the silicon substrate includes: moving a tungsten needle to the second end of the sample strip, depositing Pt or W between the tungsten needle and the second end to connect the tungsten needle to the second end; using the focused ion beam to cut the first end of the sample strip from the semiconductor substrate; and moving the tungsten needle to translate the sample strip to the silicon substrate of the three-dimensional atom probe.

[0014] According to an exemplary embodiment of the present invention, transferring the sample strip to and connecting it to the silicon substrate of the three-dimensional atomic probe further includes: depositing Pt or W between the silicon substrate and a first end of the sample strip on the side opposite to the Pt layer, thereby connecting the silicon substrate to the first end.

[0015] According to an exemplary embodiment of the present invention, the thickness of the Pt or W deposited between the tungsten needle and the second end is 0.3 to 0.6 μm, and the deposition area is 3 μm * 2 μm.

[0016] According to an exemplary embodiment of the present invention, the tip diameter of the tungsten needle is 2 to 6 μm.

[0017] According to an exemplary embodiment of the present invention, the tip diameter of the conical sample is 100 nm to 200 nm.

[0018] According to an exemplary embodiment of the present invention, the preparation method further includes: after forming the conical sample, removing the sample from the silicon substrate; transferring the sample strip back to the silicon substrate and connecting it to the silicon substrate; cutting the sample strip near the silicon substrate to form a second sample to be circumcised connected to the silicon substrate; circumcising the second sample to be circumcised to form a second conical sample; repeating the above method to form a plurality of conical samples.

[0019] According to an exemplary embodiment of the present invention, the sample strip forms three conical samples.

[0020] According to an exemplary embodiment of the present invention, a word line trench is provided in the active region of the semiconductor substrate, and the word line structure is disposed in the word line trench; wherein, the word line structure includes: a dielectric layer formed on the inner wall of the word line trench; a work function layer formed on the dielectric layer; and a word line metal layer formed inside the work function layer and filling the word line trench.

[0021] According to an exemplary embodiment of the present invention, the metal layer includes the work function layer and the word line metal layer.

[0022] According to an exemplary embodiment of the present invention, the material of the work function layer is TiN, the material of the word line metal layer is W, and the material of the dielectric layer is SiO2.

[0023] According to an exemplary embodiment of the present invention, the sample is prepared by the method described in any of the above embodiments.

[0024] As can be seen from the above technical solution, the present invention possesses at least one of the following advantages and positive effects:

[0025] By depositing a Pt layer on a semiconductor substrate, the target area for sample acquisition can be located and protected, preventing damage to the sample strip. Etching away the metal layer in the word line structure eliminates the presence of this metal layer in the sample strip. The resulting conical sample after circumferential cutting is free of metal elements. This avoids the influence of metal elements during three-dimensional atom probe microanalysis, resulting in a clearer three-dimensional image and improved measurement accuracy. Attached Figure Description

[0026] The above and other features and advantages of the present invention will become more apparent from a detailed description of exemplary embodiments thereof with reference to the accompanying drawings.

[0027] Figure 1 A flowchart illustrating a preparation method as shown in an exemplary embodiment of the present invention;

[0028] Figure 2 This is a schematic cross-sectional view of a semiconductor substrate shown in an exemplary embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram illustrating a semiconductor stripping process to expose a metal layer, as shown in an exemplary embodiment of the present invention.

[0030] Figure 4 This is a schematic diagram of a word line structure in which the metal layer has been etched away, as shown in an exemplary embodiment of the present invention.

[0031] Figure 5 This is a schematic diagram illustrating the filling of the character line groove with a silicate compound, as shown in an exemplary embodiment of the present invention.

[0032] Figure 6 This is a schematic diagram illustrating the deposition of a Pt layer on a semiconductor substrate filled with a silicate compound to form a sample strip, as shown in an exemplary embodiment of the present invention.

[0033] Figure 7 This is a schematic diagram illustrating the movement of a tungsten needle to the second end of a sample strip, as shown in an exemplary embodiment of the present invention.

[0034] Figure 8 This is a schematic diagram illustrating the connection between a tungsten needle and the second end of a sample strip, as shown in an exemplary embodiment of the present invention.

[0035] Figure 9 This is a schematic diagram illustrating an exemplary embodiment of the present invention, showing a sample strip formed by cutting off the first end of the sample strip from the semiconductor substrate and moving it to the silicon substrate;

[0036] Figure 10 This is a schematic diagram illustrating an exemplary embodiment of the present invention, showing how a silicon substrate and a sample strip are simultaneously rotated 180° vertically and then connected.

[0037] Figure 11 This is a schematic diagram illustrating an exemplary embodiment of the present invention, showing the process of flipping the connected silicon substrate and sample strip 180° back to their original positions and then cutting them.

[0038] Figure 12 This is a schematic diagram illustrating the formation of a sample to be circumcised, as shown in an exemplary embodiment of the present invention.

[0039] Figure 13 This is a schematic diagram illustrating the formation of a cone-shaped sample, as shown in an exemplary embodiment of the present invention.

[0040] Explanation of reference numerals in the attached figures:

[0041] 1. Semiconductor substrate; 11. Semiconductor substrate; 12. Word line structure; 121. Dielectric layer; 122. Work function layer; 123. Word line metal layer; 124. Silicate compound; 13. Barrier layer; 2. Pt layer; 3. Sample strip; 4. Silicon substrate; 5. Sample to be circumcised; 6. Sample; 7. Tungsten needle; g. Word line groove. Detailed Implementation

[0042] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that the invention will be thorough and complete, and the concept of the exemplary embodiments will be fully conveyed to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.

[0043] In the following description of different exemplary embodiments of the present disclosure, reference is made to the accompanying drawings, which form part of the present disclosure and illustrate, by way of example, different exemplary structures that can implement various aspects of the present disclosure. It should be understood that other specific embodiments of components, structures, exemplary devices, systems, and steps may be used, and structural and functional modifications may be made without departing from the scope of the present disclosure. Furthermore, while the terms “above,” “between,” “within,” etc., may be used in this specification to describe different exemplary features and elements of the present disclosure, these terms are used herein only for convenience, such as according to the orientation of the examples in the drawings. Nothing in this specification should be construed as requiring a specific three-dimensional orientation of the structure to fall within the scope of the present disclosure. Moreover, the terms “first,” “second,” etc., in the claims are used only as illustrative marks and not as numerical limitations on the object.

[0044] The flowcharts shown in the accompanying drawings are merely illustrative and do not necessarily include all content and operations / steps, nor do they necessarily have to be performed in the described order. For example, some operations / steps can be broken down, while others can be combined or partially combined; therefore, the actual execution order may change depending on the specific circumstances.

[0045] Furthermore, in the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified. "Above" and "below" are technical terms indicating orientation. In the embodiments of this invention, "above" refers to the portion on the semiconductor substrate 11 where each functional layer is sequentially formed, such as the Pt layer 2 located above the word line structure 12. This direction is also the vertical direction described in this invention. These technical terms are merely for clarity and do not have a limiting effect.

[0046] According to one aspect of the present invention, embodiments of the present invention provide a method for preparing a sample for measuring dopant elements in a semiconductor device. For example... Figures 1 to 13 As shown, where, Figure 1 A flowchart of the preparation method of the present invention is shown. Figures 2 to 5 Schematic diagrams are shown of different states of a semiconductor substrate 1 with word lines having its metal layer removed and filled with silicate compound 124. Figures 6 to 13 A schematic diagram showing the sample states at different stages is provided. Figure 1 As shown, an embodiment of the present invention provides a method for preparing a sample for measuring doping elements in a semiconductor device, comprising:

[0047] Step S200: Provide a semiconductor substrate 1 having a word line structure 12, the word line structure 12 including a metal layer;

[0048] Step S400: Polish the semiconductor substrate 1 until the metal layer is exposed.

[0049] Step S600: Etch away the metal layer to form the character line groove g.

[0050] Step S800: Fill the groove g of the letter line with silicate compound 124.

[0051] Step S1000: Deposit a Pt layer 2 on a semiconductor substrate 1 filled with the silicate compound 124.

[0052] Step S1200: Use a focused ion beam to cut the semiconductor substrate 1 to form a sample strip 3.

[0053] Step S1400: Transfer sample strip 3 to the silicon substrate 4 of the three-dimensional atom probe and connect it to the silicon substrate 4.

[0054] Step S1600: Cut the sample strip 3 near the silicon substrate 4, leaving a portion of the sample strip 3 on the silicon substrate 4 as the sample 5 to be circumcised.

[0055] Step S1800: Ring cut the sample 5 to be ring cut to form a cone-shaped sample 6.

[0056] In the preparation method of this invention, by depositing a Pt layer 2 on the semiconductor substrate 11, the target area for sample collection can be located and protected, preventing damage to the sample strip 3. By etching away the metal layer in the word line structure, the sample strip 3 is free of the metal layer of the word line structure 12, and the conical sample 6 formed after circumferential cutting is free of metal elements. During three-dimensional atomic probe measurement, the influence of metal elements is avoided, resulting in a clearer three-dimensional image and improved measurement accuracy.

[0057] The preparation method of the present invention will be described in detail below.

[0058] Step S200: Provide a semiconductor substrate 1 having a word line structure 12, the word line structure 12 including a metal layer.

[0059] like Figure 2 The diagram illustrates a schematic structure of a semiconductor substrate 1 according to an embodiment of the present invention. The semiconductor substrate 1 includes a semiconductor substrate 11, which includes a doped region. In subsequent processes, this doped region can form an active region. When fabricating the word line structure 12, word line trenches are formed in the active region of the semiconductor substrate 11. The word line structure 12 is disposed in a portion of these word line trenches, and the remaining trench portion is filled with a barrier layer 13. The barrier layer 13 is an insulating layer, and the material can be SiN. Figure 2 As shown, the word line structure 12 includes: a dielectric layer 121 formed on the inner wall of the word line trench; a work function layer 122 formed on the dielectric layer 121; and a word line metal layer 123 formed inside the work function layer 122 and filling the word line trench. Of course, other layers may also be included, such as a polysilicon layer between the dielectric layer 121 and the work function layer 122. The above-mentioned functional layers are listed only to illustrate the word line structure and are not intended to be limiting.

[0060] In some embodiments, the material of the work function layer 122 can be TiN, the material of the word line metal layer 123 can be W, and the material of the dielectric layer 121 can be SiO2. Of course, the materials of the functional layers are not limited to these. Since the work function layer 122 contains Ti metal and the word line metal layer 123 contains W metal, the metal layers of the word line structure 12 in this embodiment of the invention include the work function layer 122 and the word line metal layer 123.

[0061] The semiconductor substrate 11 can be made of silicon, silicon carbide, silicon nitride, silicon-on-insulator, silicon-on-insulator, silicon-on-germanide, etc.

[0062] The present invention measures the distribution of doped elements in a semiconductor substrate 11. Therefore, during sample preparation, it is necessary to cut out a semiconductor substrate 11 containing word line structures 12. In actual operation, because the metal layer of the word line structure 12 is embedded in the structure, the sample taken directly will contain metal elements.

[0063] In three-dimensional atom probe microanalysis, when high voltage and pulsed laser are applied to the sample, the rate at which silicon atoms are ionized and deposited is much greater than the rate at which metals are deposited. This difference in deposition rates affects the final three-dimensional imaging, leading to inaccurate measurements. The preparation method of this invention overcomes these shortcomings.

[0064] Step S400: Polish the semiconductor substrate 1 until the metal layer is exposed.

[0065] A sample region is defined on semiconductor substrate 1, such as... Figure 3 As shown, the surface of the semiconductor substrate 1 is ground and polished to expose the metal layer of the word line structure, that is, to expose the upper surface of the work function layer 122 and the word line metal layer 123. The polishing process used for the semiconductor substrate 1 can be chemical mechanical polishing.

[0066] Step S600: Etch away the metal layer to form the letter line groove g.

[0067] like Figure 4 As shown, an etchant is used to etch the metal layer. The etchant used to etch the metal layer is at least one of concentrated nitric acid and hydrofluoric acid. For example, the etchant can be concentrated nitric acid or a mixture of concentrated nitric acid and hydrofluoric acid. After the etchant etches away the metal layer, a character line groove g is formed. At this time, the sidewall of the character line groove g is the dielectric layer 121 of the character line structure.

[0068] Step S800: Fill the groove g of the letter line with silicate compound 124.

[0069] like Figure 5 As shown, a silicate compound 124 is filled into the word line groove g, completely replacing the original metal layer. At this point, the semiconductor substrate 1 in the sample area contains no metal elements and has a smooth surface. The silicate compound 124 can bond well with the dielectric layer 121, and the filling process is simple and cost-effective. The silicate compound 124 can be tetraethyl orthosilicate.

[0070] Step S1000: Deposit a Pt layer 2 on a semiconductor substrate 1 filled with silicate compound 124.

[0071] like Figure 6 As shown, a Pt layer 2 is deposited on the surface of the sample region of the semiconductor substrate 1 filled with silicate compound 124. The Pt layer 2 can be deposited using chemical vapor deposition or atomic layer deposition. The silicate compound 124 can be tetraethyl orthosilicate.

[0072] In one embodiment, the thickness of the Pt layer 2 can be 0.2–0.5 μm. For example, the thickness is 0.35 μm or 0.4 μm, and no particular limitation is made here. The deposited Pt layer 2 can locate the target area for sample collection, i.e., the sample area, and can protect the sample area.

[0073] Step S1200: Use a focused ion beam to cut the semiconductor substrate 1 to form a sample strip 3.

[0074] Continue to refer to Figure 6 After depositing the Pt layer 2, the bottom of the sample region is cut through using a focused ion beam to form a cantilevered sample strip 3. At this time, one end of the sample strip 3 is connected to the semiconductor substrate 11. The two transverse ends of the sample strip 3 can be named the first end and the second end, respectively. The first end is connected to the semiconductor substrate 11, and the second end is a free end.

[0075] Step S1400: Transfer sample strip 3 to the silicon substrate 4 of the three-dimensional atom probe and connect it to the silicon substrate 4.

[0076] like Figure 7 As shown, after obtaining the sample strip 3 with its first end connected to the semiconductor substrate 11 in a cantilever structure, the tungsten needle 7 is moved to the second end of the sample strip 3, as follows: Figure 8 As shown, Pt or W is deposited between the tungsten needle 7 and the second end, that is, the tip of the tungsten needle 7 is welded to the second end of the sample strip 3 with the Pt layer 2, thus connecting the tungsten needle 7 to the second end of the sample strip 3. Figure 9 As shown, the first end of the sample strip 3 is cut from the semiconductor substrate 11 using a focused ion beam to form an independent sample strip 3. Then, the tungsten needle 7 is moved to translate the sample strip 3 to the silicon substrate 4 of the three-dimensional atom probe.

[0077] In one embodiment, the tip diameter of the tungsten needle 7 is 2–6 μm, specifically, it can be 3 μm, 4 μm, or 5 μm. The thickness of the Pt or W deposited between the tungsten needle 7 and the second end is 0.3–0.6 μm, for example, it can be 0.4 μm or 0.5 μm, and the deposition area is 3 μm * 2 μm. Those skilled in the art can adjust the above specific values ​​according to actual conditions, and no special limitations are made here.

[0078] like Figure 10As shown, the silicon substrate 4 and sample strip 3 are rotated 180° together in the vertical direction. At this time, the top of the silicon substrate 4 faces downward. Pt or W is deposited between the first ends of the silicon substrate 4 and the sample strip 3 opposite to the Pt layer 2, so that the silicon substrate 4 is connected to the first end. Rotating the silicon substrate 4 and sample strip 3 together by 180° facilitates the deposition of Pt or W between the first ends of the silicon substrate 4 and sample strip 3, making the operation simpler.

[0079] like Figure 11 As shown, after the silicon substrate 4 is connected to the sample strip 3, the silicon substrate 4 and the sample strip 3 are rotated 180° in the vertical direction to return to their original positions, so as to facilitate subsequent steps.

[0080] Of course, the above flipping can also be performed on the parts, such as... Figure 9 After the sample strip 3 shown is transferred to the silicon substrate 4, Pt or W can be deposited directly between the two. Those skilled in the art can operate according to the actual situation, and no special limitations are made here.

[0081] Step S1600: Cut the sample strip 3 near the silicon substrate 4, leaving a portion of the sample strip 3 on the silicon substrate 4 as the sample 5 to be circumcised.

[0082] like Figure 11 As shown, sample strip 3 was cut using a focused ion beam near the silicon substrate 4. After cutting, as shown... Figure 12 As shown, the portion of the sample strip 3 remaining on the silicon substrate 4 becomes the sample 5 to be circumcised. The term "position near the silicon substrate 4" refers to the dimension from that position to the first end of the sample strip 3, which is the size of the sample 5 to be circumcised; for example, this dimension can be 2μm to 3μm. In one embodiment, the sample strip 3 can ultimately form three samples. In this case, the position near the silicon substrate 4 is one-third of the way from the first end of the sample strip 3. When making the next cut, the position near the silicon substrate 4 is halfway to the remaining sample sleeve. Alternatively, smaller samples can be cut without adhering to the above proportions. Of course, in other embodiments, the sample strip 3 can ultimately form two, four, five, or more samples. In this case, the distance from each cut position to the first end of the sample strip 3 is the size of each sample. Those skilled in the art can adjust this according to actual conditions; no special limitations are made here.

[0083] Step S1800: Ring cut the sample 5 to be ring cut to form a cone-shaped sample 6.

[0084] like Figure 12As shown, after forming the diced sample on the silicon substrate 4, the focused ion beam is set to a ring. Specifically, the etching ring is placed at the center of the sample, and its size is adjusted to ensure a suitable etching amount. High current etching can be used first, followed by low current etching. The ion beam ring etching of the sample 5 to be diced is performed from top to bottom, and the etching process is constantly observed. If the etching amount is too large or too small, adjustments are made immediately to form a suitable result. Figure 13 The cone-shaped sample 6 shown is an example. During the circumferential cutting process, the Pt layer was removed, so the final cone-shaped sample 6 does not contain metallic Pt, thus avoiding the influence of metallic elements.

[0085] In one embodiment, the tip diameter of the conical sample 6 is 100-200 nm, specifically, it can be 120 nm, 150 nm, 180 nm or 190 nm, without any special limitation.

[0086] Steps S200 to S1800 above illustrate a method for preparing the first conical sample 6. After cutting the first sample, the sample strip 3 can be used to cut a second sample. Specifically, this includes: after forming the conical sample 6, removing the sample from the silicon substrate 4; transferring the sample strip 3 back to the silicon substrate 4 and connecting it to the silicon substrate 4, as in step S1400; cutting the sample strip 3 near the silicon substrate 4 to form a second sample 5 to be circumcised, connected to the silicon substrate 4, as in step S1600; circumcising the second sample 5 to be circumcised to form a second conical sample 6, as in step S1800. By repeating the above method, multiple conical samples 6 can be prepared.

[0087] In the preparation method of this invention, by depositing a Pt layer 2 on the semiconductor substrate 11, the target area for sample collection can be located and protected, preventing damage to the sample strip 3. By etching away the metal layer in the word line structure, the sample strip 3 is free of the metal layer of the word line structure 12, and the conical sample 6 formed after circumferential cutting is free of metal elements. During three-dimensional atomic probe measurement, the influence of metal elements is avoided, resulting in a clearer three-dimensional image and improved measurement accuracy.

[0088] According to another aspect of the present invention, embodiments of the present invention provide a sample for measuring doping elements in a semiconductor device, the sample being prepared by the method of any of the above embodiments, which will not be described in detail here.

[0089] The sample prepared by the above method in this invention can form a clear three-dimensional image by measuring the distribution of dopant elements in the sample using a three-dimensional atomic probe, which improves the accuracy of the measurement.

[0090] It should be understood that the application of this invention is not limited to the detailed structure and arrangement of the components presented in this specification. The invention can have other embodiments and can be implemented and performed in various ways. The foregoing variations and modifications fall within the scope of this invention. It should be understood that the invention disclosed and defined in this specification extends to all alternative combinations of two or more individual features mentioned or apparent in the text and / or drawings. All these different combinations constitute multiple alternative aspects of the invention. The embodiments described in this specification illustrate the best known mode for carrying out the invention and will enable those skilled in the art to utilize the invention.

Claims

1. A method for preparing a sample for measuring a doped element in a semiconductor device, characterized by, The application relates to a semiconductor substrate provided with a word line structure, and a method for preparing a sample from the semiconductor substrate. The semiconductor substrate is polished to expose the metal layer. The metal layer is etched to form a word line groove. The word line groove is filled with a silicate compound. A Pt layer is deposited on the semiconductor substrate filled with the silicate compound by chemical vapor deposition or atomic layer deposition, and the thickness of the Pt layer is 0.2-0.5 microns. The semiconductor substrate is cut by a focused ion beam to form a sample strip. The sample strip is transferred to a silicon base of a three-dimensional atom probe and connected to the silicon base. The sample strip is cut at a position close to the silicon base, and a part of the sample strip is left on the silicon base as a sample to be ringed. The sample to be ringed is ringed to form a conical sample. The semiconductor substrate is polished to expose the metal layer.

2. The method of claim 1, wherein, The semiconductor substrate is polished by chemical mechanical polishing. The etching liquid for etching the metal layer is at least one of concentrated nitric acid and hydrofluoric acid.

3. The method of claim 2, wherein, The sample strip is in a cantilever structure, and the sample strip has a first end and a second end, the first end is connected to the semiconductor substrate, and the second end is a free end.

4. The method of claim 1, wherein, The sample strip is transferred to a silicon base of a three-dimensional atom probe and connected to the silicon base.

5. The method of claim 1, wherein, A tungsten needle is moved to the second end of the sample strip, Pt or W is deposited between the tungsten needle and the second end to connect the tungsten needle and the second end.

6. The method of claim 5, wherein, The first end of the sample strip is cut from the semiconductor substrate by the focused ion beam. The tungsten needle is moved to translate the sample strip to the silicon base of the three-dimensional atom probe. The sample strip is transferred to a silicon base of a three-dimensional atom probe and connected to the silicon base. Pt or W is deposited between the silicon base and the first end of the surface opposite to the Pt layer of the sample strip to connect the silicon base and the first end.

7. The method of claim 6, wherein, The thickness of the Pt or W deposited between the tungsten needle and the second end is 0.3-0.6 microns, and the deposition area is 3 microns*2 microns. The top end of the tungsten needle has a diameter of 2-6 microns.

8. The method of claim 6, wherein, The tip of the conical sample has a diameter of 100-200 nanometers.

9. The method of claim 6, wherein, The sample is taken away from the silicon base after the conical sample is formed.

10. The method of claim 1, wherein, The sample strip is transferred to the silicon base again and connected to the silicon base.

11. The method of claim 1, wherein, The sample strip is cut at a position close to the silicon base to form a second sample to be ringed connected to the silicon base. The second sample to be ringed is ringed to form a second conical sample. The above method is repeated to form multiple conical samples. The sample strip forms three conical samples. ​ ​ 12. The method of claim 11, wherein, ​ 13. The method of claim 1, wherein, The metal layer includes a work function layer and a word line metal layer, the work function layer is formed on the dielectric layer, and the word line metal layer is formed inside the work function layer and fills the word line trench.

14. The method of claim 13, wherein, The material of the work function layer is TiN, and the material of the word line metal layer is W.

15. A sample for measuring a dopant element in a semiconductor device, characterized by, The sample is prepared by the method of any one of claims 1 to 14.

Images