Array substrate and display device

Abstract

An array substrate and a display device. The array substrate includes data lines and signal lines, each sub-pixel unit includes a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, the distance between the pixel electrode and the signal line is a second distance D2, the side length of the pixel electrode close to the data line is L1, and the side length of the pixel electrode close to the signal line is L2; ​​each sub-pixel unit also includes a driving transistor, the source of the driving transistor is connected to one of the data line and the signal line, and the drain is connected to the pixel electrode; the drain of the driving transistor is separated from the source by a third distance D3, and separated from the other of the data line and the signal line by a fourth distance D4, the source has a dimension L3 in the second direction, the drain has a dimension L4 in the second direction, and the ratio of (E1*L1 / D1+E2*L3 / D3) to (E1*L2 / D2+E2*L4 / D4) is in the range of 0.9-1.1, thereby effectively avoiding grayscale crosstalk.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to an array substrate and a display device. Background Art

[0002] With the continuous development of technology, display panels are widely used in various electronic devices, such as smartphones, tablets, laptops, and in-car navigation systems. Common display panels can be divided into liquid crystal display (LCD) panels and organic light emitting diode (OLED) display panels. LCD panels have advantages such as fast response speed, high resolution, high integration, low power consumption, and low cost, and therefore occupy a large market share.

[0003] Typically, a liquid crystal display panel includes an array substrate, an opposing substrate, a liquid crystal layer, a first polarizer, and a second polarizer. The array substrate and the opposing substrate are arranged relative to each other, with the liquid crystal layer located between the array substrate and the opposing substrate. The first polarizer is located on the side of the array substrate away from the opposing substrate, and the second polarizer is located on the side of the opposing substrate away from the array substrate. Thin-film transistors (TFTs) and pixel electrodes are provided on the array substrate. The liquid crystal display panel can provide a driving voltage to the pixel electrodes through the thin-film transistors to generate an electric field. This electric field can change the molecular arrangement of the liquid crystal molecules in the liquid crystal layer. In conjunction with the first and second polarizers arranged on both sides of the liquid crystal display panel, a liquid crystal light valve can be formed, thereby realizing the display function. In addition, in conjunction with a color filter layer formed on the array substrate or the opposing substrate, the liquid crystal display panel can further realize color display. Summary of the Invention

[0004] Embodiments of the present disclosure provide an array substrate and a display device. The array substrate effectively avoids grayscale V-crosstalk and improves display quality by ensuring that the parasitic capacitance between the pixel electrode in each sub-pixel unit and other conductive structures on its left and right sides is approximately equal.

[0005] At least one embodiment of the present disclosure provides an array substrate, which includes a base substrate; a plurality of sub-pixel units, which are located on the base substrate and arranged in an array along a first direction and a second direction to form a sub-pixel row extending in the first direction and a sub-pixel column extending in the second direction; a gate line, which is located on the base substrate, extends along the first direction and is configured to provide a gate signal to the sub-pixel row; a data line, which is located on the base substrate, extends along the second direction; and a signal line, which is located on the base substrate, extends along the second direction; the data line and the signal line are respectively located on both sides of the sub-pixel column in the first direction, each of the sub-pixel units includes a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, the distance between the pixel electrode and the signal line is a second distance D2, the side length of the pixel electrode close to the data line is S1, and the The side length of the pixel electrode close to the signal line is L2, each sub-pixel unit further includes a driving transistor, the driving transistor includes a source and a drain, the source is connected to one of the data line and the signal line, the drain is connected to the pixel electrode, the distance between the drain and the source in the first direction is a third distance D3, the distance between the drain and the other of the data line and the signal line is a fourth distance D4, the size of the source in the second direction is L3, the size of the drain in the second direction is L4, the ratio of (E1*L1 / D1+E2*L3 / D3) and (E1*L2 / D2+E2*L4 / D4) ranges from 0.9 to 1.1, E1 is the dielectric constant of the film layer between the pixel electrode and the data line or the signal line, and E2 is the dielectric constant of the film layer between the signal line and the source or the drain.

[0006] For example, in an array substrate provided in an embodiment of the present disclosure, the ratio of (E1*L1 / D1+E2*L3 / D3) to (E1*L2 / D2+E2*L4 / D4) ranges from 0.95 to 1.05.

[0007] For example, in an array substrate provided by an embodiment of the present disclosure, (E1*L1 / D1+E2*L3 / D3)=(E1*L2 / D2+E2*L4 / D4).

[0008] For example, in an array substrate provided in one embodiment of the present disclosure, the data line and the signal line are both configured to transmit data signals, the source electrodes of some of the sub-pixel units in the sub-pixel column are connected to the data line, and the source electrodes of another part of the sub-pixel units in the sub-pixel column are connected to the signal line.

[0009] For example, in an array substrate provided in one embodiment of the present disclosure, the data line located on one side of the j-th sub-pixel column in the first direction is configured to provide a data signal to the j-th sub-pixel column, and the signal line located on the other side of the j-th sub-pixel column in the first direction is configured to provide a data signal to the j+1-th sub-pixel column, where j is a positive integer greater than or equal to 1.

[0010] For example, in an array substrate provided in one embodiment of the present disclosure, the signal line located on one side of the j-th sub-pixel column in the first direction and the data line located on one side of the j+1-th sub-pixel column in the first direction are configured to be connected to the same signal end.

[0011] For example, in an array substrate provided in an embodiment of the present disclosure, the signal line is configured to transmit a common electrode signal.

[0012] For example, in an array substrate provided by an embodiment of the present disclosure, the connection portion between the pixel electrode and the drain electrode is located on an area bisector of the pixel electrode in the first direction.

[0013] For example, in an array substrate provided in an embodiment of the present disclosure, the side length L1 of the pixel electrode close to the data line is equal to the side length L2 of the pixel electrode close to the signal line, and the first distance D1 is equal to the second distance D2.

[0014] For example, in an array substrate provided by an embodiment of the present disclosure, a dimension L3 of the source in the second direction is equal to a dimension L4 of the drain in the second direction, and the third distance D3 is equal to the fourth distance D4.

[0015] For example, in an array substrate provided by an embodiment of the present disclosure, each sub-pixel unit includes a first region and a second region sequentially arranged along the second direction, the pixel electrode is located in the first region, and the driving transistor is located in the second region.

[0016] For example, in an array substrate provided in one embodiment of the present disclosure, the source electrode and the data line or the signal line connected to the source electrode are arranged relatively spaced apart, and the array substrate also includes a conductive connection block, and the source electrode is connected to the data line or the signal line connected to the source electrode through the conductive connection block, and the distance between the source electrode and the data line or the signal line connected to the source electrode is a fifth distance D5, and the fifth distance D5 is equal to the fourth distance D4.

[0017] For example, in an array substrate provided in an embodiment of the present disclosure, the width of the sub-pixel unit in the first direction is Wpixel, the driving transistor includes an active layer, the length of the channel region of the active layer in the first direction is L, the length of the channel region of the active layer in the second direction is W, the width of the source in the first direction is Wsource, the width of the drain in the first direction is Wdrain, the width of the data line and the signal line in the first direction is Wdata, and the length of the channel region of the active layer in the first direction is L, satisfying the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain) / 3.

[0018] For example, in an array substrate provided by an embodiment of the present disclosure, the length L of the channel region of the active layer in the first direction satisfies the following formula:

[0019] Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain) / 4.

[0020] For example, in an array substrate provided by an embodiment of the present disclosure, the source electrode is a portion of the data line or the signal line connected to the source electrode.

[0021] For example, in an array substrate provided in an embodiment of the present disclosure, the width of the sub-pixel unit in the first direction is Wpixel, the driving transistor includes an active layer, the length of the channel region of the active layer in the first direction is L, the length of the channel region of the active layer in the second direction is W, the width of the source in the first direction is Wsource, the width of the drain in the first direction is Wdrain, the width of the data line and the signal line in the first direction is Wdata, and the length of the channel region of the active layer in the first direction is L, satisfying the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wdrain) / 2.

[0022] For example, in an array substrate provided by an embodiment of the present disclosure, the orthographic projection of the pixel electrode on the base substrate is axisymmetric about the area bisector of the pixel electrode in the first direction.

[0023] For example, in an array substrate provided by an embodiment of the present disclosure, the pixel electrode includes a first domain, a second domain, a third domain and a fourth domain, the first domain and the second domain are axially symmetrical about the area bisector of the pixel electrode in the first direction, the third domain and the fourth domain are axially symmetrical about the area bisector of the pixel electrode in the first direction, the first domain and the third domain are arranged in sequence along the second direction, and the second domain and the fourth domain are arranged in sequence along the second direction.

[0024] For example, in an array substrate provided in one embodiment of the present disclosure, the pixel electrode includes a middle portion, extending along the second direction, and located between the first domain and the second domain, and between the third domain and the fourth domain, and the drain is connected to the middle portion of the pixel electrode.

[0025] For example, in an array substrate provided in one embodiment of the present disclosure, the pixel electrode includes: a plurality of first slits arranged at intervals, located in the first domain; a plurality of second slits arranged at intervals, located in the second domain; a plurality of third slits arranged at intervals, located in the third domain; and a plurality of fourth slits arranged at intervals, located in the fourth domain.

[0026] For example, in an array substrate provided by an embodiment of the present disclosure, the multiple sub-pixel units form n sub-pixel rows arranged in the second direction, the array substrate includes n gate lines, which are arranged in a one-to-one correspondence with the n sub-pixel rows, the kth gate line and the k+1th gate line form a (k+1) / 2th gate line group, the array substrate also includes a first vertical gate line and a second vertical gate line, which are respectively located on both sides of the multiple sub-pixel units in the first direction, and in the (k+1) / 2th gate line group, the kth gate line and the k+1th gate line are connected through the first vertical gate line and the second vertical gate line, k can be an odd number greater than or equal to 1, and n is a positive integer greater than k.

[0027] For example, in an array substrate provided by an embodiment of the present disclosure, the first vertical gate line and the second vertical gate line are provided in the same layer as the data line.

[0028] For example, in an array substrate provided in one embodiment of the present disclosure, the first vertical gate line is connected to the kth gate line through a first via connection structure, the first vertical gate line is connected to the k+1th gate line through a second via connection structure, the second vertical gate line is connected to the kth gate line through a third via connection structure, and the second vertical gate line is connected to the k+1th gate line through a fourth via connection structure.

[0029] For example, in an array substrate provided in one embodiment of the present disclosure, the array substrate further includes at least one intermediate vertical gate line, which is located between two adjacent sub-pixel columns, and in the (k+1) / 2th gate line group, the kth gate line and the k+1th gate line are connected through the intermediate vertical gate line.

[0030] For example, in an array substrate provided by an embodiment of the present disclosure, the middle vertical gate lines are provided in the same layer as the gate lines.

[0031] For example, an array substrate provided by an embodiment of the present disclosure also includes: a first common electrode line extending along the first direction; and a second common electrode line extending along the second direction, each of the sub-pixel units includes a first area and a second area arranged in sequence along the second direction, the pixel electrode is located in the first area, the driving transistor is located in the second area, the first common electrode line is located between two adjacent sub-pixel units in the second direction, and between the first area and the second area of ​​the same sub-pixel unit, and the second common electrode line is located between two adjacent sub-pixel columns.

[0032] For example, in an array substrate provided in an embodiment of the present disclosure, the first common electrode line and the gate line are arranged in the same layer, the first common electrode line includes at least one first notch and first sub-common electrode lines located on both sides of the first notch, the middle vertical gate line passes through the first notch, and is respectively insulated from the first sub-common electrode lines.

[0033] For example, in an array substrate provided in one embodiment of the present disclosure, the second common electrode line includes a gate layer common electrode line and a data line layer common electrode line, the gate layer common electrode line is arranged on the same layer as the gate line, the data line layer common electrode line is arranged on the same layer as the data line, and the gate layer common electrode line is connected to the data line layer common electrode line through a fifth via connection structure.

[0034] For example, in an array substrate provided by an embodiment of the present disclosure, two first common electrode lines are arranged between the kth gate line and the k+1th gate line in the (k+1) / 2th gate line group, and respectively include the first notch, and the middle vertical gate line passes through the two first notches of the two first common electrode lines to connect the kth gate line and the k+1th gate line.

[0035] For example, in an array substrate provided by an embodiment of the present disclosure, the width of a portion of the second common electrode line located in the first region is greater than the width of a portion of the second common electrode line located in the second region.

[0036] For example, in an array substrate provided by an embodiment of the present disclosure, the second common electrode line is located between the lth sub-pixel column and the l+1th sub-pixel column, the distance between the second common electrode line and the signal line corresponding to the lth sub-pixel column is equal to the distance between the second common electrode line and the data line corresponding to the l+1th sub-pixel column, or the distance between the second common electrode line and the data line corresponding to the lth sub-pixel column is equal to the distance between the second common electrode line and the signal line corresponding to the l+1th sub-pixel column, and l is a positive integer greater than or equal to 1.

[0037] For example, in an array substrate provided in an embodiment of the present disclosure, each of the sub-pixel units includes a first area and a second area arranged in sequence along the second direction, the pixel electrode is located in the first area, the driving transistor is located in the second area, the distance between the portion of the data line in the first area and the portion of the signal line in the first area in the first direction is smaller than the distance between the portion of the data line in the second area and the portion of the signal line in the second area in the first direction, the data line includes a first inclined connection portion, connecting the portion of the data line in the first area and the portion of the data line in the second area, and the signal line includes a second inclined connection portion, connecting the portion of the signal line in the first area and the portion of the signal line in the second area.

[0038] For example, an array substrate provided by an embodiment of the present disclosure also includes: a plurality of gate lead lines, each of the gate lead lines is located between two adjacent sub-pixel columns, and each of the gate lead lines includes: a first gate lead line, which is arranged on the same layer as the data line and is configured to connect the gate signal; a second gate lead line, which is arranged on the same layer as the gate line and is configured to be connected to the corresponding gate line, and the first gate lead line and the second gate lead line are connected through a fifth via structure.

[0039] For example, in an array substrate provided by an embodiment of the present disclosure, the gate lead line is configured to be electrically connected to the (m+1) / 2th gate line group, the second gate lead line is directly connected to the mth gate line, m is an odd number greater than or equal to 1, the m-1th gate line includes a second notch, three first common electrode lines are arranged between the mth gate line and the m-2th gate line, and each includes a first notch, the second gate lead line passes through the second notch of the m-1th gate line and the three first notches of the three first common electrode lines, and extends to the position of the sixth via connection structure, the sixth via connection structure is located between the m-2th gate line and the first common electrode line, and the first gate lead line is connected to the second gate lead line through the sixth via connection structure.

[0040] For example, an array substrate provided by an embodiment of the present disclosure further includes: a shielding electrode, which is located on the base substrate and is provided in the same layer as the gate line.

[0041] For example, in an array substrate provided in one embodiment of the present disclosure, the orthographic projection of the shielding electrode on the base substrate is located between the orthographic projection of the second common electrode line on the base substrate and the orthographic projection of the data line on the base substrate, and between the orthographic projection of the second common electrode line on the base substrate and the orthographic projection of the signal line on the base substrate.

[0042] For example, in an array substrate provided by an embodiment of the present disclosure, the orthographic projection of the shielding electrode on the base substrate is also located between the orthographic projection of the data line on the base substrate and the orthographic projection of the signal line on the base substrate.

[0043] At least one embodiment of the present disclosure further provides a display device, comprising any of the array substrates described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, rather than limiting the present disclosure.

[0045] Figure 1 is a planar schematic diagram of an array substrate;

[0046] Figure 2 A schematic plan view of an array substrate provided in one embodiment of the present disclosure;

[0047] Figure 3 An enlarged schematic diagram of a driving transistor in an array substrate provided in one embodiment of the present disclosure;

[0048] Figure 4 A schematic plan view of another array substrate provided in one embodiment of the present disclosure;

[0049] Figure 5 An enlarged schematic diagram of a driving transistor in another array substrate provided by an embodiment of the present disclosure;

[0050] Figure 6A A schematic plan view of another array substrate provided in one embodiment of the present disclosure;

[0051] Figure 6B A schematic plan view of another array substrate provided in one embodiment of the present disclosure;

[0052] Figure 7AA schematic diagram of another array substrate provided in one embodiment of the present disclosure;

[0053] Figure 7B A schematic diagram of another array substrate provided in one embodiment of the present disclosure;

[0054] Figure 8A An array substrate provided by an embodiment of the present disclosure is Figure 7A Schematic diagram of the cross section of the AB line;

[0055] Figure 8B An array substrate provided by an embodiment of the present disclosure Figure 7A Schematic cross-section of the mid-CD line;

[0056] Figure 9 A schematic plan view of another array substrate provided in one embodiment of the present disclosure;

[0057] Figure 10 A schematic plan view of another array substrate provided in one embodiment of the present disclosure;

[0058] Figure 11 A schematic diagram of a display device provided in one embodiment of the present disclosure; and

[0059] Figure 12 A schematic cross-sectional view of a display device provided in accordance with an embodiment of the present disclosure. DETAILED DESCRIPTION

[0060] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0061] Unless otherwise defined, technical or scientific terms used in this disclosure should have the ordinary meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar terms used in this disclosure do not indicate any order, quantity or importance, but are simply used to distinguish different components. The words "include" or "comprising" and similar terms mean that the elements or objects preceding the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects.

[0062] Figure 1 FIG. 1 is a planar schematic diagram of an array substrate. Figure 1As shown, the array substrate 10 includes a base substrate 11, multiple gate lines 12, and multiple data lines 13; the multiple gate lines 12 and the multiple data lines 13 are arranged to intersect with each other to define multiple pixel units 20; each pixel unit 20 includes a pixel electrode 14, a common electrode 15, and a driving transistor 16; the gate line 12 is connected to the gate of the driving transistor 16, the data line 13 is connected to the source of the driving transistor 16, and the pixel electrode 14 is connected to the drain of the driving transistor 16. In order to achieve continuous light emission, a storage capacitor is required between the pixel electrode 14 and the common electrode 15 in the pixel unit 20. However, in an actual array substrate, in addition to the storage capacitor used for normal display, the pixel electrode 14 also forms parasitic capacitance with other conductive structures. For example, a parasitic capacitance Cpd1 is formed between the pixel electrode 14 and the data line 13, and a parasitic capacitance Cpd2 is formed between the pixel electrode 14 and the source of the driving transistor 16.

[0063] like Figure 1 As shown, since the driving transistor 16 is usually arranged close to the data line 13, it is easy to cause the pixel electrode 14 to generate different parasitic capacitances with other conductive structures on the left and right sides. On the left, the pixel electrode 14 forms a parasitic capacitance Cpd1 with the data line 13 on the left, and forms a parasitic capacitance Cpd2 with the source of the driving transistor 16; on the right, the pixel electrode 14 forms a parasitic capacitance Cpd3 with the data line 13 on the right. At this time, the parasitic capacitance C1 generated by the pixel electrode 14 and the conductive structure on the left is Cpd1+Cpd2, and the parasitic capacitance C2 generated by the pixel electrode 14 and the conductive structure on the right is Cpd3. Usually, Cpd1 and Cpd3 are roughly equal. At this time, the parasitic capacitance C1 generated by the pixel electrode 14 and the conductive structure on the left is greater than the parasitic capacitance C2 generated by the pixel electrode 14 and the conductive structure on the right.

[0064] The difference in parasitic capacitance between the pixel electrode 14 and other conductive structures on the left and right sides will lead to poor grayscale V-Crosstalk (crosstalk); and, for high-resolution products, such as 8K products, due to the smaller size of the pixel unit, its own storage capacitance is smaller, and therefore it is more susceptible to the pull of parasitic capacitance. The difference in parasitic capacitance between the pixel electrode and other conductive structures on the left and right sides will cause poor V-Crosstalk.

[0065] In this regard, an embodiment of the present disclosure provides an array substrate and a display device. The array substrate includes a base substrate, a plurality of sub-pixel units, a gate line, a data line, and a signal line; the plurality of sub-pixel units are located on the base substrate, and the plurality of sub-pixel units are arrayed along a first direction and a second direction to form a sub-pixel row extending in the first direction and a sub-pixel column extending in the second direction; the gate line is located on the base substrate, extends along the first direction and is configured to provide a gate signal to the sub-pixel row; the data line is located on the base substrate, extends along the second direction; the signal line is located on the base substrate, and extends in the second direction; the data line and the signal line are respectively located on both sides of the sub-pixel column in the first direction, each sub-pixel unit includes a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, the distance between the pixel electrode and the signal line is a second distance D2, and the pixel electrode is close to the data line. The side length of the line is L1, and the side length of the pixel electrode close to the signal line is L2; ​​each sub-pixel unit also includes a driving transistor, the driving transistor includes a source and a drain, the source is connected to one of the data line and the signal line, and the drain is connected to the pixel electrode; the distance between the drain and the source in the first direction is a third distance D3, and the distance between the drain and the other of the data line and the signal line is a fourth distance D4, the size of the source in the second direction is L3, and the size of the drain in the second direction is L4, the ratio range of (E1*L1 / D1+E2*L3 / D3) and (E1*L2 / D2+E2*L4 / D4) is 0.9-1.1, E1 is the dielectric constant of the film layer between the pixel electrode and the data line or the signal line, and E2 is the dielectric constant of the film layer between the drain and the source or the signal line. Therefore, since the ratio range of (E1*L1 / D1+E2*L3 / D3) and (E1*L2 / D2+E2*L4 / D4) is 0.9-1.1, the parasitic capacitance generated by the pixel electrode in each sub-pixel unit and other conductive structures on the left and right sides is roughly equal, which can effectively avoid grayscale V-Crosstalk (crosstalk) defects and improve display quality.

[0066] The array substrate and the display device provided by the embodiments of the present disclosure are described in detail below with reference to the accompanying drawings.

[0067] An embodiment of the present disclosure provides an array substrate. Figure 2 FIG. 1 is a plan view of an array substrate provided in one embodiment of the present disclosure. Figure 2As shown, the array substrate 100 includes a base substrate 110, a plurality of sub-pixel units 120, a gate line 130, a data line 141 and a signal line 142; the plurality of sub-pixel units 120 are located on the base substrate 110, and the plurality of sub-pixel units 120 are arrayed along a first direction X and a second direction Y to form sub-pixel rows 210 extending in the first direction X and sub-pixel columns 220 extending in the second direction Y; the gate line 130 is located on the base substrate 110, extends along the first direction and is configured to provide gate signals to the sub-pixel rows 210; the data line 141 is located on the base substrate 110 and extends along the second direction; the signal line 142 is located on the base substrate 110 and extends along the second direction; the data line 141 and the signal line 142 are respectively located on both sides of the sub-pixel column 220 in the first direction, and each sub-pixel unit 120 includes a pixel electrode 122.

[0068] like Figure 2 As shown, the distance between the pixel electrode 122 and the data line 141 is a first distance D1, the distance between the pixel electrode 122 and the signal line 142 is a second distance D2, the side length of the pixel electrode 122 close to the data line 141 is L1, and the side length of the pixel electrode 122 close to the signal line 142 is L2; ​​each sub-pixel unit 120 further includes a driving transistor T1, the driving transistor T1 includes a source Source1 and a drain Drain1, the source Source1 is connected to one of the data line 141 and the signal line 142, and the drain Drain1 is connected to the pixel electrode 122; the drain Drain1 and the source Source1 are connected in the first direction The distance on X is a third distance D3, the distance between the drain Drain1 and the other of the data line 141 and the signal line 142 is a fourth distance D4, the size of the source Source1 in the second direction is L3, the size of the drain Drain1 in the second direction is L4, the ratio of (E1*L1 / D1+E2*L3 / D3) and (E1*L2 / D2+E2*L4 / D4) ranges from 0.9 to 1.1, E1 is the dielectric constant of the film layer between the pixel electrode 122 and the data line 141 or the signal line 142, and E2 is the dielectric constant of the film layer between the signal line 142 and the source Source1 or the drain Drain1.

[0069] In the array substrate provided by the embodiment of the present disclosure, the pixel electrode 122 has a first side in the first direction X (eg Figure 2 The data line 141 is provided on the left side in the first direction X, and the data line 141 is provided on the second side in the first direction X (for example Figure 2A signal line 142 is provided on the right side of the pixel electrode 122. On the first side of the pixel electrode 122, the parasitic capacitance Cpd1 between the pixel electrode 122 and the data line 141 is equal to E1*L1 / D1, and the parasitic capacitance Cpd2 between the drain electrode Drain1 and the source electrode Source1 connected to the pixel electrode 122 is equal to E2*L3 / D3. At this time, the parasitic capacitance C1 between the pixel electrode 122 and the conductive structure on the first side of the pixel electrode 122 is equal to E1*L1 / D1+E2*L3 / D3. On the second side of the pixel electrode 122, the parasitic capacitance Cpd3 between the pixel electrode 122 and the signal line 142 is equal to E1*L2 / D2, and the parasitic capacitance Cpd4 between the drain electrode Drain1 connected to the pixel electrode 122 and the data line 141 or the signal line 142 is equal to E2*L4 / D4. At this time, the parasitic capacitance C2 between the pixel electrode 122 and the conductive structure on the second side of the pixel electrode 122 is equal to E1*L2 / D2+E2*L4 / D4. Since the ratio of (E1*L1 / D1+E2*L3 / D3) to (E1*L2 / D2+E2*L4 / D4) is in the range of 0.9-1.1, the pixel electrode in each sub-pixel unit and the first side and the second side of the pixel electrode in the first direction (for example, Figure 2 The parasitic capacitance generated by other conductive structures (on the left and right sides) is roughly equal, thereby effectively avoiding grayscale V-crosstalk and improving display quality. It should be noted that the first side and the second side of the pixel electrode are divided by the area bisector of the pixel electrode in the first direction.

[0070] In some examples, the ratio of (E1*L1 / D1+E2*L3 / D3) to (E1*L2 / D2+E2*L4 / D4) ranges from 0.95 to 1.05, thereby better avoiding grayscale V-Crosstalk (crosstalk) defects and improving display quality.

[0071] In some examples, the ratio of (E1*L1 / D1+E2*L3 / D3) to (E1*L2 / D2+E2*L4 / D4) ranges from 0.99 to 1.01, thereby better avoiding grayscale V-Crosstalk (crosstalk) defects and improving display quality.

[0072] In some examples, the ratio of (E1*L1 / D1+E2*L3 / D3) to (E1*L2 / D2+E2*L4 / D4) ranges from 0.995 to 1.005, thereby better avoiding grayscale V-Crosstalk (crosstalk) defects and improving display quality.

[0073] In some examples, the ratio of (E1*L1 / D1+E2*L3 / D3) to (E1*L2 / D2+E2*L4 / D4) is equal to 1, thereby better avoiding grayscale V-Crosstalk defects and improving display quality.

[0074] In some examples, such as Figure 2 As shown, the data line 141 located on one side of the j-th sub-pixel column 220 in the first direction is configured to provide a data signal to the j-th sub-pixel column 220, and the signal line 142 located on the other side of the j-th sub-pixel column 220 in the first direction is configured to provide a data signal to the j+1-th sub-pixel column 220, where j is a positive integer greater than or equal to 1. In other words, both the data line 141 and the signal line 142 are configured to transmit data signals.

[0075] In some examples, such as Figure 2 As shown, the signal line 142 located on one side of the j-th sub-pixel column 220 in the first direction and the data line 141 located on one side of the j+1-th sub-pixel column 220 in the first direction are configured to be connected to the same signal terminal. In this case, the signal line 142 located on one side of the j-th sub-pixel column 220 in the first direction is configured to transmit the same data signal as the data line 141 located on one side of the j+1-th sub-pixel column 220 in the first direction.

[0076] In some examples, the signal line can also be used to transmit other signals, for example, the signal line is configured to transmit a common electrode signal. Figure 2 As shown, the gate line 130 is insulated from the data line 141 and the signal line 142; for example, the data line 141 and the signal line 142 are arranged in the same layer, and an insulating layer can be provided between the layer where the gate line 130 is located and the layer where the data line 141 and the signal line 142 are located.

[0077] For example, the film layer between the pixel electrode 122 and the data line 141 or the signal line 142 may be an optical adhesive layer; the material of the optical adhesive layer includes polyethylene, and the dielectric constant thereof may be in the range of 2.2-2.5.

[0078] For example, the film layer between the signal line 142 and the source electrode Source1 or the drain electrode Drain1 may be a passivation layer; the material of the passivation layer includes silicon nitride, silicon oxide or silicon oxynitride, and the dielectric constant thereof may be in the range of 1.56-3.9.

[0079] For example, the base substrate 110 may be a glass substrate, a plastic substrate, a quartz substrate, or a polyimide substrate. Of course, the embodiments of the present disclosure include but are not limited to these, and the base substrate may also be other substrates.

[0080] For example, the gate lines 130, the data lines 141, and the signal lines 142 may be made of the same conductive material or different conductive materials. For example, the materials of the gate lines 130, the data lines 141, and the signal lines 142 include one or more selected from aluminum, aluminum alloy, copper, copper alloy, molybdenum, and molybdenum-aluminum alloy.

[0081] For example, the first distance D1 between the pixel electrode 122 and the data line 141 can be in the range of 10-12 microns, for example, 10.9 microns; the second distance D2 between the pixel electrode 122 and the signal line 142 can also be in the range of 10-12 microns, for example, 10.9 microns; the third distance D3 between the drain Drain1 and the source Source1 in the first direction X can be in the range of 5.1-6.4 microns, for example, 5.79 microns; the fourth distance D4 between the drain Drain1 and the signal line 142 can be in the range of 5.1-6.4 microns, for example, 5.79 microns.

[0082] For example, the side length L1 of the pixel electrode 122 close to the data line 141 can be in the range of 110-120 microns, for example, 114 microns; the side length L2 of the pixel electrode 122 close to the signal line 142 can also be 110-120 microns, for example, 114 microns; the dimension L3 of the source Source1 in the second direction can be in the range of 20-24 microns, for example, 22 microns; the dimension L4 of the drain Drain in the second direction can be in the range of 20-24 microns, for example, 22 microns.

[0083] In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=10.1 μm, L2=119 μm, D3=5.2 μm, L3=22.1 μm, D4=5.1 μm, L4=22.1 μm, therefore, (E1*L1 / D1+E2*L3 / D3) / (E1*L2 / D2+E2*L4 / D4)=0.900.

[0084] In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=10.6 μm, L2=114 μm, D3=5.2 μm, L3=22.1 μm, D4=5.1 μm, L4=23.9 μm, therefore, (E1*L1 / D1+E2*L3 / D3) / (E1*L2 / D2+E2*L4 / D4)=0.950.

[0085] In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=11 μm, L2=114 μm, D3=5.2 μm, L3=22.1 μm, D4=5.2 μm, L4=22.1 μm, therefore, (E1*L1 / D1+E2*L3 / D3) / (E1*L2 / D2+E2*L4 / D4)=1.

[0086] In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=11.1 μm, L2=114 μm, D3=5.2 μm, L3=22.1 μm, D4=6.4 μm, L4=22.1 μm, therefore, (E1*L1 / D1+E2*L3 / D3) / (E1*L2 / D2+E2*L4 / D4)=1.051.

[0087] In some examples, E1=2.3, E2=1.6, D1=11 μm, L1=114 μm, D2=11.8 μm, L2=114 μm, D3=5.2 μm, L3=22.1 μm, D4=6.4 μm, L4=22.6 μm, therefore, (E1*L1 / D1+E2*L3 / D3) / (E1*L2 / D2+E2*L4 / D4)=1.099.

[0088] In some examples, such as Figure 2 As shown, the connection portion 1220 between the pixel electrode 122 and the drain electrode Drain1 is located on the area bisector of the pixel electrode 122 in the first direction. As a result, the parasitic capacitance Cpd2 between the drain electrode Drain1 and the source electrode Source1 and the parasitic capacitance Cpd4 between the drain electrode Drain1 and the signal line 142 are both connected in the middle of the pixel electrode 122 in the first direction, thereby more evenly affecting the parasitic capacitances on both sides of the pixel electrode 122 in the first direction, thereby further effectively avoiding grayscale V-crosstalk and improving display quality. It should be noted that the aforementioned area bisector can be the area bisector of the orthographic projection of the pixel electrode on the substrate.

[0089] In some examples, such as Figure 2 As shown, the length L1 of the side of the pixel electrode 122 near the data line 141 is equal to the length L2 of the side of the pixel electrode 122 near the signal line 142, and the first distance D1 is equal to the second distance D2. Therefore, the parasitic capacitance Cpd1 = E1 * L1 / D1 between the pixel electrode 122 and the data line 141 is equal to the parasitic capacitance Cpd3 = E1 * L2 / D2 between the pixel electrode 122 and the signal line 142, thereby ensuring that the parasitic capacitances generated by the data line 141 and the signal line 142 on both sides of the pixel electrode 122 and the pixel electrode 122 are equal.

[0090] In some examples, such as Figure 2 As shown, the dimension L3 of the source electrode Source1 in the second direction Y is equal to the dimension L4 of the drain electrode Drain1 in the second direction Y, and the third distance D3 is equal to the fourth distance D4. Therefore, the parasitic capacitance Cpd2 = E2 * L3 / D3 between the drain electrode Drain1 and the source electrode Source1 and the parasitic capacitance Cpd4 = E2 * L4 / D4 between the drain electrode Drain1 and the signal line 142 are equal, thereby ensuring that the parasitic capacitances generated by the source electrode Source1 and the signal line 142 on the left and right sides of the drain electrode Drain1 are equal.

[0091] In the array substrate provided in the above example, by setting the parasitic capacitance Cpd1=E1*L1 / D1 between the pixel electrode 122 and the data line 141 and the parasitic capacitance Cpd3=E1*L2 / D2 between the pixel electrode 122 and the signal line 142 to be equal, and setting the parasitic capacitance Cpd2=E2*L3 / D3 between the drain Drain1 and the source Source1 and the parasitic capacitance Cpd4=E2*L4 / D4 between the drain Drain1 and the signal line 142 to be equal, it can better ensure that E1*L1 / D1+E2*L3 / D3=E1*L2 / D2+E2*L4 / D4, thereby effectively avoiding poor grayscale V-Crosstalk and improving display quality.

[0092] In some examples, such as Figure 2 As shown, each sub-pixel unit 120 includes a first region 120A and a second region 120B sequentially arranged along the second direction Y. The pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region 120B. In this case, the first region 120A can be a light-emitting region or a color filter region, and the second region 120B can be a driving region or a TFT region.

[0093] In some examples, such as Figure 2As shown, in the second area 120B, the source electrode Source1 and the data line 141 or signal line 142 connected to the source electrode Source1 are arranged relatively spaced apart. At this time, the array substrate 100 further includes a conductive connection block 151, and the source electrode Source1 is connected to the data line 141 or signal line 142 connected to the source electrode Source1 through the conductive connection block 151; the distance between the source electrode Source1 and the data line 141 or signal line 142 connected to the source electrode Source1 is a fifth distance D5, and the fifth distance D5 is equal to the fourth distance D4. In other words, the third distance D3, the fourth distance D4, and the fifth distance D5 are all equal. As a result, the driving transistor T1 is located as a whole on the area bisector of the pixel electrode 122 in the first direction, thereby improving the symmetry of the driving transistor T1, and further improving the symmetry of the sub-pixel unit 120.

[0094] like Figure 2 As shown, Figure 2 Four sub-pixel units 120 are shown, including a first sub-pixel unit 1201, a second sub-pixel unit 1202, a third sub-pixel unit 1203, and a fourth sub-pixel unit 1204. The first sub-pixel unit 1201, the second sub-pixel unit 1202, the third sub-pixel unit 1203, and the fourth sub-pixel unit 1204 are arranged in sequence along a first direction X. In the first sub-pixel unit 1201 and the second sub-pixel unit 1202, the source electrode Source1 is connected to the data line 141; in the third sub-pixel unit 1203 and the fourth sub-pixel unit 1204, the source electrode Source1 is connected to the signal line 142. Thus, taking the above four sub-pixel units 120 as a whole, the symmetry of these four sub-pixel units 120 in the first direction is improved.

[0095] In some examples, such as Figure 2 As shown, the orthographic projection of the pixel electrode 122 on the base substrate 110 is axisymmetric about the area bisector of the pixel electrode 122 in the first direction, thereby improving the symmetry of the pixel electrode 122 .

[0096] In some examples, such as Figure 2As shown, the pixel electrode 122 includes a first domain 161, a second domain 162, a third domain 163, and a fourth domain 164. The first domain 161 and the second domain 162 are axially symmetrical about a line bisectoring the area of ​​the pixel electrode 122 in the first direction X, while the third domain 163 and the fourth domain 164 are axially symmetrical about a line bisectoring the area of ​​the pixel electrode 122 in the first direction X. The first domain 161 and the third domain 163 are arranged sequentially along the second direction Y, while the second domain 162 and the fourth domain 163 are arranged sequentially along the second direction Y. Thus, by arranging the pixel electrode 122 into the first domain 161, the second domain 162, the third domain 163, and the fourth domain 164, the array substrate can reduce color shift and improve display quality.

[0097] In addition, since the first domain 161 and the second domain 162 are axisymmetric about the area bisector of the pixel electrode 122 in the first direction X, and the third domain 163 and the fourth domain 164 are axisymmetric about the area bisector of the pixel electrode 122 in the first direction X, the pixel electrode 122 has high symmetry.

[0098] In some examples, such as Figure 2 As shown, the pixel electrode 122 further includes a middle portion 1225, which extends along the second direction Y and is located between the first domain 161 and the second domain 162, and between the third domain 163 and the fourth domain 164. The drain electrode Drain1 is connected to the middle portion 1225 of the pixel electrode 122. As a result, the parasitic capacitance Cpd2 between the drain electrode Drain1 and the source electrode Source1, and the parasitic capacitance Cpd4 between the drain electrode Drain1 and the signal line 142 are both connected in the middle of the pixel electrode 122 in the first direction. This makes the influence of the parasitic capacitance on both sides of the pixel electrode 122 in the first direction more balanced, thereby further effectively preventing grayscale V-crosstalk and improving display quality.

[0099] In some examples, such as Figure 2 As shown, the pixel electrode 122 includes a plurality of first slits 1224A arranged at intervals, located in the first domain 161; a plurality of second slits 1224B arranged at intervals, located in the second domain 162; a plurality of third slits 1224C arranged at intervals, located in the third domain 163; and a plurality of fourth slits 1224D arranged at intervals, located in the fourth domain 164.

[0100] Figure 3 This is an enlarged schematic diagram of a driving transistor in an array substrate provided by an embodiment of the present disclosure. Figure 3As shown, the sub-pixel unit 120 has a width of Wpixel in the first direction X, the driving transistor T1 includes an active layer A1, the channel region of the active layer A1 has a length of L in the first direction X, and the channel region of the active layer A has a length of W in the second direction Y; the width of the source electrode Source1 in the first direction X is Wsource, the width of the drain electrode Drain1 in the first direction X is Wdrain, and the width of the data line 141 or the signal line 142 in the first direction X is Wdata. In this case, the length L of the channel region of the active layer A1 in the first direction X satisfies the following formula:

[0101] Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain) / 3.

[0102] In the array substrate provided by the embodiment of the present disclosure, the turn-on current I of the driving transistor T1 is on The calculation formula is as follows:

[0103]

[0104] Wherein, W and L are the width and length of the channel region of the active layer A1 of the driving transistor T1, μ n is the equivalent electron mobility, C SiNx is the capacitance of the driving transistor T1, V TH is the threshold voltage of the driving transistor T1, V G and V D is the voltage of the gate G1 and drain Drain1 of the driving transistor T1 relative to the source Source1.

[0105] It can be seen from the above formula that the current I on The main factors are the ratio of the width and length of the channel region W / L, electron mobility, etc. In order to obtain a larger turn-on current I on , the ratio of the width to the length of the channel region, W / L, needs to be set larger. Therefore, by ensuring that the length L of the channel region of the active layer A1 in the first direction X satisfies the following formula: Wsource + Wdrain < L < (Wpixel - 2Wdata - Wsource - Wdrain) / 3, the length L of the channel region of the active layer A1 in the first direction X can be reduced, thereby increasing the ratio W / L of the width to the length of the channel of the driving transistor T1, thereby increasing the turn-on current.

[0106] In some examples, the length L of the channel region of the active layer A1 in the first direction X satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain) / 4. Thus, by ensuring that the length L of the channel region of the active layer A1 in the first direction X satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain) / 4, the length L of the channel region of the active layer A1 in the first direction X can be further reduced, thereby increasing the ratio W / L of the width to length of the channel of the driving transistor T1, thereby increasing the turn-on current.

[0107] Figure 4 This is a schematic plan view of another array substrate provided by an embodiment of the present disclosure. Figure 4 As shown, the source electrode Source1 is part of the data line 141 or signal line 142 connected to the source electrode Source1. Therefore, the array substrate 100 does not need to be provided with the above-mentioned conductive connection block, and the data line 141 or signal line 142 connected to the source electrode Source1 directly overlaps the active layer A1 of the driving transistor T1.

[0108] like Figure 4 As shown, the distance between the pixel electrode 122 and the data line 141 is a first distance D1, the distance between the pixel electrode 122 and the signal line 142 is a second distance D2, the side length of the pixel electrode 122 close to the data line 141 is L1, and the side length of the pixel electrode 122 close to the signal line 142 is L2; ​​the distance between the drain Drain1 and the source Source1 in the first direction is a third distance D3, the distance between the drain Drain1 and the signal line 142 is a fourth distance D4, the size of the drain Drain1 in the second direction is L3, and the size of the source Source1 in the second direction is L4. The above L1, L2, L3, L4, D1, D2, D3, and D4 also satisfy the following formula:

[0109] E1*L1 / D1+E2*L3 / D3=E1*L2 / D2+E2*L4 / D4,

[0110] E1 is the dielectric constant of the film between the pixel electrode 122 and the data line 141 or the signal line 142 , and E2 is the dielectric constant of the film between the signal line 142 and the source electrode Source1 or the drain electrode Drain1 .

[0111] In the array substrate, the pixel electrode 122 has a first side in the first direction X (eg Figure 4 The data line 141 is provided on the left side in the first direction X, and the data line 141 is provided on the second side in the first direction X (for example Figure 4A signal line 142 is provided on the right side of the pixel electrode 122. On the first side of the pixel electrode 122, the parasitic capacitance Cpd1 between the pixel electrode 122 and the data line 141 is equal to E1*L1 / D1, and the parasitic capacitance Cpd2 between the drain electrode Drain1 and the source electrode Source1 connected to the pixel electrode 122 is equal to E2*L3 / D3. At this time, the parasitic capacitance C1 between the pixel electrode 122 and the conductive structure on the first side of the pixel electrode 122 is equal to E1*L1 / D1+E2*L3 / D3. On the second side of the pixel electrode 122, the parasitic capacitance Cpd3 between the pixel electrode 122 and the signal line 142 is equal to E1*L2 / D2, and the parasitic capacitance Cpd4 between the drain electrode Drain1 connected to the pixel electrode 122 and the signal line 142 is equal to E2*L4 / D4. At this time, the parasitic capacitance C2 between the pixel electrode 122 and the conductive structure on the second side of the pixel electrode 122 is equal to E1*L2 / D2+E2*L4 / D4. Since the ratio of (E1*L1 / D1+E2*L3 / D3) to (E1*L2 / D2+E2*L4 / D4) is in the range of 0.9-1.1, the pixel electrode in each sub-pixel unit and the first side and the second side of the pixel electrode in the first direction (for example, Figure 4 The parasitic capacitance generated by other conductive structures (on the left and right sides) is roughly equal, thereby effectively avoiding grayscale V-crosstalk and improving display quality. It should be noted that the first side and the second side of the pixel electrode are divided by the area bisector of the pixel electrode in the first direction.

[0112] Figure 5 This is an enlarged schematic diagram of a driving transistor in another array substrate provided by an embodiment of the present disclosure. Figure 5 As shown, the width of the sub-pixel unit 120 in the first direction X is Wpixel, the driving transistor T1 includes an active layer A1, the length of the channel region of the active layer A1 in the first direction X is L, the length of the channel region of the active layer A1 in the second direction Y is W, the width of the source Source1 in the first direction is Wsource, the width of the drain Drain1 in the first direction is Wdrain, the width of the data line 141 and the signal line 142 in the first direction is Wdata, and the length of the channel region of the active layer in the first direction is L, which satisfies the following formula:

[0113] Wsource+Wdrain<L<(Wpixel-2Wdata-Wdrain) / 2.

[0114] In the array substrate, by making the length of the channel region of the active layer A1 in the first direction X be L to satisfy the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wdrain) / 2, the length of the channel region of the active layer A1 in the first direction X can be reduced to L, thereby increasing the ratio W / L of the width and length of the channel of the driving transistor T1, thereby increasing the turn-on current.

[0115] For example, the width Wpixel of the sub-pixel unit 120 in the first direction X is in the range of 60-64 microns, for example, 62 microns; the length L of the channel region of the active layer A1 in the first direction X is in the range of 5-7 microns, for example, 5.79 microns; the length W of the channel region of the active layer A1 in the second direction Y can be in the range of 9-12.5 microns, for example, 11.24 microns; the width Wsource of the source electrode Source1 in the first direction can be in the range of 2-4 microns, for example, 2.57 microns; the width Wdrain of the drain electrode Drain1 in the first direction can be in the range of 2-4 microns, for example, 2.57 microns; the width Wdata of the data line 141 and the signal line 142 in the first direction can be in the range of 4-6 microns, for example, 5.4 microns. At this time, the turn-on current I on The calculation formula is:

[0116] Can be simplified to

[0117] The value range of k may be 1.05-1.20, for example, k=1.11.

[0118] Figure 6A A schematic plan view of another array substrate provided in one embodiment of the present disclosure; Figure 6B This is a schematic plan view of another array substrate provided by an embodiment of the present disclosure. Figure 6A As shown, multiple sub-pixel units 120 form n sub-pixel rows 210 arranged in a second direction Y, and the array substrate 100 includes n gate lines 130, which are arranged in a one-to-one correspondence with the n sub-pixel rows 210; the k-th gate line 130 and the k+1-th gate line 130 form a (k+1) / 2-th gate line group 1300. At this time, the array substrate 100 also includes a first vertical gate line 131 and a second vertical gate line 132, which are respectively located on both sides of the multiple sub-pixel units 120 in the first direction. Within the (k+1) / 2-th gate line group 1300, the k-th gate line 130 and the k+1-th gate line 130 are connected by the first vertical gate line 131 and the second vertical gate line 132, where k can be an odd number greater than or equal to 1, and n is a positive integer greater than k. Thus, a gate line group 1300 can have a ring structure, thereby reducing signal delay on the gate lines and improving the display quality of the array substrate.

[0119] In some examples, such as Figure 6A and Figure 6B As shown, the first vertical gate line 131 and the second vertical gate line 132 are disposed in the same layer as the data line 141 .

[0120] In some examples, such as Figure 6A and Figure 6B As shown, the first vertical gate line 131 is connected to the k-th gate line 130 through the first via connection structure H1, the first vertical gate line 131 is connected to the k+1-th gate line 130 through the second via connection structure H2, the second vertical gate line 132 is connected to the k-th gate line 130 through the third via connection structure H3, and the second vertical gate line 132 is connected to the k+1-th gate line 130 through the fourth via connection structure H4. It should be noted that the above-mentioned via connection structure generally includes a via in the insulating layer between two conductive film layers and a conductive structure located in the via, so that the two conductive film layers can be electrically connected.

[0121] In some examples, such as Figure 6B As shown, the array substrate 100 further includes at least one middle vertical gate line 135 located between two adjacent sub-pixel columns 220. Within the (k+1) / 2th gate line group 1300, the kth gate line 130 and the k+1th gate line 130 are connected via the middle vertical gate line 135. Thus, the middle vertical gate line can be used to connect two gate lines in the same gate line group, thereby ensuring electrical connection between the two gate lines in the same gate line group when a short circuit occurs in the first vertical gate line or the second vertical gate line, and reducing signal delay in the sub-pixel unit located in the middle of the array substrate.

[0122] In some examples, such as Figure 6B As shown, the middle vertical gate line 135 is provided in the same layer as the gate line 130 , so that no additional via connection structure is required, and the same metal film layer and the same patterning process can be used to form the middle vertical gate line 135 .

[0123] In some examples, such as Figure 6A and Figure 6B As shown, the data line 141 and the signal line 142 are both configured to transmit data signals, the source Source1 of some sub-pixel units 120 in the sub-pixel column 220 is connected to the data line 141, and the source Source1 of another part of the sub-pixel units 120 in the sub-pixel column 220 is connected to the signal line 142.

[0124] Figure 7A A schematic diagram of another array substrate provided in one embodiment of the present disclosure; Figure 7B This is a schematic diagram of another array substrate provided by an embodiment of the present disclosure. Figure 7AAs shown, the array substrate 100 further includes a first common electrode line 171 and a second common electrode line 172; the first common electrode line 171 extends along a first direction X, and the second common electrode line 172 extends along a second direction Y; each sub-pixel unit 120 includes a first region 120A and a second region 120B sequentially arranged along the second direction Y, the pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region 120B; the first common electrode line 171 is located between two adjacent sub-pixels 120 in the second direction Y, and between the first region 120A and the second region 120B of the same sub-pixel 120; the second common electrode line 172 is located between two adjacent sub-pixel columns 220, thereby shielding the mutual influence between the data signals of adjacent sub-pixel units 120.

[0125] In some examples, such as Figure 7A As shown, each sub-pixel unit 120 includes a first region 120A and a second region 120B arranged in sequence along the second direction Y. The pixel electrode 122 is located in the first region 120A, and the driving transistor T1 is located in the second region 120B. The width of the portion of the second common electrode line 172 located in the first region 120A is greater than the width of the portion of the second common electrode line 172 located in the second region 120B. In other words, the width of the orthographic projection of the portion of the second common electrode line located in the first region on the substrate is greater than the width of the orthographic projection of the portion of the second common electrode line located in the second region on the substrate. Therefore, when the array substrate adopts a COA (color filter on array) structure, the color filter can be arranged in the first region 120A. In this case, by setting the width of the second common electrode line 172 larger, the array substrate 100 can use the second common electrode line 172 as a black matrix to achieve a light shielding effect.

[0126] In some examples, such as Figure 7A and 7B As shown, the second common electrode line 172 includes a gate layer common electrode line 1721 and a data line layer common electrode line 1722; the gate layer common electrode line 1721 is arranged in the same layer as the gate line 130, and is connected to the data line layer common electrode line 1722 through a via hole, thereby reducing the resistance of the second common electrode line 172.

[0127] In some examples, such as Figure 7A and Figure 7BAs shown, the first common electrode line 171 is disposed on the same layer as the gate line 130. The first common electrode line 171 includes at least one first notch 1710 and first sub-common electrode lines 1712 located on both sides of the first notch 1710. The middle vertical gate line 135 passes through the first notch 1710 and is insulated from the first sub-common electrode line 1712. Thus, by providing the first notch 1710 on the first common electrode line 171, the above-mentioned middle vertical gate line 135 can be easily disposed.

[0128] In some examples, such as Figure 7A and Figure 7B As shown, two first common electrode lines 171 are arranged between the kth gate line 130 and the k+1th gate line 130 in the (k+1) / 2th gate line group 1300, and respectively include a first gap 1710. The middle vertical gate line 135 passes through the two first gaps 1710 of the two first common electrode lines 171 to connect the kth gate line 130 and the k+1th gate line 130.

[0129] In some examples, such as Figure 7A and Figure 7B As shown, in the case where the above-mentioned middle vertical gate line 135 is provided, since the middle vertical gate line 135 is provided in the same layer as the gate line 130, the second common electrode line 172 at the location of the middle vertical gate line 135 may not include the gate layer common electrode line 1721. In some examples, such as Figure 7A and Figure 7B As shown, the second common electrode line 172 is located between the lth sub-pixel column 220 and the l+1th sub-pixel column 220, the distance between the second common electrode line 172 and the signal line 142 corresponding to the lth sub-pixel column 220 is equal to the distance between the second common electrode line 172 and the data line 141 corresponding to the l+1th sub-pixel column 220, or the distance between the second common electrode line 172 and the data line 141 corresponding to the lth sub-pixel column 220 is equal to the distance between the second common electrode line 172 and the signal line 142 corresponding to the l+1th sub-pixel column 220, and l is a positive integer greater than or equal to 1.

[0130] Figure 8A An array substrate provided by an embodiment of the present disclosure Figure 7A Schematic diagram of the cross section of the AB line. Figure 8A As shown, the second common electrode line 172 includes a gate layer common electrode line 1721 and a data line layer common electrode line 1722; the gate layer common electrode line 1721 is arranged on the same layer as the gate line 130, and is connected to the data line layer common electrode line 1722 through a fifth via connection structure H5, thereby reducing the resistance of the second common electrode line 172.

[0131] In some examples, such as Figure 8A As shown, the array substrate 100 further includes a first color filter 191 and a second color filter 192. The orthographic projections of the first color filter 191 and the second color filter 192 on the base substrate 110 overlap with the orthographic projections of the second common electrode lines 172 on the base substrate 110. In this case, by setting the width of the second common electrode lines 172 to be larger, the array substrate 100 can use the second common electrode lines 172 as a black matrix to achieve a light shielding effect.

[0132] For example, the width of the portion of the second common electrode line 172 located in the first region 120A may be 12.3 micrometers, and the width of the portion of the second common electrode line 172 located in the second region 120B may be 5.5 micrometers.

[0133] For example, Figure 8A As shown, the array substrate 100 further includes a shielding electrode 195 located on the base substrate 110 and disposed in the same layer as the gate line 130. The shielding electrode 195 is used to prevent signal crosstalk between the data line 141 or the signal line 142 and the second common electrode line 172, thereby improving display quality.

[0134] For example, Figure 8A As shown, the shielding electrode 195 may be disposed between the data line 141 and the signal line 142 of the same sub-pixel unit 120 , thereby also preventing signal crosstalk between the data line 141 and the signal line 142 of the same sub-pixel unit 120 .

[0135] For example, the shielding electrode 195 can be made of a transparent conductive oxide material, such as ITO (indium tin oxide). The width of the shielding electrode 195 in the first direction X is in the range of 3-5 microns, for example, 4 microns; the thickness of the shielding electrode 195 in the direction perpendicular to the base substrate 110 is in the range of For example

[0136] In some examples, such as Figure 8A As shown, the orthographic projection of the shielding electrode 195 on the base substrate 110 is located between the orthographic projection of the second common electrode line 172 on the base substrate 110 and the orthographic projection of the data line 141 on the base substrate 110, and between the orthographic projection of the second common electrode line 172 on the base substrate 110 and the orthographic projection of the signal line 142 on the base substrate 110.

[0137] Figure 8B An array substrate provided by an embodiment of the present disclosure Figure 7A Schematic diagram of the cross section of the CD line; Figure 8BAs shown, the orthographic projection of the shielding electrode 195 on the base substrate 110 is also located between the orthographic projection of the data line 141 on the base substrate 110 and the orthographic projection of the signal line 142 on the base substrate 110 .

[0138] Figure 9 This is a schematic plan view of another array substrate provided by an embodiment of the present disclosure. Figure 9 As shown, each sub-pixel unit 120 includes a first area 120A and a second area 120B arranged in sequence along the second direction Y, the pixel electrode 122 is located in the first area 120A, and the driving transistor T1 is located in the second area 120B; the distance between the portion of the data line 141 in the first area 120A and the portion of the signal line 142 in the first area 120A in the first direction is smaller than the distance between the portion of the data line 141 in the second area 120B and the portion of the signal line 142 in the second area 120B in the first direction; the data line 141 includes a first oblique connection portion 1415, which connects the portion of the data line 141 in the first area 120A and the portion of the data line 141 in the second area 120B, and the signal line 142 includes a second oblique connection portion 1425, which connects the portion of the signal line 142 in the first area 120A and the portion of the signal line 142 in the second area 120B.

[0139] In some examples, such as Figure 9 As shown, the orthographic projection of the first oblique connection portion 1415 on the base substrate 110 overlaps with the orthographic projection of the first common electrode line 171 on the base substrate 110 , and the orthographic projection of the second oblique connection portion 1425 on the base substrate 110 overlaps with the orthographic projection of the first common electrode line 171 on the base substrate 110 .

[0140] In some examples, such as Figure 9 As shown, the orthographic projection of the via hole H7 connecting the pixel electrode 122 and the drain Drain1 of the driving transistor T1 on the base substrate 110 is located between the first oblique connection portion 1415 and the second oblique connection portion 1425 .

[0141] Figure 10 This is a schematic plan view of another array substrate provided by an embodiment of the present disclosure. Figure 10 As shown, the array substrate 100 also includes: a plurality of gate lead lines 180, each gate lead line 180 is located between two adjacent sub-pixel columns 220; each gate lead line 180 includes: a first gate lead line 181, which is arranged on the same layer as the data line 141 and is configured to connect the gate signal; a second gate lead line 182, which is arranged on the same layer as the gate line 130 and is configured to be connected to the corresponding gate line 130, and the first gate lead line 181 and the second gate lead line 182 are connected through a sixth via connection structure H6.

[0142] In some examples, such as Figure 10 As shown, the gate lead line 180 is configured to be electrically connected to the (m+1) / 2 gate line group 1300, and the second gate lead line 182 is directly connected to the mth gate line 130, where m is an odd number greater than or equal to 1; the m-1th gate line 130 includes a second notch 1302, and the three first common electrode lines 171 are arranged between the mth gate line 130 and the m-2th gate line 130, and each includes a first notch 1710, the second gate lead line 182 passes through the second notch 1302 of the m-1th gate line 130 and the three first notches 1710 of the three first common electrode lines 171, and extends to the position of the sixth via connection structure H6; the sixth via connection structure H6 is located between the m-2th gate line 130 and the first common electrode line 171, and the first gate lead line 181 is connected to the second gate lead line 182 through the sixth via connection structure H6.

[0143] At least one embodiment of the present disclosure further provides a display device. Figure 11 Schematic diagram of a display device provided by an embodiment of the present disclosure. Figure 11 As shown, the display device 400 includes any of the above-described array substrates 100. In this array substrate, the parasitic capacitance generated between the pixel electrode in each sub-pixel unit and other conductive structures on both sides of the pixel electrode in the first direction is substantially equal, thereby effectively avoiding grayscale V-crosstalk and improving display quality. Therefore, this display device can also effectively avoid grayscale V-crosstalk and improve display quality.

[0144] Figure 12 A schematic cross-sectional view of a display device provided in accordance with an embodiment of the present disclosure. Figure 12 As shown, the display device 400 further includes an opposing substrate 300 and a liquid crystal layer 350. The opposing substrate 300 is spaced apart from the array substrate 100, and the liquid crystal layer 350 is disposed between the opposing substrate 300 and the array substrate 100. The opposing substrate 300 includes a common electrode 310. The common electrode 310 is spaced apart from the pixel electrode 122 on the array substrate 100 and is configured to form an electric field to drive the liquid crystal molecules in the liquid crystal layer 350 to deflect. Figure 12 The display device shown adopts the VA mode. Of course, the embodiments of the present disclosure include but are not limited to this. The display device may also adopt the ADS mode or the IPS mode, that is, the common electrode 310 is also provided on the array substrate 100.

[0145] In some examples, the display device can be a liquid crystal display, a smart phone, a tablet computer, a television, a monitor, a smart watch, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0146] There are a few points to note:

[0147] (1) The drawings of the embodiments of the present disclosure only relate to the structures related to the embodiments of the present disclosure, and other structures may refer to conventional designs.

[0148] (2) In the absence of conflict, features in the same embodiment and different embodiments of the present disclosure may be combined with each other.

[0149] The above are merely exemplary embodiments of the present disclosure and are not intended to limit the scope of protection of the present disclosure. The scope of protection of the present disclosure is determined by the appended claims.

Claims

1. An array substrate, comprising: substrate; A plurality of sub-pixel units are located on the base substrate and arranged in an array along a first direction and a second direction to form sub-pixel rows extending in the first direction and sub-pixel columns extending in the second direction; a gate line, located on the base substrate, extending along the first direction and configured to provide a gate signal to the sub-pixel row; a data line, located on the base substrate and extending along the second direction; as well as a signal line, located on the base substrate and extending along the second direction, wherein the data line and the signal line are arranged on the same layer; The data line and the signal line are respectively located on both sides of the sub-pixel column in the first direction. Each of the sub-pixel units includes a pixel electrode, the distance between the pixel electrode and the data line is a first distance D1, the distance between the pixel electrode and the signal line is a second distance D2, the side length of the pixel electrode close to the data line is L1, and the side length of the pixel electrode close to the signal line is L2, Each of the sub-pixel units further includes a driving transistor, the driving transistor including a source and a drain, one of the data line and the signal line is connected to the source, and the drain is connected to the pixel electrode. The distance between the drain and the source in the first direction is a third distance D3, the distance between the other of the data line and the signal line and the drain is a fourth distance D4, the size of the source in the second direction is L3, and the size of the drain in the second direction is L4. Among them, the ratio range of (E1*L1 / D1+E2*L3 / D3) and (E1*L2 / D2+E2*L4 / D4) is 0.9-1.1, E1 is the dielectric constant of the film layer between the pixel electrode and the data line or the signal line, and E2 is the dielectric constant of the film layer between the signal line and the source or the drain.

2. The array substrate according to claim 1, wherein: The ratios of (E1*L1 / D1+E2*L3 / D3) and (E1*L2 / D2+E2*L4 / D4) ranged from 0.95 to 1.

05.

3. The array substrate according to claim 2, wherein: (E1*L1 / D1+E2*L3 / D3)=(E1*L2 / D2+E2*L4 / D4).

4. The array substrate according to claim 1, wherein: The data line and the signal line are both configured to transmit data signals, the sources of some of the sub-pixel units in the sub-pixel column are connected to the data line, and the sources of another part of the sub-pixel units in the sub-pixel column are connected to the signal line.

5. The array substrate according to claim 1, wherein: The data line located on one side of the jth sub-pixel column in the first direction is configured to provide a data signal to the jth sub-pixel column, and the signal line located on the other side of the jth sub-pixel column in the first direction is configured to provide a data signal to the j+1th sub-pixel column, where j is a positive integer greater than or equal to 1.

6. The array substrate according to claim 5, wherein: The signal line located on one side of the j-th sub-pixel column in the first direction and the data line located on one side of the j+1-th sub-pixel column in the first direction are configured to be connected to the same signal terminal.

7. The array substrate according to claim 1, wherein: The signal line is configured to transmit a common electrode signal.

8. The array substrate according to any one of claims 1 to 7, wherein: A connection portion between the pixel electrode and the drain electrode is located on an area bisector of the pixel electrode in the first direction.

9. The array substrate according to any one of claims 1 to 7, wherein: The side length L1 of the pixel electrode close to the data line is equal to the side length L2 of the pixel electrode close to the signal line. The first distance D1 is equal to the second distance D2.

10. The array substrate according to any one of claims 1 to 7, wherein: A dimension L3 of the source in the second direction is equal to a dimension L4 of the drain in the second direction, and the third distance D3 is equal to the fourth distance D4.

11. The array substrate according to any one of claims 1 to 7, wherein: Each of the sub-pixel units includes a first region and a second region sequentially arranged along the second direction, the pixel electrode is located in the first region, and the driving transistor is located in the second region.

12. The array substrate according to claim 11, wherein: The source electrode and the data line or the signal line connected to the source electrode are arranged relatively spaced apart. The array substrate further includes a conductive connection block, and the source electrode is connected to the data line or the signal line connected to the source electrode via the conductive connection block. The distance between the source electrode and the data line or the signal line connected to the source electrode is a fifth distance D5 , and the fifth distance D5 is equal to the fourth distance D4 .

13. The array substrate according to claim 12, wherein: The width of the sub-pixel unit in the first direction is Wpixel, the driving transistor includes an active layer, the length of the channel region of the active layer in the first direction is L, the length of the channel region of the active layer in the second direction is W, the width of the source in the first direction is Wsource, the width of the drain in the first direction is Wdrain, and the width of the data line and the signal line in the first direction is Wdata, The length L of the channel region of the active layer in the first direction satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain) / 3.

14. The array substrate according to claim 13, wherein: The length L of the channel region of the active layer in the first direction satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wsource-Wdrain) / 4.

15. The array substrate according to claim 11, wherein: The source electrode is a portion of the data line or the signal line connected to the source electrode.

16. The array substrate according to claim 15, wherein: The width of the sub-pixel unit in the first direction is Wpixel, the driving transistor includes an active layer, the length of the channel region of the active layer in the first direction is L, the length of the channel region of the active layer in the second direction is W, the width of the source in the first direction is Wsource, the width of the drain in the first direction is Wdrain, and the width of the data line and the signal line in the first direction is Wdata, The length L of the channel region of the active layer in the first direction satisfies the following formula: Wsource+Wdrain<L<(Wpixel-2Wdata-Wdrain) / 2.

17. The array substrate according to any one of claims 1 to 7, wherein: The orthographic projection of the pixel electrode on the base substrate is axisymmetric about an area bisector of the pixel electrode in the first direction.

18. The array substrate according to claim 17, wherein: The pixel electrode includes a first domain, a second domain, a third domain and a fourth domain, The first domain and the second domain are axially symmetrical about the area bisector of the pixel electrode in the first direction, and the third domain and the fourth domain are axially symmetrical about the area bisector of the pixel electrode in the first direction. The first domain and the third domain are sequentially arranged along the second direction, and the second domain and the fourth domain are sequentially arranged along the second direction.

19. The array substrate according to claim 18, wherein: The pixel electrode includes a middle portion extending along the second direction and located between the first domain and the second domain, and between the third domain and the fourth domain. The drain electrode is connected to the middle portion of the pixel electrode.

20. The array substrate according to claim 19, wherein: The pixel electrode comprises: a plurality of first slits spaced apart from each other and located in the first domain; a plurality of second slits arranged at intervals, located in the second domain; a plurality of third slits arranged at intervals and located in the third domain; and A plurality of fourth slits arranged at intervals are located in the fourth domain.

21. The array substrate according to any one of claims 1 to 7, wherein: The plurality of sub-pixel units form n sub-pixel rows arranged in the second direction, and the array substrate includes n gate lines arranged in a one-to-one correspondence with the n sub-pixel rows. The kth gate line and the k+1th gate line form a (k+1) / 2th gate line group, The array substrate further includes a first vertical gate line and a second vertical gate line, which are respectively located on both sides of the plurality of sub-pixel units in the first direction. In the (k+1) / 2th gate line group, the kth gate line and the k+1th gate line are connected via the first vertical gate line and the second vertical gate line. Wherein, k is an odd number greater than or equal to 1, and n is a positive integer greater than k.

22. The array substrate according to claim 21, wherein: The first vertical gate line and the second vertical gate line are arranged in the same layer as the data line.

23. The array substrate according to claim 22, wherein: The first vertical gate line is connected to the kth gate line through a first via connection structure, and the first vertical gate line is connected to the k+1th gate line through a second via connection structure. The second vertical gate line is connected to the kth gate line through a third via connection structure, and the second vertical gate line is connected to the k+1th gate line through a fourth via connection structure.

24. The array substrate according to claim 21, wherein: The array substrate further includes at least one middle vertical gate line located between two adjacent sub-pixel columns. In the (k+1) / 2th gate line group, the kth gate line and the (k+1)th gate line are connected via the middle vertical gate line.

25. The array substrate according to claim 24, wherein: The middle vertical grid lines are arranged in the same layer as the grid lines.

26. The array substrate according to claim 24, further comprising: a first common electrode line extending along the first direction; as well as A second common electrode line extends along the second direction, Each of the sub-pixel units includes a first area and a second area sequentially arranged along the second direction, the pixel electrode is located in the first area, the driving transistor is located in the second area, the first common electrode line is located between two adjacent sub-pixel units in the second direction, and between the first area and the second area of ​​the same sub-pixel unit. The second common electrode line is located between two adjacent sub-pixel columns.

27. The array substrate according to claim 26, wherein: The first common electrode line is provided in the same layer as the gate line, and the first common electrode line includes at least one first notch and first sub-common electrode lines located on both sides of the first notch. The middle vertical gate lines pass through the first gaps and are respectively spaced apart and insulated from the first sub-common electrode lines.

28. The array substrate according to claim 26, wherein: The second common electrode line includes a gate layer common electrode line and a data line layer common electrode line. The gate layer common electrode line is arranged in the same layer as the gate line, and the data line layer common electrode line is arranged in the same layer as the data line. The gate layer common electrode line is connected to the data line layer common electrode line through a fifth via connection structure.

29. The array substrate according to claim 27, wherein: The two first common electrode lines are arranged between the kth gate line and the k+1th gate line in the (k+1) / 2th gate line group, and respectively include the first gap, and the middle vertical gate line passes through the two first gaps of the two first common electrode lines to connect the kth gate line and the k+1th gate line.

30. The array substrate according to claim 26, wherein: A width of a portion of the second common electrode line located in the first region is greater than a width of a portion of the second common electrode line located in the second region.

31. The array substrate according to claim 26, wherein: The second common electrode line is located between the lth sub-pixel column and the l+1th sub-pixel column, the distance between the second common electrode line and the signal line corresponding to the lth sub-pixel column is equal to the distance between the second common electrode line and the data line corresponding to the l+1th sub-pixel column, or the distance between the second common electrode line and the data line corresponding to the lth sub-pixel column is equal to the distance between the second common electrode line and the signal line corresponding to the l+1th sub-pixel column, and l is a positive integer greater than or equal to 1.

32. The array substrate according to any one of claims 1 to 7, wherein: Each of the sub-pixel units includes a first region and a second region sequentially arranged along the second direction, the pixel electrode is located in the first region, and the driving transistor is located in the second region. The distance between the portion of the data line in the first area and the portion of the signal line in the first area in the first direction is smaller than the distance between the portion of the data line in the second area and the portion of the signal line in the second area in the first direction. The data line includes a first oblique connection portion connecting the portion of the data line in the first area and the portion of the data line in the second area. The signal line includes a second oblique connection portion connecting the portion of the signal line in the first area and the portion of the signal line in the second area.

33. The array substrate according to claim 26, further comprising: a plurality of gate lead lines, each of the gate lead lines being located between two adjacent sub-pixel columns; Wherein, each of the gate lead lines includes: A first gate lead line is provided on the same layer as the data line and is configured to connect a gate signal; The second gate lead line is provided in the same layer as the gate line and is configured to be connected to the corresponding gate line. The first gate lead-out line and the second gate lead-out line are connected via a sixth via connection structure.

34. The array substrate according to claim 33, wherein: The gate lead line is configured to be electrically connected to the (m+1) / 2th gate line group, the second gate lead line is directly connected to the mth gate line, and m is an odd number greater than or equal to 1. The m-1th gate line includes a second notch, three first common electrode lines are arranged between the m-th gate line and the m-2th gate line, and each includes a first notch, the second gate lead line passes through the second notch of the m-1th gate line and the three first notches of the three first common electrode lines, and extends to the position where the sixth via connection structure is located, The sixth via hole connection structure is located between the (m-2)th gate line and the first common electrode line, and the first gate lead line is connected to the second gate lead line through the sixth via hole connection structure.

35. The array substrate according to claim 26, further comprising: The shielding electrode is located on the base substrate and is provided in the same layer as the gate line.

36. The array substrate according to claim 35, wherein: The orthographic projection of the shielding electrode on the base substrate is located between the orthographic projection of the second common electrode line on the base substrate and the orthographic projection of the data line on the base substrate, and between the orthographic projection of the second common electrode line on the base substrate and the orthographic projection of the signal line on the base substrate.

37. The array substrate according to claim 36, wherein: The orthographic projection of the shielding electrode on the base substrate is also located between the orthographic projection of the data line on the base substrate and the orthographic projection of the signal line on the base substrate.

38. A display device comprising the array substrate according to any one of claims 1 to 37.

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