Memory control circuit unit, memory device, and clock signal control method

Abstract

This invention provides a memory control circuit unit, a memory storage device, and a clock signal control method. The method includes: performing an access operation on a volatile memory module via a memory interface circuit; setting the working period of a first clock signal according to the type of the access operation; and transmitting the first clock signal to the volatile memory module to execute the access operation. Therefore, the quality of the access signal to the volatile memory module can be improved.

Description

TECHNICAL FIELD

[0001] The present application relates to a memory control technique, and more particularly, to a memory control circuit unit, a memory storage device, and a clock signal control method. BACKGROUND

[0002] Dynamic random access memory (DRAM) and other volatile memories have advantages of fast access speed and small size, and thus are quite suitable for being arranged in portable electronic devices as temporary data storage media. In addition, a memory controller can be used to control and access the volatile memories.

[0003] Generally, the duty cycle of the clock signal used by the memory controller to communicate with the volatile memories is set before the memory controller is shipped from the factory (e.g., 40% or 50%, etc.), and is not dynamically adjusted for different operation states. However, in practice, the clock signal with a fixed duty cycle cannot achieve the best signal quality in various types of access operations (e.g., data write operation and data read operation) to the volatile memories. SUMMARY

[0004] The present application provides a memory control circuit unit, a memory storage device, and a clock signal control method, which can improve the access signal quality to a volatile memory module.

[0005] An exemplary embodiment of the present application provides a memory control circuit unit for controlling a volatile memory module, the memory control circuit unit comprising a memory interface circuit and a memory controller. The memory interface circuit is connected to the volatile memory module. The memory controller is connected to the memory interface circuit. The memory controller is configured to perform an access operation to the volatile memory module through the memory interface circuit. The memory interface circuit is configured to set a duty cycle of a first clock signal according to a type of the access operation. The memory interface circuit is further configured to transmit the first clock signal to the volatile memory module to perform the access operation.

[0006] In an example embodiment of the present disclosure, the operation of setting the duty cycle of the first clock signal according to the type of the access operation by the memory interface circuit includes: setting the duty cycle of the first clock signal as a first duty cycle in response to the access operation being a first type of access operation; and setting the duty cycle of the first clock signal as a second duty cycle in response to the access operation being a second type of access operation, wherein the first type of access operation is different from the second type of access operation, and the first duty cycle is different from the second duty cycle.

[0007] In an example embodiment of the present disclosure, the first type of access operation is a data read operation, and the second type of access operation is a data write operation.

[0008] In an example embodiment of the present disclosure, the memory interface circuit is further configured to store duty cycle setting data, and the operation of setting the duty cycle of the first clock signal as the second duty cycle in response to the access operation being the second type of access operation includes: switching the duty cycle of the first clock signal from the first duty cycle to the second duty cycle according to the duty cycle setting data in response to the access operation being the second type of access operation.

[0009] In an example embodiment of the present disclosure, the memory interface circuit is further configured to restore the duty cycle of the first clock signal from the second duty cycle to the first duty cycle after the second type of access operation is completed.

[0010] In an example embodiment of the present disclosure, the operation of setting the duty cycle of the first clock signal according to the type of the access operation by the memory interface circuit includes: adjusting the duty cycle of the first clock signal in response to a change in the type of the access operation.

[0011] In an example embodiment of the present disclosure, the memory interface circuit is further configured to transmit a second clock signal to the volatile memory module, and a duty cycle of the second clock signal is a preset value.

[0012] In an example embodiment of the present disclosure, the memory interface circuit includes an internal clock generator and a first clock path circuit. The first clock path circuit is connected to the memory controller, the internal clock generator, and the volatile memory module. The internal clock generator is configured to generate an internal clock signal. The first clock path circuit is configured to generate the first clock signal according to the internal clock signal. The memory controller is configured to generate an enable signal according to the type of the access operation. The first clock path circuit is further configured to adjust the duty cycle of the first clock signal according to the enable signal.

[0013] In an exemplary embodiment of the present invention, the memory interface circuit further includes a write path circuit connected to the memory controller and the internal clock generator. The write path circuit is used to generate a data signal based on the enable signal, the internal clock signal, and the internal data signal. The memory interface circuit is further used to transmit the data signal to the volatile memory module.

[0014] In an exemplary embodiment of the present invention, the memory interface circuit further includes a second clock path circuit connected to the internal clock generator and the volatile memory module. The second clock path circuit is used to generate a second clock signal based on the internal clock signal. The duty cycle of the second clock signal is a preset value. The memory interface circuit is further used to transmit the second clock signal to the volatile memory module.

[0015] An exemplary embodiment of the present invention provides a memory storage device, comprising a connection interface unit, a rewritable non-volatile memory module, a volatile memory module, and a memory control circuit unit. The connection interface unit is used to connect to a host system. The memory control circuit unit is connected to the connection interface unit, the rewritable non-volatile memory module, and the volatile memory module. The memory control circuit unit is used to: perform access operations on the volatile memory module through the memory interface circuit; set the working period of a first clock signal according to the type of the access operation; and transmit the first clock signal to the volatile memory module to perform the access operation.

[0016] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to set the working period of the first clock signal according to the type of the access operation includes: setting the working period of the first clock signal to a first working period in response to the access operation being a first type of access operation; and setting the working period of the first clock signal to a second working period in response to the access operation being a second type of access operation, wherein the first type of access operation is different from the second type of access operation, and the first working period is different from the second working period.

[0017] In an exemplary embodiment of the present invention, the memory control circuit unit is further configured to store duty cycle setting data, and in response to the access operation being a second type of access operation, the operation of setting the duty cycle of the first clock signal to the second duty cycle includes: in response to the access operation being a second type of access operation, switching the duty cycle of the first clock signal from the first duty cycle to the second duty cycle according to the duty cycle setting data.

[0018] In an exemplary embodiment of the present invention, after the second type of access operation is completed, the memory control circuit unit is further configured to restore the working cycle of the first clock signal from the second working cycle to the first working cycle.

[0019] In an exemplary embodiment of the present invention, the operation of the memory control circuit unit to set the working period of the first clock signal according to the type of the access operation includes: adjusting the working period of the first clock signal in response to a change in the type of the access operation.

[0020] In one exemplary embodiment of the present invention, the memory interface circuit is further configured to transmit a second clock signal to the volatile memory module, and the working period of the second clock signal is a preset value.

[0021] An exemplary embodiment of the present invention provides a clock signal control method for a memory control circuit unit. The clock signal control method includes: performing an access operation on a volatile memory module through a memory interface circuit; setting the working period of a first clock signal according to the type of the access operation; and transmitting the first clock signal to the volatile memory module to perform the access operation.

[0022] In an exemplary embodiment of the present invention, the step of setting the working period of the first clock signal according to the type of the access operation includes: setting the working period of the first clock signal to a first working period in response to the access operation being a first type of access operation; and setting the working period of the first clock signal to a second working period in response to the access operation being a second type of access operation, wherein the first type of access operation is different from the second type of access operation, and the first working period is different from the second working period.

[0023] In an exemplary embodiment of the present invention, the memory interface circuit is used to store duty cycle setting data, and in response to the access operation being a second type of access operation, the step of setting the duty cycle of the first clock signal to the second duty cycle includes: in response to the access operation being a second type of access operation, switching the duty cycle of the first clock signal from the first duty cycle to the second duty cycle according to the duty cycle setting data.

[0024] In an exemplary embodiment of the present invention, the step of setting the working period of the first clock signal according to the type of access operation further includes: after the second type of access operation is completed, restoring the working period of the first clock signal from the second working period to the first working period.

[0025] In an exemplary embodiment of the present invention, the step of setting the working period of the first clock signal according to the type of the access operation includes: adjusting the working period of the first clock signal in response to a change in the type of the access operation.

[0026] In an exemplary embodiment of the present invention, the clock signal control method further includes: transmitting a second clock signal to the volatile memory module, wherein the working period of the second clock signal is a preset value.

[0027] In an exemplary embodiment of the present invention, the step of setting the duty cycle of the first clock signal according to the type of the access operation includes: generating an internal clock signal; generating the first clock signal according to the internal clock signal; generating an enable signal according to the type of the access operation; and adjusting the duty cycle of the first clock signal according to the enable signal.

[0028] In an exemplary embodiment of the present invention, the clock signal control method further includes: generating a data signal based on the enable signal, the internal clock signal, and the internal data signal; and transmitting the data signal to the volatile memory module.

[0029] In an exemplary embodiment of the present invention, the clock signal control method further includes: generating a second clock signal according to the internal clock signal, wherein the working period of the second clock signal is a preset value; and transmitting the second clock signal to the volatile memory module.

[0030] Based on the above, the memory controller can perform access operations on the volatile memory module through the memory interface circuit. Specifically, the memory interface circuit can set the duty cycle of a first clock signal according to the type of access operation and transmit the first clock signal to the volatile memory module to execute the access operation. Therefore, by dynamically adjusting the duty cycle of the first clock signal according to different access operations, the quality of the access signal to the volatile memory module can be effectively improved. Attached Figure Description

[0031] Figure 1 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0032] Figure 2 This is a schematic diagram illustrating the setting of the working period of the first clock signal according to the type of access operation, as shown in an exemplary embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0034] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention;

[0035] Figure 5 This is a flowchart illustrating a clock signal control method according to an exemplary embodiment of the present invention. Detailed Implementation

[0036] Reference will now be made in detail to exemplary embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same element references are used in the drawings and description to denote the same or similar parts.

[0037] The present invention is illustrated below with several exemplary embodiments; however, the invention is not limited to these exemplary embodiments. Suitable combinations are also permitted between the exemplary embodiments. The term "connection" as used throughout this specification (including the claims) may refer to any direct or indirect means of connection. For example, if the text describes a first device connected to a second device, it should be interpreted as the first device being directly connected to the second device, or the first device being indirectly connected to the second device through other devices or some means of connection. Furthermore, the term "signal" may refer to at least one current, voltage, charge, temperature, data, or any other one or more signals.

[0038] Figure 1 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 1 The memory storage device 10 includes a memory control circuit unit 11 and a volatile memory module 12.

[0039] The memory control circuitry unit 11 can be used to control and access the volatile memory module 12. For example, the memory control circuitry unit 11 may include a central processing unit (CPU), a graphics processing unit (GPU), or other programmable general-purpose or special-purpose microprocessors, digital signal processors (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or other similar devices or combinations thereof.

[0040] The volatile memory module 12 can be used to temporarily store data. For example, the volatile memory module 12 may include a fifth-generation dual-channel synchronous dynamic random access memory (Double Data Rate 5 SDRAM) or other types of volatile memory. The memory control circuit unit 11 can store data in or read data from the volatile memory module 12. Furthermore, the number of volatile memory modules 12 can be one or more, and this invention is not limited thereto.

[0041] The memory control circuit unit 11 may include a memory interface circuit 111 and a memory controller 112. The memory interface circuit 111 is used to connect to the volatile memory module 12. For example, the memory interface circuit 111 may communicate with the volatile memory module 12 via the Peripheral Component Interconnect Express (PCI Express) standard or other types of connection interface standards.

[0042] Memory controller 112 is connected to memory interface circuit 111. Memory controller 112 can perform access operations on volatile memory module 12 through memory interface circuit 111. For example, the access operations may include data read operations and data write operations. Data read operations are used to read data from volatile memory module 12. Data write operations are used to write (i.e., store) data into volatile memory module 12. In an exemplary embodiment, memory controller 112 is also referred to as dynamic random access memory controller (SRAM controller).

[0043] The memory controller 112 can send a corresponding instruction signal CMD to the volatile memory module 12 through the memory interface circuit 111 according to the desired access operation. The volatile memory module 12 can then perform the corresponding access behavior according to the instruction signal CMD.

[0044] In one exemplary embodiment, during a data read operation, the memory controller 112 transmits an instruction signal CMD containing a read instruction sequence to the volatile memory module 12 via the memory interface circuit 111. This read instruction sequence instructs the volatile memory module 12 to read data from a specific logical address (or virtual address). The memory address corresponding to this logical address (or virtual address) is located within the volatile memory module 12. The volatile memory module 12 can read data from the specific memory address according to the instruction signal CMD containing the read instruction sequence and transmit the read data to the memory interface circuit 111 via the data signal DATA. The memory controller 112 can parse the data signal DATA through the memory interface circuit 111 to obtain the data to be read.

[0045] In one exemplary embodiment, during a data write operation, the memory controller 112 transmits an instruction signal CMD containing a write instruction sequence and a data signal DATA containing the data to be stored to the volatile memory module 12 via the memory interface circuit 111. This write instruction sequence instructs the volatile memory module 12 to write (i.e., store) the data carried by the data signal DATA to a specific logical address (or virtual address). The memory address corresponding to this logical address (or virtual address) is also located within the volatile memory module 12. The volatile memory module 12 can write the data to be stored to the specific memory address within its internal memory according to the instruction signal CMD and the data signal DATA.

[0046] In one exemplary embodiment, the memory interface circuit 111 may generate a clock signal (also referred to as a first clock signal) CK(1) and transmit the clock signal CK(1) to the volatile memory module 12. The volatile memory module 12 may perform corresponding data read and / or data write operations according to the clock signal CK(1). For example, in a data read operation, the volatile memory module 12 may transmit a data signal DATA to the memory interface circuit 111 according to the clock signal CK(1). Furthermore, in a data write operation, the volatile memory module 12 may sample the data signal DATA from the memory interface circuit 111 according to the clock signal CK(1) to obtain the data to be stored.

[0047] The memory interface circuit 111 can set the duty cycle of the clock signal CK(1) according to the type of access operation to be performed. It should be noted that the duty cycle of the clock signal CK(1) represents the ratio of the working time (e.g., the duration of a positive half-cycle or the pulse duration) of the clock signal CK(1) to the total time length within one clock cycle. For example, assuming the duty cycle of the clock signal CK(1) is 47%, it means that within one clock cycle of the clock signal CK(1), the working time (e.g., the duration of a positive half-cycle or the pulse duration) of the clock signal CK(1) accounts for 47% of the total time length. Then, the memory interface circuit 11 can transmit the clock signal CK(1) with the set duty cycle to the volatile memory module 12 to perform the corresponding access operation.

[0048] Traditionally, the clock cycle used by the memory controller to communicate with volatile memory is preset at the factory (e.g., 40% or 50%) and is not dynamically adjusted for different operating states. However, in practice, using a clock signal with a fixed cycle cannot achieve optimal signal quality for various types of access operations to volatile memory (e.g., data write and data read operations). In contrast, by setting the cycle of the clock signal CK(1) according to the type of access operation to be performed, the access signal quality of the volatile memory module 12 can be effectively improved for different types of access behaviors.

[0049] In one exemplary embodiment, in response to the desired access operation being a first type of access operation, the memory interface circuit 111 can set the duty cycle of the clock signal CK(1) to a certain duty cycle (also referred to as the first duty cycle). Subsequently, the volatile memory module 12 can perform the first type of access operation based on the clock signal CK(1) having the first duty cycle. For example, the clock signal CK(1) having the first duty cycle can be used to improve the signal quality of the volatile memory module 12 performing the first type of access operation. However, the clock signal CK(1) having the first duty cycle may not improve or may even degrade the signal quality of the volatile memory module 12 performing the second type of access operation.

[0050] In one exemplary embodiment, in response to the desired access operation being a second type of access operation, the memory interface circuit 111 can set the duty cycle of the clock signal CK(1) to another duty cycle (also referred to as the second duty cycle). The first type of access operation is different from the second type of access operation, and the first duty cycle is different from the second duty cycle. Subsequently, the volatile memory module 12 can perform the second type of access operation according to the clock signal CK(1) with the second duty cycle. For example, the clock signal CK(1) with the second duty cycle can be used to improve the signal quality of the volatile memory module 12 performing the second type of access operation. However, the clock signal CK(1) with the second duty cycle may not improve or may even degrade the signal quality of the volatile memory module 12 performing the first type of access operation.

[0051] In one exemplary embodiment, it is assumed that the first type of access operation is a data read operation and the second type of access operation is a data write operation. Therefore, the first workload can be 47% and the second workload can be 40%, but the invention is not limited thereto. In other exemplary embodiments, the first workload and / or the second workload can be adjusted according to practical needs, depending on the type of access operation.

[0052] In one exemplary embodiment, the first working cycle is a preset working cycle of the clock signal CK(1), and the memory interface circuit 111 may store working cycle setting data. For example, the working cycle setting data may include information that can be used to set and / or adjust the working cycle of the clock signal CK(1). For example, the working cycle setting data may include setting information corresponding to the second working cycle mentioned above. For example, the working cycle setting data may reflect the proportion of the second working cycle in one clock cycle (e.g., 40%). In addition, the working cycle setting data may also include setting information corresponding to the first working cycle mentioned above. For example, the working cycle setting data may also reflect the proportion of the first working cycle in one clock cycle (e.g., 47%). The memory interface circuit 111 may set (including adjust and / or switch) the working cycle of the clock signal CK(1) according to the working cycle setting data. Alternatively, in one exemplary embodiment, the working cycle setting data may also reflect the setting value of the working cycle of the clock signal CK(1) in one or more usage scenarios.

[0053] In one exemplary embodiment, in response to the desired access operation being a second type of access operation, the memory interface circuit 111 can switch the working cycle of the clock signal CK(1) from the first working cycle (i.e., the preset working cycle) to the second working cycle according to the working cycle setting data. After the second type of access operation is completed, the memory interface circuit 111 can restore the working cycle of the clock signal CK(1) from the second working cycle to the first working cycle (i.e., the preset working cycle). For example, the completion of the second type of access operation means that one or more write instruction sequences corresponding to a single data write operation have all been sent to or arrived at the volatile memory module 12. The write instruction sequence is used to instruct the volatile memory module 12 to store data. In addition, in response to the desired access operation being a first type of access operation, the memory interface circuit 111 can maintain the working cycle of the clock signal CK(1) at the first working cycle (i.e., the preset working cycle).

[0054] In one exemplary embodiment, if the type of the access operation to be performed does not change, for example, if the previously performed access operation and the next access operation are of the same type (e.g., both are type 1 or type 2 access operations), the memory interface circuit 111 may not adjust the operating period of the clock signal CK(1). However, in response to a change in the type of the access operation to be performed, for example, from a previously performed type 1 access operation to a type 2 access operation or from a previously performed type 2 access operation to a type 1 access operation, the memory interface circuit 111 may adjust the operating period of the clock signal CK(1) to improve the signal quality of the volatile memory module 12 when performing the next or current access operation.

[0055] In one exemplary embodiment, the memory interface circuit 111 may also generate a clock signal (also referred to as a second clock signal) CK(2) and transmit the clock signal CK(2) to the volatile memory module 12. The volatile memory module 12 may obtain the basic clock of the controller based on the clock signal CK(2). For example, the volatile memory module 12 may set its internal reference clock based on the clock signal CK(2). However, it should be noted that the duty cycle of the clock signal CK(2) is a preset value, unlike the clock signal CK(1), and will not change according to the type of access operation to be performed. Furthermore, the clock signals CK(1) and CK(2) may be transmitted to the volatile memory module 12 through different interfaces or signal paths.

[0056] Figure 2 This is a schematic diagram illustrating, according to an exemplary embodiment of the present invention, the duty cycle of a first clock signal is set according to the type of access operation. Please refer to... Figure 1 and Figure 2 Assuming that after time point T(1), the memory controller 112 transmits a read instruction sequence to the volatile memory module 12 via the memory interface circuit 111 to instruct the volatile memory module 12 to perform a data read operation. In response to the desired access operation being a data read operation (e.g., a first type of access operation), the memory interface circuit 111 can set (or maintain) the working period of the clock signal CK(1) to D(1) (e.g., a first working period or a preset working period). For example, the time length corresponding to D(1) can account for 47% of the total time length within one clock cycle of the clock signal CK(1), and the time length corresponding to D(1) can be adjusted according to practical needs. Therefore, after time point T(1), the read instruction sequence can be synchronously transmitted to the volatile memory module 12 with the clock signal CK(1) having a working period of D(1). The volatile memory module 12 can perform a data read operation based on the clock signal CK(1) with a working period of D(1) and the read instruction sequence, so as to improve the signal quality of the volatile memory module 12 performing the data read operation.

[0057] After performing a data read operation, after time point T(2), the memory controller 112 transmits a write instruction sequence to the volatile memory module 12 via the memory interface circuit 111 to instruct the volatile memory module 12 to perform a data write operation. In response to the change of the desired access operation to a data write operation (e.g., a second type of access operation), the memory interface circuit 111 can adjust the working cycle of the clock signal CK(1) from D(1) to D(2) (e.g., a second working cycle). For example, the time length corresponding to D(2) can account for 40% of the total time length within one clock cycle of the clock signal CK(1), and the time length corresponding to D(2) can be adjusted according to practical needs. Therefore, after time point T(2), the write instruction sequence can be synchronously transmitted to the volatile memory module 12 with the clock signal CK(1) having a working cycle of D(2). The volatile memory module 12 can perform a data write operation based on the clock signal CK(1) with a working period of D(2) and the write instruction sequence, so as to improve the signal quality of the volatile memory module 12 performing the data write operation.

[0058] After performing the data write operation, after time point T(3), the memory controller 112 again transmits the read instruction sequence to the volatile memory module 12 through the memory interface circuit 111 to instruct the volatile memory module 12 to perform the data read operation. In response to the desired access operation changing (or reverting) to a data read operation (e.g., a first type of access operation), the memory interface circuit 111 can adjust (e.g., revert) the working period of the clock signal CK(1) from D(2) to D(1) (e.g., a first working period or a preset working period). Therefore, after time point T(3), the read instruction sequence can be transmitted to the volatile memory module 12 synchronously with the clock signal CK(1) with a working period of D(1). The volatile memory module 12 can revert to performing the data read operation according to the clock signal CK(1) with a working period of D(1) and the read instruction sequence to improve the signal quality of the volatile memory module 12 performing the data read operation. In addition, in an exemplary embodiment, after the write instruction sequence is sent, the memory interface circuit 111 can also automatically adjust (e.g., revert) the working period of the clock signal CK(1) from D(2) to D(1), regardless of whether a new read instruction sequence is sent or the next data read operation is performed.

[0059] It should be noted that, in Figure 2 In the exemplary embodiments, the execution order of different types of access operations and the working cycle of the clock signal CK(1) corresponding to various types of access operations are all examples and are not intended to limit the present invention.

[0060] Figure 3This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 3 The memory storage device 30 includes a memory control circuit unit 31 and a volatile memory module 32. The memory control circuit unit 31 and the volatile memory module 32 may be identical or similar to [other components / mechanisms]. Figure 1 The memory control circuit unit 11 and the volatile memory module 12.

[0061] The memory control circuit unit 31 includes a memory interface circuit 311 and a memory controller 312. The memory interface circuit 311 and the memory controller 312 may be identical or similar to... Figure 1 The memory interface circuit 111 and the memory controller 112.

[0062] The memory interface circuit 311 includes an internal clock generator 33 and a clock path circuit (also referred to as a first clock path circuit) 34. The internal clock generator 33 generates a clock signal (also referred to as an internal clock signal) ICK. The clock path circuit 34 is connected to the memory controller 312, the internal clock generator 33, and the volatile memory module 32. The clock path circuit 34 can receive the clock signal ICK and the enable signal (also referred to as a first enable signal) WCK_EN. The clock path circuit 34 can generate a clock signal CK (1) based on the clock signal ICK and the enable signal WCK_EN.

[0063] On the other hand, the memory controller 312 can generate an enable signal (also called a second enable signal or write enable signal) WD_EN according to the type of access operation to be performed. The clock path circuit 34 can also receive the enable signal WD_EN. The clock path circuit 34 can adjust the working period of the clock signal CK(1) according to the enable signal WD_EN. Alternatively, from another perspective, the clock path circuit 34 can generate the clock signal CK(1) according to the enable signal WD_EN, the clock signal ICK, and the enable signal WCK_EN. Then, the clock path circuit 34 can transmit the clock signal CK(1) to the volatile memory module 32.

[0064] In one exemplary embodiment, at a certain point in time, in response to the intended access operation being a first type of access operation (e.g., a data read operation), the memory controller 312 may not generate an enable signal WD_EN. In this case, the clock path circuit 34 may generate a clock signal CK(1) with a first duty cycle based on the clock signal ICK and the enable signal WCK_EN. However, at another point in time, in response to the intended access operation being a second type of access operation (e.g., a data write operation), the memory controller 312 may generate an enable signal WD_EN. In this case, the clock path circuit 34 may generate a clock signal CK(1) with a second duty cycle based on the enable signal WD_EN, the clock signal ICK, and the enable signal WCK_EN.

[0065] In one exemplary embodiment, the memory interface circuit 311 further includes a clock path circuit (also referred to as a second clock path circuit) 35. The clock path circuit 35 is connected to the internal clock generator 33 and the volatile memory module 32. The clock path circuit 35 can receive a clock signal ICK and transmit a clock signal CK(2) to the volatile memory module 32 based on the clock signal ICK. It should be noted that the duty cycle of the clock signal CK(2) can be a preset value and does not change according to the type of access operation to be performed.

[0066] In one exemplary embodiment, the memory interface circuit 311 further includes a command path circuit 36. The command path circuit 36 ​​is connected to the memory controller 312, the internal clock generator 33, and the volatile memory module 32. The command path circuit 36 ​​receives instruction information CA related to the access operation to be performed from the memory controller 312 and receives a clock signal ICK from the internal clock generator 33. The command path circuit 36 ​​can transmit an instruction signal CMD to the volatile memory module 32 based on the instruction information CA and the clock signal ICK. The instruction signal CMD may carry an instruction sequence (e.g., a read instruction sequence or a write instruction sequence). The volatile memory module 32 can perform the corresponding access operation based on the instruction signal CMD.

[0067] In one exemplary embodiment, the memory interface circuit 311 further includes a write path circuit 37, a read path circuit 38, and a multiplexer circuit 39. Both the write path circuit 37 and the read path circuit 38 are connected to the memory controller 312 and the internal clock generator 33. The multiplexer circuit 39 is connected to the write path circuit 37, the read path circuit 38, and the volatile memory module 32. Both the write path circuit 37 and the read path circuit 38 can receive a clock signal ICK from the internal clock generator 33.

[0068] When the memory controller 312 performs a data write operation, the write path circuit 37 receives the enable signal WD_EN and the internal data signal WR_DQ from the memory controller 312. The write path circuit 37 generates a data signal DATA based on the enable signal WD_EN, the internal clock signal ICK, and the internal data signal WR_DQ. The data signal DATA carries information related to the data to be stored. For example, the data signal DATA may include the RDQST signal and the DQ signal. The RDQST signal can be used to transmit error correction code information related to the data to be stored. The DQ signal can be used to transmit the data to be stored. The write path circuit 37 can transmit the data signal DATA to the volatile memory module 32 via the multiplexer circuit 39. At the same time, in response to the enable signal WD_EN, the clock path circuit 34 can transmit a clock signal CK(1) with a second working cycle to the volatile memory module 32. The volatile memory module 32 can perform a data write operation based on the instruction signal CMD, the data signal DATA, and the clock signal CK(1) with a second working cycle from the memory interface circuit 311.

[0069] On the other hand, when the memory controller 312 performs a data read operation, the clock path circuit 34 does not receive the enable signal WD_EN. Therefore, the clock path circuit 34 can transmit the clock signal CK(1) with a first working cycle to the volatile memory module 32. The volatile memory module 32 can perform a data read operation based on the instruction signal CMD from the memory interface circuit 311 and the clock signal CK(1) with a first working cycle. The read path circuit 38 can receive the data signal DATA from the volatile memory module 32 through the multiplexer circuit 39. The data signal DATA from the volatile memory module 32 can carry information related to the data to be read. The read path circuit 38 can transmit the RDQS signal and the RD_DQ signal to the memory controller 312 based on the data signal DATA. For example, the RDQS signal can be used to transmit the clock signal corresponding to the RD_DQ signal. The RD_DQ signal can be used to transmit the read data.

[0070] Figure 4 This is a schematic diagram of a memory storage device according to an exemplary embodiment of the present invention. Please refer to... Figure 4 The memory storage device 40 includes a connection interface unit 41, a memory control circuit unit 42, a rewritable non-volatile memory module 43, and a volatile memory module 44.

[0071] The connection interface unit 41 is used to connect the memory storage device 40 to the host system 11. The memory storage device 40 can communicate with the host system through the connection interface unit 41. In one exemplary embodiment, the connection interface unit 41 is compatible with the Peripheral Component Interconnect Local Bus (PCI Express) standard. In one exemplary embodiment, the connection interface unit 41 may also conform to the Serial Advanced Technology Attachment (SATA) standard, the Parallel Advanced Technology Attachment (PATA) standard, the Institute of Electrical and Electronics Engineers (IEEE) 1394 standard, the Universal Serial Bus (USB) standard, the SD interface standard, the Ultra High Speed-I (UHS-I) interface standard, the Ultra High Speed-II (UHS-II) interface standard, the Memory Stick (MS) interface standard, the MCP interface standard, the MMC interface standard, the eMMC interface standard, the Universal Flash Storage (UFS) interface standard, the eMCP interface standard, the CF interface standard, the Integrated Device Electronics (IDE) standard, or other suitable standards. The connection interface unit 41 can be packaged in a chip with the memory control circuit unit 42, or the connection interface unit 41 can be disposed outside a chip containing the memory control circuit unit 42.

[0072] The memory control circuit unit 42 is connected to the connection interface unit 41 and the rewritable non-volatile memory module 43. The memory control circuit unit 42 executes multiple logic gates or control instructions implemented in hardware or firmware, and performs data writing, reading, and erasing operations in the rewritable non-volatile memory module 43 according to instructions from the host system. Furthermore, the memory control circuit unit 42 may include... Figure 1 The memory control circuit unit 11 or Figure 3 The memory control circuit unit 31.

[0073] The rewritable non-volatile memory module 43 is used to store data written by the host system. The rewritable non-volatile memory module 43 may include a single-level cell (SLC) NAND flash memory module (i.e., a flash memory module that can store 1 bit in one memory cell), a multi-level cell (MLC) NAND flash memory module (i.e., a flash memory module that can store 2 bits in one memory cell), a triple-level cell (TLC) NAND flash memory module (i.e., a flash memory module that can store 3 bits in one memory cell), a quad-level cell (QLC) NAND flash memory module (i.e., a flash memory module that can store 4 bits in one memory cell), other flash memory modules, or other memory modules with the same characteristics.

[0074] Each memory cell in the rewritable non-volatile memory module 43 stores one or more bits by changing a voltage (hereinafter also referred to as the threshold voltage). Specifically, each memory cell has a charge trapping layer between its control gate and channel. By applying a write voltage to the control gate, the amount of electrons in the charge trapping layer can be changed, thereby changing the threshold voltage of the memory cell. This operation of changing the threshold voltage of the memory cell is also called "writing data to the memory cell" or "programming the memory cell". As the threshold voltage changes, each memory cell in the rewritable non-volatile memory module 43 has multiple storage states. By applying a read voltage, it can be determined which storage state a memory cell belongs to, and thus the one or more bits stored in that memory cell can be retrieved.

[0075] In one exemplary embodiment, the memory cells of the rewritable non-volatile memory module 43 can constitute multiple physical programmable units, and these physical programmable units can constitute multiple physical erase units. Specifically, memory cells on the same word line can form one or more physical programmable units. If a memory cell can store more than two bits, then physical programmable units on the same word line can be classified into lower physical programmable units and upper physical programmable units. For example, the least significant bit (LSB) of a memory cell belongs to the lower physical programmable unit, and the most significant bit (MSB) of a memory cell belongs to the upper physical programmable unit. Generally, in MLC NAND flash memory, the write speed of the lower physical programmable unit is greater than that of the upper physical programmable unit, and / or the reliability of the lower physical programmable unit is higher than that of the upper physical programmable unit.

[0076] In one exemplary embodiment, a physical programming unit is the smallest unit of programming. That is, a physical programming unit is the smallest unit for writing data. For example, a physical programming unit can be a physical page or a physical sector. If the physical programming unit is a physical page, these physical programming units may include data bit areas and redundancy bit areas. The data bit area contains multiple physical sectors for storing user data, while the redundancy bit area is used to store system data (e.g., management data such as error correction codes). In one exemplary embodiment, the data bit area contains 32 physical sectors, and the size of one physical sector is 512 bytes (B). However, in other exemplary embodiments, the data bit area may also contain 8, 16, or more or fewer physical sectors, and the size of each physical sector may also be larger or smaller. On the other hand, a physical erase unit is the smallest unit of erasure. That is, each physical erase unit contains a minimum number of storage units to be erased together. For example, a physical erase unit is a physical block.

[0077] The volatile memory module 44 is used to volatilely store data. For example, the volatile memory module 44 may include... Figure 1 volatile memory module 12 or Figure 3 The volatile memory module 32. The memory control circuit unit 42 can also be used to access the volatile memory module 44.

[0078] Figure 5 This is a flowchart illustrating a clock signal control method according to an exemplary embodiment of the present invention. Please refer to... Figure 5In step S501, an access operation is performed on the volatile memory module through the memory interface circuit. In step S502, the working period of the first clock signal is set according to the type of the access operation. In step S503, the first clock signal is transmitted to the volatile memory module to execute the access operation.

[0079] However, Figure 5 Each step has been explained in detail above and will not be repeated here. It is worth noting that... Figure 5 Each step can be implemented as multiple pieces of code or circuits; this application does not impose any restrictions. Furthermore, Figure 5 The method can be used in conjunction with the above examples and embodiments, or it can be used alone; this case does not impose any restrictions.

[0080] In summary, the memory control circuit unit, memory storage device, and clock signal control method provided in the embodiments of the present invention can dynamically adjust the working period of the first clock signal according to different access operations, which can effectively improve the access signal quality of the volatile memory module.

[0081] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory control circuit unit, characterized in that, The memory control circuit unit, used to control the volatile memory module, includes: Memory interface circuitry for connecting to the volatile memory module; and The memory controller is connected to the memory interface circuit. The memory controller is used to perform access operations on the volatile memory module through the memory interface circuit. The memory interface circuit is used to set the duty cycle of a first clock signal according to the type of the access operation, wherein the duty cycle of the first clock signal represents the ratio of the working time in the first clock signal to the total time length within one clock cycle, and The memory interface circuit is further used to transmit the first clock signal to the volatile memory module to perform the access operation.

2. The memory control circuit unit according to claim 1, wherein the operation of the memory interface circuit in setting the working period of the first clock signal according to the type of the access operation includes: In response to the access operation being a first type of access operation, the working period of the first clock signal is set to a first working period; as well as In response to the access operation being a second type of access operation, the working period of the first clock signal is set to a second working period, wherein the first type of access operation is different from the second type of access operation, and the first working period is different from the second working period.

3. The memory control circuit unit according to claim 2, wherein the first type of access operation is a data read operation, and the second type of access operation is a data write operation.

4. The memory control circuit unit according to claim 2, wherein the memory interface circuit is further configured to store duty cycle setting data, and the operation of setting the duty cycle of the first clock signal to the second duty cycle in response to the access operation being the second type of access operation includes: In response to the access operation being the second type of access operation, the working cycle of the first clock signal is switched from the first working cycle to the second working cycle according to the working cycle setting data.

5. The memory control circuit unit according to claim 4, wherein after the second type of access operation is completed, the memory interface circuit is further configured to restore the working cycle of the first clock signal from the second working cycle to the first working cycle.

6. The memory control circuit unit according to claim 1, wherein the operation of the memory interface circuit in setting the working period of the first clock signal according to the type of the access operation includes: In response to the change in the type of the access operation, the duty cycle of the first clock signal is adjusted.

7. The memory control circuit unit according to claim 1, wherein the memory interface circuit is further configured to transmit a second clock signal to the volatile memory module, and the working period of the second clock signal is a preset value.

8. The memory control circuit unit according to claim 1, wherein the memory interface circuit comprises: Internal clock generator; as well as The first clock path circuit is connected to the memory controller, the internal clock generator, and the volatile memory module. The internal clock generator is used to generate an internal clock signal. The first clock path circuit is used to generate the first clock signal based on the internal clock signal. The memory controller is configured to generate an enable signal based on the type of the access operation, and The first clock path circuit is further configured to adjust the operating period of the first clock signal according to the enable signal.

9. The memory control circuit unit according to claim 8, wherein the memory interface circuit further comprises: The write path circuit is connected to the memory controller and the internal clock generator. The write path circuit is used to generate a data signal based on the enable signal, the internal clock signal, and the internal data signal. The memory interface circuit is further used to transmit the data signal to the volatile memory module.

10. The memory control circuit unit according to claim 8, wherein the memory interface circuit further comprises: The second clock path circuit is connected to the internal clock generator and the volatile memory module. The second clock path circuit is used to generate a second clock signal based on the internal clock signal. The operating period of the second clock signal is a preset value. The memory interface circuit is further used to transmit the second clock signal to the volatile memory module.

11. A memory storage device, characterized in that, include: A connection interface unit for connecting to the host system; Rewritable non-volatile memory module; Volatile memory module; as well as The memory control circuit unit is connected to the connection interface unit, the rewritable non-volatile memory module, and the volatile memory module. The memory control circuit unit is used to: Access operations are performed on the volatile memory module through the memory interface circuit; The duty cycle of a first clock signal is set according to the type of the access operation, wherein the duty cycle of the first clock signal represents the ratio of the working time in the first clock signal to the total time length within one clock cycle; and The first clock signal is transmitted to the volatile memory module to perform the access operation.

12. The memory storage device of claim 11, wherein the operation of the memory control circuit unit in setting the operating period of the first clock signal according to the type of the access operation includes: In response to the access operation being a first type of access operation, the working period of the first clock signal is set to a first working period; as well as In response to the access operation being a second type of access operation, the working period of the first clock signal is set to a second working period, wherein the first type of access operation is different from the second type of access operation, and the first working period is different from the second working period.

13. The memory storage device according to claim 12, wherein the first type of access operation is a data read operation, and the second type of access operation is a data write operation.

14. The memory storage device of claim 12, wherein the memory control circuit unit is further configured to store duty cycle setting data, and the operation of setting the duty cycle of the first clock signal to the second duty cycle in response to the access operation being the second type of access operation includes: In response to the access operation being the second type of access operation, the working cycle of the first clock signal is switched from the first working cycle to the second working cycle according to the working cycle setting data.

15. The memory storage device of claim 14, wherein after the second type of access operation is completed, the memory control circuit unit is further configured to restore the working cycle of the first clock signal from the second working cycle to the first working cycle.

16. The memory storage device of claim 11, wherein the operation of the memory control circuit unit in setting the operating period of the first clock signal according to the type of the access operation includes: In response to the change in the type of the access operation, the duty cycle of the first clock signal is adjusted.

17. The memory storage device according to claim 11, wherein the memory interface circuit is further configured to transmit a second clock signal to the volatile memory module, and the working period of the second clock signal is a preset value.

18. The memory storage device according to claim 11, wherein the memory interface circuit comprises: Internal clock generator; as well as The first clock path circuit is connected to the memory controller, the internal clock generator, and the volatile memory module. The internal clock generator is used to generate an internal clock signal. The first clock path circuit is used to generate the first clock signal based on the internal clock signal. The memory controller is configured to generate an enable signal based on the type of the access operation, and The first clock path circuit is further configured to adjust the operating period of the first clock signal according to the enable signal.

19. The memory storage device according to claim 18, wherein the memory interface circuit further comprises: The write path circuit is connected to the memory controller and the internal clock generator. The write path circuit is used to generate a data signal based on the enable signal, the internal clock signal, and the internal data signal. The memory interface circuit is further used to transmit the data signal to the volatile memory module.

20. The memory storage device of claim 18, wherein the memory interface circuit further comprises: The second clock path circuit is connected to the internal clock generator and the volatile memory module. The second clock path circuit is used to generate a second clock signal based on the internal clock signal. The operating period of the second clock signal is a preset value. The memory interface circuit is further used to transmit the second clock signal to the volatile memory module.

21. A clock signal control method, characterized in that, For a memory control circuit unit, the clock signal control method includes: Access operations are performed on the volatile memory module through the memory interface circuit; The duty cycle of a first clock signal is set according to the type of the access operation, wherein the duty cycle of the first clock signal represents the ratio of the working time in the first clock signal to the total time length within one clock cycle; and The first clock signal is transmitted to the volatile memory module to perform the access operation.

22. The clock signal control method according to claim 21, wherein the step of setting the working period of the first clock signal according to the type of the access operation includes: In response to the access operation being a first type of access operation, the working period of the first clock signal is set to a first working period; as well as In response to the access operation being a second type of access operation, the working period of the first clock signal is set to a second working period, wherein the first type of access operation is different from the second type of access operation, and the first working period is different from the second working period.

23. The clock signal control method according to claim 22, wherein the first type of access operation is a data read operation, and the second type of access operation is a data write operation.

24. The clock signal control method according to claim 22, wherein the memory interface circuit is used to store duty cycle setting data, and the step of setting the duty cycle of the first clock signal to the second duty cycle in response to the access operation being the second type of access operation includes: In response to the access operation being the second type of access operation, the working cycle of the first clock signal is switched from the first working cycle to the second working cycle according to the working cycle setting data.

25. The clock signal control method according to claim 24, wherein the step of setting the working period of the first clock signal according to the type of the access operation further comprises: After the second type of access operation is completed, the working cycle of the first clock signal is restored from the second working cycle to the first working cycle.

26. The clock signal control method according to claim 21, wherein the step of setting the working period of the first clock signal according to the type of the access operation includes: In response to the change in the type of the access operation, the duty cycle of the first clock signal is adjusted.

27. The clock signal control method according to claim 21, further comprising: The second clock signal is transmitted to the volatile memory module, wherein the working period of the second clock signal is a preset value.

28. The clock signal control method according to claim 21, wherein the step of setting the working period of the first clock signal according to the type of the access operation includes: Generate an internal clock signal; The first clock signal is generated based on the internal clock signal; An enable signal is generated according to the type of the access operation; as well as The operating period of the first clock signal is adjusted according to the enable signal.

29. The clock signal control method according to claim 28, further comprising: Data signals are generated based on the enable signal, the internal clock signal, and the internal data signal; as well as The data signal is transmitted to the volatile memory module.

30. The clock signal control method according to claim 28, further comprising: A second clock signal is generated based on the internal clock signal, wherein the working period of the second clock signal is a preset value; as well as The second clock signal is transmitted to the volatile memory module.

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