Branch predictor, related apparatus and branch prediction method

Abstract

Embodiments of the present application provide a branch predictor, a related device and a branch prediction method. The branch predictor comprises a base predictor and a plurality of labeled branch predictors with labels, wherein each labeled branch predictor has two storage units, a first storage unit is a single-port storage unit, used to store a high bit of a saturation counter and a flag bit in a label prediction table corresponding to the current labeled branch predictor; and a second storage unit is a dual-port storage unit, used to store a low bit of the saturation counter and a valid bit in the label prediction table corresponding to the current labeled branch predictor. Embodiments of the present application are suitable for various chips including CISC instruction set, RISC instruction set (especially RISC-V instruction set) or VLIM instruction set architecture, such as Internet of Things chips, audio / video chips, etc.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a branch predictor, related devices containing the branch predictor, and a branch prediction method. Background Technology

[0002] With the continuous development of modern processors, branch predictors are included to improve processor performance. Before the execution of conditional branch instructions (instructions that change program flow; if the branch condition is true, the next instruction to be executed will be changed) finishes, the branch predictor guesses which branch will be executed, thus improving the performance of the processor's instruction pipeline and streamlining the instruction pipeline process. However, in the operation of some branch predictors (such as hybrid branch predictors like the TAGE predictor), it is necessary to both read the historical execution results from the corresponding memory for branch prediction and write the prediction results back to memory for updates, leading to memory read / write conflicts.

[0003] To avoid this problem, existing technologies have some branch prediction schemes that can resolve read-write conflicts. For example, one approach is to decouple the front-end pipeline and the predictor, but this approach adds more circuit logic, increasing the processor's area and power consumption. Another approach is to pause the pipeline when a read-write conflict occurs, and then perform the read operation after the write operation is completed, but this approach will result in a loss of processor performance.

[0004] Therefore, how to effectively avoid read / write conflicts in the branch predictor while taking into account the processor's power consumption, area, and performance has become an urgent problem to be solved. Summary of the Invention

[0005] In view of this, embodiments of the present invention provide a branch predictor, related devices, and a branch prediction method to at least partially solve the above-mentioned problems.

[0006] According to a first aspect of the present invention, a branch predictor is provided. The branch predictor includes: a base predictor and a plurality of labeled branch predictors, wherein each labeled branch predictor has two storage units, namely a first storage unit and a second storage unit; wherein: the first storage unit is a single-port storage unit, which stores a high-order bit of a saturation counter of a preset number of bits used for branch jump prediction in the labeled prediction table corresponding to the current labeled branch predictor and a flag bit used for branch hit determination; the second storage unit is a dual-port storage unit, which stores a low-order bit of a saturation counter of a preset number of bits used for saturation update in the labeled prediction table corresponding to the current labeled branch predictor and a valid bit used to indicate the validity of an entry in the prediction table of the current labeled branch predictor.

[0007] According to a second aspect of the present invention, a processor core is provided, comprising: the branch predictor described in the first aspect.

[0008] According to a third aspect of the present invention, a pipelined processor is provided. The pipelined processor includes the branch predictor according to the first aspect; or, the processor core according to the second aspect.

[0009] According to a fourth aspect of the present invention, a chip is provided, comprising: a branch predictor according to a first aspect; or a processor core according to a second aspect; or a processor according to a third aspect.

[0010] According to a fifth aspect of the present invention, a control device is provided, comprising: a branch predictor according to a first aspect; or a processor core according to a second aspect; or a processor according to a third aspect; or a chip according to a fourth aspect.

[0011] According to a sixth aspect of the present invention, a branch prediction method is provided. The branch prediction method includes: determining whether the prediction result of a branch predictor is correct or incorrect; if the prediction is correct, for the correctly predicted marked branch predictor among the plurality of marked branch predictors of the branch predictor, a write update operation is performed on the low bits of a preset number of saturation counters in the marked prediction table stored in the second storage unit through the data write port in the dual-port of the marked branch predictor; if the prediction is incorrect, for the incorrectly predicted marked branch predictor among the plurality of marked branch predictors of the branch predictor, a write update operation is performed on the high bits of a preset number of saturation counters in the marked prediction table stored in the first storage unit through the single-port first storage unit of the marked branch predictor, using the single port of the first storage unit as the data write port; and, through the data write port in the dual-port of the second storage unit, a write update operation is performed on all the low bits of the preset number of saturation counters in the marked prediction table stored in the second storage unit.

[0012] In the embodiment of this invention, the storage unit of the marked branch predictor portion of the branch predictor is divided into two parts: a first storage unit and a second storage unit. The first storage unit stores the high-order bits of a saturation counter (preset number of bits) used for branch jump prediction in the marked prediction table corresponding to the current marked branch predictor, and a flag bit used for branch hit determination. The second storage unit stores the low-order bits of a saturation counter (preset number of bits) used for saturation update in the marked prediction table corresponding to the current marked branch predictor, and a valid bit used to indicate the validity of entries in the prediction table of the current marked branch predictor. Since the flag bit and the high-order bits of the saturation counter do not need to be updated when the branch prediction is correct, only the low-order bits and valid bits of the saturation counter need to be updated periodically. Depending on the update conditions, the portion requiring updates for each branch is separated and stored in the second storage unit. This second storage unit is implemented using a dual-port memory, while the first storage unit is implemented using a single-port memory, thereby ensuring a balance between processor performance and area. Attached Figure Description

[0013] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0014] Figure 1 This is a schematic block diagram of a processor including a branch predictor, based on an example.

[0015] Figure 2 This is a schematic structural diagram of a branch predictor according to an embodiment of the present invention.

[0016] Figure 3 for Figure 2 A schematic diagram of the storage unit configuration of the tag branch predictor in the illustrated embodiment.

[0017] Figure 4 This is a structural block diagram of a pipelined processor according to another embodiment of the present invention.

[0018] Figure 5 This is a schematic diagram illustrating the steps of a branch prediction method according to another embodiment of the present invention. Detailed Implementation

[0019] To enable those skilled in the art to better understand the technical solutions in the embodiments of the present invention, the technical solutions in the embodiments of the present invention will be clearly and thoroughly described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art should fall within the protection scope of the present invention.

[0020] The following terms are used in this document:

[0021] Conditional branch instructions: Instructions that can change the flow of a program. If the branch condition is true, the next instruction to be executed will be changed.

[0022] Branch predictor: Predicts which branch will be executed before the branch instruction finishes execution, thus improving the performance of the processor's instruction pipeline. Using a branch predictor can improve the instruction pipeline process.

[0023] TAGE Predictor: TAGE stands for Tagged Geometric History Branch Predictor. It is a hybrid predictor whose advantage is that it can simultaneously predict a branch instruction based on branch history sequences of different lengths, and evaluate the accuracy of the branch instruction under each history sequence, selecting the one with the highest historical accuracy as the final criterion for branch prediction.

[0024] Saturation counter: Also known as a bimodal predictor, it typically has a state machine with four states: strong non-select, weak non-select, weak selection, and strong selection. When a branch command is evaluated, the corresponding state machine is modified. If the branch is not adopted, the state value decreases towards "strong non-select"; if the branch is adopted, the state value increases towards "strong selection".

[0025] Processor core: Also known as the processor kernel, it is the core of the processor. A processor can have multiple (two or more) cores, but each core belongs to only one processor. The processor core is responsible for the processor's computing engine; all calculations, receiving / storing commands, and processing data are performed within the processor core.

[0026] Pipeline processor: A processor with a pipeline of multiple stages, each stage performing different tasks related to program instructions. In a standard pipeline processor, the multiple stages typically include five stages: instruction fetch, instruction decode, arithmetic fetch, execution, and write-back.

[0027] Dual-port storage unit: A storage unit that can support one read and one write operation simultaneously.

[0028] Single-port storage unit: A storage unit that can only be read or written at the same time, and cannot be read or written simultaneously.

[0029] The following describes the embodiments of the present invention based on the above terminology.

[0030] Generally, a hardware processor with one or more processing cores can execute instructions (e.g., threads of instructions) to manipulate data, such as performing arithmetic, logic, or other functions. In some examples, the executed instruction operations (e.g., threads) include one or more branch operations (e.g., branch instructions).

[0031] In some examples, branching operations are unconditional (e.g., the branch is taken each time the instruction is executed) or conditional (e.g., the direction of the branch depends on a condition). For example, the instructions to be executed after a conditional branch (e.g., a conditional jump) are not exactly known until the condition on which the branch depends is resolved. In this case, instead of waiting until the condition is resolved, the processor's branch predictor can perform branch prediction to predict whether the branch will be taken, and / or predict the target instruction (e.g., the target address) for that branch. In some examples, if the branch is predicted to be taken, the processor obtains and speculatively executes one or more instructions for the direction (e.g., the path) of the branch to be taken, such as the instruction found at the predicted branch target address. Instructions executed after branch prediction are speculative in some examples, where the processor has not yet determined whether the prediction is correct. In some examples, the processor determines the branch instruction at the back end of the pipeline circuit (e.g., in the execution, retirement, and / or write-back unit / circuit). In some examples, if a branch instruction is determined by the processor (e.g., by the backend) to be not taken, then all instructions following the currently taken branch instruction in the pipeline are flushed (e.g., discarded). In some examples, a branch predictor (e.g., a branch forecaster) learns from past behavior of branches to predict the next (e.g., the incoming) branch.

[0032] Figure 1 The processor architecture diagram illustrates a hardware processor 100 including at least one branch predictor 104(1)-104(N) and at least one (e.g., data loading compliance) branch redirection circuit 102(1)-102(N), which may be a pipelined processor. Although Figure 1Multiple branch predictors are described, with a single branch predictor available for branch prediction of computation cores 106(1)-106(N). In some examples, the branch predictors are distributed, with each computation core including its own local branch predictor 104(1)-104(N). Each local branch predictor 104(1)-104(N) may share data, such as the history of branch instructions executed by processor 100.

[0033] In some examples, N is any integer greater than two. The hardware processor 100 may be coupled to the system memory 114 to form a computing system. The operational core of the hardware processor 100 may include, for example, any one of an instruction fetch circuit, a decoder, an execution circuit, or a deactivation circuit (or other units or circuits discussed herein), as pipelined circuitry of the operational core.

[0034] Hardware processor 100 may also include register 108. As an addition or replacement for, for example, access to data in system memory 114, register 108 may include one or more general-purpose registers 110 to perform (e.g., logical or arithmetic) operations. Register 108 may include one or more architectural register files 112. In some examples, processor 100 (e.g., its branch predictor) will populate one or more registers 108 with branch history data (e.g., context data) based on instructions (e.g., branch instructions). In another embodiment, branch history may be stored in system memory 114. Branch history may include a global history of branch instructions (e.g., a history of paths taken to reach a branch instruction via currently executing program code) and an address identifier of the branch instruction (e.g., an instruction pointer value or program counter value associated with the branch instruction).

[0035] System memory 114 may include (for example, storing) one or more of the following: operating system (OS) code 116, or application code 118.

[0036] The branch reboot circuit 102 for core 106 is used to reboot incorrect predictions.

[0037] The branch predictor 104 in processor 100 can be such as a Gshare predictor, a TAGE predictor, or a Tournament branch predictor. Due to the superior performance of the TAGE predictor in processors, in various embodiments of the present invention, only the TAGE predictor is used as an example to illustrate the solutions of the embodiments of the present invention.

[0038] An exemplary structure of a TAGE predictor is as follows: Figure 2As shown, it divides the branches into historically relevant branches and historically unrelated branches, using a base prediction table and a labeled prediction table for prediction respectively. Specifically, as... Figure 2 As shown, it includes a base predictor and n (usually four) labeled branch predictors. The base predictor uses a base prediction table, illustrated as T0 in the diagram, to predict branches that are not related to the history. The labeled prediction tables for the four labeled branch predictors are illustrated as T1, T2, T3, and T4, respectively, and are used to predict branches that are related to the history.

[0039] Each entry (row) in the basic prediction table T0 includes a 2-bit saturation counter ctr. The basic predictor directly indexes the 2-bit saturation counter by XORing the program counter PC with the number of entries in T0. Each tag prediction table has a certain number of entries (rows), and the entries can be different for different tag prediction tables. However, each entry includes three parts: the saturation counter ctr indicating the jump instruction, the flag bit tag used to match the PC, and the signal valid bit u indicating that the current entry is valid.

[0040] In addition, the branch predictor also includes a history register h to record historical prediction information.

[0041] Once the branch instruction enters the predictor, it will obtain the prediction results of the above five tables. Then, based on the priority of the five tables, the result value with the highest priority will be selected as the final prediction result for this time.

[0042] based on Figure 2 An exemplary branch prediction process of the branch predictor shown includes: (1) Each branch instruction corresponds to a program counter value PC. First, the part of the PC is indexed into table T0 to obtain the value of the two-bit saturation counter; (2) The history register h is divided into 4 equal parts, and the part of the PC is hashed twice with 1 / 4, 2 / 4, 3 / 4 and 4 / 4 of the length of the history register respectively to obtain 8 result values, which are used as the index value and tag value of the 4 tables T0-T4; (3) The index value obtained in (2) is used to select the corresponding table entries (table rows) of the 4 tables T1, T2, T3 and T4, and the tag bit of the corresponding table entry is taken out and compared with the tag value obtained in (2); if they are equal, the ctr of the corresponding table entry is taken out; otherwise, the predicted value of the table is ignored; (4) More than one predicted value is obtained according to (2) and (3), and the priority order of these predicted values ​​is T4>T3>T2>T1>T0. The final predicted value is selected according to this priority.

[0043] During the branch prediction process described above, it is necessary to periodically access the memory (e.g., SRAM) of each predictor, such as reading historical execution results from memory, and at the same time, it is also necessary to write the prediction results back to memory for updates, which leads to memory read-write conflicts.

[0044] However, traditional methods of decoupling the front-end pipeline and branch predictor, or pausing the pipeline when read / write conflicts occur, either increase processor complexity and area, or cause processor performance loss.

[0045] Therefore, embodiments of the present invention provide a branch predictor, including a base predictor and multiple labeled branch predictors, such as... Figure 2 As shown in the diagram. However, unlike traditional branch predictors, in this embodiment of the invention, each tag branch predictor employs a dual-memory cell structure. That is, each tag branch predictor has two memory cells, namely a first memory cell and a second memory cell.

[0046] The first storage unit is a single-port storage unit, used to store the high-order bit of a saturation counter with a preset number of bits for branch jump prediction in the tag prediction table corresponding to the current tag branch predictor, and a flag bit for branch hit determination. The second storage unit is a dual-port storage unit, used to store the low-order bit of a saturation counter with a preset number of bits for saturation update in the tag prediction table corresponding to the current tag branch predictor, and a valid bit indicating the validity of entries in the prediction table of the current tag branch predictor. In this way, the part that needs to be updated in each tag branch predictor can be separated and implemented using dual-port memory, thereby resolving read / write conflicts while ensuring a balance between processor performance and area.

[0047] Preferably, the high-order bit of the saturation counter is the most significant bit of the saturation counter, and the low-order bits are all the bits of the saturation counter except for the most significant bit. This is particularly important in branch predictors. Figure 2 In the TAGE predictor, the highest bit of the saturation counter (in this article, "bit" in "high bit", "low bit", etc., all refer to bit bits) is used for branch jump prediction, and no update is needed if the prediction is correct.

[0048] Generally, for the saturation counter, when the mark branch predictor predicts correctly and the corresponding mark prediction tables T1 to T4 are hit, the saturation counter in the mark prediction table of the correctly predicted mark branch predictor is updated, while the saturation counters in the mark prediction tables of the other three mark branch predictors are updated when they predict incorrectly. If all mark branch predictors predict incorrectly, the 2-bit saturation counter is updated by directly indexing the number of entries in the base prediction table T0 of the PC XOR base predictor. For the valid bits, when one mark branch predicts correctly while the other mark branch predictors predict incorrectly, the valid bit corresponding to the correctly predicted mark branch predictor is incremented by 1. Furthermore, all mark branch predictors have a maximum value for their corresponding valid bits. In practical applications, updates are performed periodically based on when the valid bit corresponding to a mark branch predictor is at its maximum value.

[0049] However, in actual table updates, the branch predictor is correct most of the time, and for a saturation counter, only a portion of its bits need to be updated when correct. Therefore, in one feasible approach, after a branch prediction is completed, the branch predictor updates the data in the second memory cell based on the branch prediction result, or updates the data in both the first and second memory cells.

[0050] In this scenario, when the branch prediction is correct, the branch predictor updates the low-order bits of the saturation counter stored in the second memory unit by writing data to the data write port of the second memory unit that marks the correct prediction. In this case, because the second memory unit has both a data write port and a data read port, writing data does not affect reading data. Furthermore, since the branch predictor's prediction is correct most of the time, using a dual-port second memory unit to store the low-order bits of the saturation counter effectively ensures data operations on this memory unit while avoiding read / write conflicts, achieving an effective balance between processor area and performance.

[0051] When the branch prediction result is a branch prediction error, the branch predictor uses the single port of the first memory cell of the erroneous branch predictor as the data write port to update the high-order bits of the saturation counter stored in the first memory cell. Simultaneously, it uses the dual ports of the second memory cell of the erroneous branch predictor to update the low-order bits of the saturation counter stored in the second memory cell. In this case, the branch prediction error will result in vacancy in the prediction table, requiring updates to both the high and low orders of the saturation counter. However, because the probability of a prediction error is very low, using the single-port first memory cell to store the high-order bits of the saturation counter and using that single port as the data write port during updates will not significantly impact processor performance and effectively reduces the processor area.

[0052] Furthermore, when a branch predictor receives a data read instruction from its processor, each marked branch predictor uses a single port of the first memory unit as a data read port to provide access to the high bits of the saturation counter; and provides access to the low bits of the saturation counter through the data read port in the dual ports of the second memory unit.

[0053] In this embodiment, the storage unit of the marked branch predictor portion of the branch predictor is divided into two units: a first storage unit and a second storage unit. The first storage unit stores the high-order bits of a saturation counter (preset number of bits) used for branch jump prediction in the marked prediction table corresponding to the current marked branch predictor, and a flag bit used for branch hit determination. The second storage unit stores the low-order bits of a saturation counter (preset number of bits) used for saturation update in the marked prediction table corresponding to the current marked branch predictor, and a valid bit used to indicate the validity of entries in the prediction table of the current marked branch predictor. Since the flag bit and the high-order bits of the saturation counter do not need to be updated when the branch prediction is correct, only the low-order bits and valid bits of the saturation counter need to be updated periodically. Based on the different update conditions, the portion requiring updates for each branch is separated and stored in the second storage unit. This second storage unit is implemented using a dual-port memory, while the first storage unit is implemented using a single-port memory, thereby ensuring a balance between processor performance and area.

[0054] The following uses the TAGE predictor as an example, combined with... Figure 2 and Figure 3 The above process will be illustrated by example.

[0055] As mentioned earlier, the TAGE predictor mainly includes: a T0-level base predictor, used to provide default prediction results; and Tn-level multiple label branch predictors (…). Figure 2The example in the text has 4 entries, which contains three logical components: ① an N-bit tag (flag bit) used to mark the hit judgment of the prediction table entry (i.e., branch hit judgment); ② an M-bit counter (saturation counter) used to indicate the predicted value of the marked prediction table entry; ③ a J-bit useful counter used to indicate the usage status (whether it is valid) of the marked prediction table entry.

[0056] In this example, the three logical components mentioned above will be divided into two memory units (e.g., Figure 3 As shown), where:

[0057] ① The first storage unit (TAGE_HI) includes: the highest bit of the 1-bit counter (ctr_hi, the highest bit of the saturation counter), used as the jump prediction value, and N-bit tag (flag bits);

[0058] ② The second storage unit (TAGE_LO) includes: M-1 bit counter (ctr_lo, the low bits of the saturation counter excluding the highest bit), used for saturation updates of the counter; J bit useful counter (u, the effective bit).

[0059] The second storage unit has two ports, which can support simultaneous read and write operations.

[0060] Based on the above settings, memory access can be implemented as follows:

[0061] (1) Read operation: For a regular read operation, both the high and low storage parts of the base predictor and the mark branch predictor will be accessed, that is, both the first storage unit and the second storage unit will be accessed.

[0062] (2) Write operation: If the branch prediction is correct, only the second storage unit needs to be updated, and the first storage unit does not need to be updated. Therefore, only the second storage unit needs to be stored using a read-write operation. If the branch prediction is wrong, and a bubble occurs, both the first and second storage units will be updated.

[0063] As can be seen from the example above, since the highest bit of the tag and counter does not need to be updated when the branch prediction is correct, only the lowest bit of the counter and the useful counter need to be updated every cycle. Therefore, the storage unit is split according to the different update conditions, so that the storage unit that needs to support simultaneous read and write uses dual ports, and the others use single ports, thereby ensuring a balance between processor performance and area.

[0064] Figure 4This is a structural block diagram of a pipelined processor according to another embodiment of the present invention. The pipelined processor 500 of this embodiment includes the branch predictor described in the foregoing embodiments. It should be understood that the pipelined processor 500 can be a single-core processor or a multi-core processor.

[0065] In some examples, the cores of the pipelined processor 500 include a branch prediction phase, an instruction fetch phase, a decode phase, an allocation phase, an execution phase, and a write-back (e.g., retirement) phase. Each of these phases may include different levels of circuitry. Alternatively, the pipelined phases may be subdivided into a larger number of phases. Additional pipelined phases may also be included, such as a prefetch phase, an instruction pointer generation (IP Gen) phase, and so on.

[0066] In some examples, the pipelined processor 500 receives an instruction pointer (IP) that identifies the next instruction to be input into the processor. For example, the IP generation stage may selectively identify the instruction pointer (e.g., a memory address) that identifies the next instruction in a sequence of programs to be fetched and executed by a core (e.g., a logical core). In some examples, the pipelined processor 500 (e.g., the IP generation stage) increments the memory address of the most recently fetched instruction by a predetermined amount X (e.g., 1) each clock cycle.

[0067] However, in exceptional circumstances, or when a branch instruction is taken, the pipelined processor 500 (e.g., during the IP generation phase) may selectively identify an instruction pointer that is not the next sequential instruction in the program order. In some examples, the pipelined processor 500 (e.g., during the branch prediction phase) predicts whether a conditional branch instruction should be taken, for example, to reduce branch penalties.

[0068] Based on the processor described above, embodiments of the present invention also provide a chip that includes at least the branch predictor, processor core, or processor as described above. In practical applications, the chip can also be equipped with various hardware and controllers to implement different functions according to different actual needs, but as long as it includes the aforementioned branch predictor, processor core, or processor, it is within the protection scope of the present invention.

[0069] Furthermore, embodiments of the present invention also provide a control device, which includes at least the branch predictor, processor core, processor, or chip described above. In practical applications, this control device can be implemented as any suitable device, such as a mobile control device, an industrial control device, a desktop control device, etc.

[0070] Furthermore, embodiments of the present invention also provide a branch prediction method. Figure 5 This is a schematic diagram illustrating the steps of a branch prediction method according to another embodiment of the present invention. The branch prediction method of this embodiment includes:

[0071] S510: Determine whether the prediction result of the branch predictor is correct or incorrect; if the prediction is correct, proceed to step S520; if the prediction is incorrect, proceed to step S530.

[0072] In one feasible approach, prior to this step, the method may further include: obtaining the program counter value PC corresponding to the branch instruction; indexing and reading the saturation counter value in the base prediction table corresponding to the base predictor in the branch predictor based on the program counter value PC; and indexing and reading the saturation counter value in the marked prediction table corresponding to each marked branch predictor in the branch predictor based on the program counter value PC; and determining the prediction result based on the saturation counter value in the read base prediction table and the saturation counter value in the marked prediction table.

[0073] Specifically, reading the saturation counter value in the tag prediction table corresponding to each tag branch predictor in the tag branch predictor can be achieved as follows: for each tag branch predictor, the single port of the first storage unit is used as the data reading port to read and access the high bit of the saturation counter; and the low bit of the saturation counter is read and accessed through the data reading port in the dual ports of the second storage unit.

[0074] S520: If the prediction is correct, for the correct prediction among the multiple marked branch predictors of the branch predictor, the low bit of the saturation counter of the preset number of bits stored in the marked prediction table is written and updated through the data write port in the dual port of the second storage unit of the marked branch predictor.

[0075] S530: If the prediction is incorrect, for the marked branch predictor among the multiple marked branch predictors of the branch predictor, the high bit of the saturation counter of the preset number of bits for branch jump prediction stored in the first storage unit of the marked branch predictor is written and updated through the single port of the first storage unit of the marked branch predictor, using the single port of the first storage unit as the data write port; and, through the data write port in the dual port of the second storage unit, the low bit of the saturation counter of the preset number of bits for saturation update stored in the marked prediction table is written and updated.

[0076] When a prediction error occurs, multiple label branch predictors will also fail. In this case, the operation of step S530 will be performed for each label branch predictor.

[0077] It should be understood that the branch prediction method in this embodiment is described in a relatively simple way. For relevant details, please refer to the description in the aforementioned branch predictor section. Furthermore, it has corresponding beneficial effects, which will not be elaborated here.

[0078] Furthermore, the specific implementation of each step in the program can be found in the corresponding descriptions of the steps and units in the above method embodiments, and will not be repeated here. Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the devices and modules described above can be referred to the corresponding process descriptions in the foregoing method embodiments, and will not be repeated here.

[0079] It should be noted that, depending on the implementation needs, the various components / steps described in the embodiments of the present invention can be broken down into more components / steps, or two or more components / steps or parts of the operation of components / steps can be combined into new components / steps to achieve the purpose of the embodiments of the present invention.

[0080] The methods described above according to embodiments of the present invention can be implemented in hardware, firmware, or as software or computer code that can be stored in a recording medium (such as a CD-ROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code originally stored on a remote recording medium or a non-transitory machine-readable medium and subsequently stored on a local recording medium, downloaded via a network. Thus, the methods described herein can be processed by software stored on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It is understood that the computer, processor, microprocessor controller, or programmable hardware includes storage components (e.g., RAM, ROM, flash memory, etc.) capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods described herein. Furthermore, when a general-purpose computer accesses code used to implement the methods shown herein, the execution of the code transforms the general-purpose computer into a dedicated computer for executing the methods shown herein.

[0081] Those skilled in the art will recognize that the units and method steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementations should not be considered beyond the scope of the embodiments of the present invention.

[0082] The above embodiments are only used to illustrate the embodiments of the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the embodiments of the present invention. Therefore, all equivalent technical solutions also fall within the scope of the embodiments of the present invention, and the patent protection scope of the embodiments of the present invention should be defined by the claims.

Claims

1. A branch predictor comprising: a base predictor and a plurality of tagged branch predictors, wherein each tagged branch predictor has two storage units, the two storage units being a first storage unit and a second storage unit, the branch predictor is configured to determine a final prediction result according to prediction results of the base predictor and the plurality of tagged branch predictors; wherein: the first storage unit is a single-port storage unit, the first storage unit is configured to store a preset number of bits of a saturating counter high bit in a tagged prediction table corresponding to a current tagged branch predictor for branch jump prediction and a flag bit for branch hit judgment, and the first storage unit is configured to perform a write update operation when a branch prediction is incorrect; the second storage unit is a double-port storage unit, the second storage unit is configured to store a preset number of bits of a saturating counter low bit in a tagged prediction table corresponding to a current tagged branch predictor for saturation update and a valid bit for indicating validity of a table entry of the prediction table of the current tagged branch predictor, and the second storage unit is configured to perform a write update operation when a branch prediction is correct or incorrect.

2. The branch predictor of claim 1, wherein, The saturating counter high bit is the highest bit of the saturating counter, and the saturating counter low bit is other bits of the saturating counter except the highest bit.

3. The branch predictor of claim 1 or 2, wherein when the branch prediction result is a branch prediction correct, the branch predictor performs a write update operation on the saturating counter low bit stored in the second storage unit of the correct tagged branch predictor through a data write port of the second storage unit.

4. The branch predictor of claim 1 or 2, wherein when the branch prediction result is a branch prediction incorrect, the branch predictor takes a single port of the first storage unit of the incorrect tagged branch predictor as a data write port, performs a write update operation on the saturating counter high bit stored in the first storage unit, and performs a write update operation on the saturating counter low bit stored in the second storage unit through a data write port in a double port of the second storage unit of the incorrect tagged branch predictor.

5. The branch predictor of claim 1 or 2, wherein, When the branch predictor receives a data read instruction sent by a processor to which the branch predictor belongs, each tagged branch predictor takes the single port of the first storage unit as a data read port to provide read access to the saturating counter high bit, and provides read access to the saturating counter low bit through a data read port in the double port of the second storage unit.

6. The branch predictor of claim 1 or 2, wherein, The branch predictor is a hybrid branch predictor.

7. The branch predictor of claim 6, wherein, The hybrid branch predictor is a TAGE hybrid branch predictor.

8. A processor core, comprising: the branch predictor of any one of claims 1-7.

9. A pipelined processor, comprising: the branch predictor of any one of claims 1-7; or the processor core of claim 8.

10. A chip, comprising: the branch predictor of any one of claims 1-7; or the processor core of claim 8; or the processor of claim 9. 11.A control device, comprising: the branch predictor according to any one of claims 1-7; or, the processor core according to claim 8; or, the processor according to claim 9; or, the chip according to claim 10. 12.A branch prediction method, comprising: determining whether a prediction result of a branch predictor is correct or incorrect; if the prediction result is correct, performing a write update operation on a low bit of a preset number of saturation counters in a tag prediction table stored in a second storage unit of a tag branch predictor that is correct among a plurality of tag branch predictors of the branch predictor through a data write port in a dual port of the second storage unit; if the prediction result is incorrect, performing a write update operation on a high bit of a preset number of saturation counters in a tag prediction table stored in a single port first storage unit of a tag branch predictor that is incorrect among a plurality of tag branch predictors of the branch predictor through a single port of the first storage unit as a data write port; and performing a write update operation on a low bit of a preset number of saturation counters in a tag prediction table stored in a second storage unit through a data write port in a dual port of the second storage unit.

13. The branch prediction method of claim 12, wherein, Before the determining whether the prediction result of the branch predictor is correct or incorrect, the method further comprises: obtaining a program counter value corresponding to a branch instruction; indexing and reading a saturation counter value in a base prediction table corresponding to a base predictor in the branch predictor according to the program counter value; and indexing and reading a saturation counter value in a tag prediction table corresponding to each tag branch predictor in the branch predictor according to the program counter value; determining the prediction result according to the read saturation counter value in the base prediction table and the saturation counter value in the tag prediction table.

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