Ram mapping preprocessing method and system in fpga synthesis process

Abstract

The present application relates to the technical field of storage, in particular to a RAM mapping pre-processing method and system in FPGA synthesis process. The method comprises: obtaining state data one of read-write ports in a memory and state data two of the memory; and reducing the number of read-write ports of the memory or reducing the capacity of the memory according to the state data one or the state data two. In the present application, when the memory contained in the design is mapped, the memory is optimized or merged, so that the memory can be represented by reasonable memory elements, and the area occupied by the synthesized netlist chip is small. The memory is mapped into one or several memories, the memory resources of the FPGA are fully utilized, and the logic resources of the design are greatly reduced.

Description

Technical Field

[0001] This invention relates to the field of storage technology, and in particular to a RAM mapping preprocessing method, system, computer device, and storage medium in the FPGA synthesis process. Background Technology

[0002] With the development of modern EDA technology, programmable logic devices (FPGAs) have been widely used in digital signal processing, network communication, industrial control, and computer-related products. FPGA technology has seen increasingly widespread application in electronic design in recent years. The programmability of FPGA hardware logic, large capacity, high speed, and embedded memory arrays make it particularly suitable for applications such as high-speed data acquisition, complex control logic, and precise timing logic. Memory is an indispensable module in digital application systems.

[0003] When designing memory, users often encounter situations where there are optimizable or mergeable memory features that are not properly processed. Using inappropriate memory or logic resources to represent memory leads to complex circuitry, large chip footprint, impacted layout and routing, and increased power consumption. To address this issue, a RAM mapping preprocessing method and system for FPGA synthesis are proposed. Summary of the Invention

[0004] To address the technical problems existing in the prior art, this invention provides a RAM mapping preprocessing method, system, computer device, and storage medium in the FPGA synthesis process. The method first optimizes or merges the memory read / write ports, and then maps the memory to a more reasonable RAM, which can improve the utilization efficiency of memory elements and reduce the number of logic resources on the chip.

[0005] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0006] In a first aspect, in one embodiment of the present invention, a RAM mapping preprocessing method is provided during FPGA synthesis, the method comprising the following steps:

[0007] Obtain the status data 1 of the read / write port in the memory, and the status data 2 of the memory;

[0008] Based on state data one or state data two, reduce the number of read / write ports of the memory or reduce the memory capacity.

[0009] As a further aspect of the present invention, the status data includes the number of read / write ports and the address data of the read / write ports.

[0010] As a further embodiment of the present invention, the second state data includes the initial state data of the memory.

[0011] As a further aspect of the present invention, the step of reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0012] When the address line inputs of the read port and the write port are the same, and the output of the read port is connected to the input of the write port, then disconnect the read port and the write port of the memory.

[0013] As a further aspect of the present invention, the step of reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0014] When the clock signals and address signals of two write ports are the same, the two write ports will be merged.

[0015] As a further aspect of the present invention, when the clock signals and address signals of the two write ports are the same, the two write ports are merged, including:

[0016] The merged write port has two OR logic control terminals, one address terminal, and one input terminal;

[0017] The merged input terminal is dataIn1.

[0018] Alternatively, when the write port has the dataIn0 control signal, dataIn0 is input.

[0019] As a further aspect of the present invention, based on state data one or state data two, the number of read / write ports of the memory or the memory capacity is reduced; including:

[0020] When two read ports with the same address signal exist in a memory, these two read ports are directly merged into one read port.

[0021] As a further aspect of the present invention, the step of reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0022] When the memory has only a read port and no write port, and the initial value of the memory is half of 0 or 1, then the address bits of the read port are narrowed, the lower bits remain unchanged, and the highest address bit is used as the selection signal for the data output terminal. The data bits remain unchanged, and the output terminal selects 0 or 1 when it is 1; when the highest address bit is 0, the original data bit is selected for output, the data bits remain unchanged, and the address bits are reduced by 1.

[0023] As a further aspect of the present invention, based on state data one or state data two, the number of read / write ports of the memory or the memory capacity is reduced; including:

[0024] When the memory has only one read port, and the output bit of the read port is floating, the output bit is adapted and replaced. The address of the read port remains unchanged, the data bits are narrowed, and the initial value of the memory is removed accordingly.

[0025] Secondly, in yet another embodiment provided by the present invention, a RAM mapping preprocessing system for FPGA synthesis is provided, the system comprising: a data module and a processing module;

[0026] The data module is used to acquire the status data 1 of the read / write port in the memory, and the status data 2 of the memory;

[0027] The processing module is used to reduce the number of read / write ports of the memory or reduce the memory capacity based on state data one or state data two.

[0028] Thirdly, in another embodiment of the present invention, a computer device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor loads and executes the computer program to implement the steps of the RAM mapping preprocessing method in the FPGA synthesis process.

[0029] Fourthly, in another embodiment of the present invention, a storage medium is provided storing a computer program, which, when loaded and executed by a processor, implements the steps of the RAM mapping preprocessing method in the FPGA synthesis process.

[0030] The technical solution provided by this invention has the following beneficial effects:

[0031] The present invention provides a RAM mapping preprocessing method, system, computer device, and storage medium for FPGA synthesis. In chip or FPGA design, before mapping the included memory, the memory is optimized or merged, allowing it to be represented using appropriate memory elements, resulting in a smaller area occupied by the synthesized netlist chip. Mapping it to one or more memories fully utilizes the FPGA's memory resources and significantly reduces the design's logic resources.

[0032] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention.

[0033] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a flowchart of a RAM mapping preprocessing method in the FPGA synthesis process according to an embodiment of the present invention.

[0036] Figure 2 This is a memory read / write port structure according to an embodiment of the present invention. Figure 1 .

[0037] Figure 3 This is a diagram illustrating the memory read / write port merging process according to an embodiment of the present invention.

[0038] Figure 4 This is a block diagram of the RAM mapping preprocessing system in the FPGA synthesis process according to an embodiment of the present invention.

[0039] Figure 5 This is a diagram of the processing module in the RAM mapping preprocessing system during the FPGA synthesis process according to an embodiment of the present invention.

[0040] Figure 6 This is a structural diagram of a computer device according to an embodiment of the present invention.

[0041] The diagram includes: data module-100, processing module-200, processing sub-unit 1-201, processing sub-unit 2-202, processing sub-unit 3-203, processing sub-unit 4-204, processing sub-unit 5-205, processor-301, communication interface-302, memory-303, and communication bus-304. Detailed Implementation

[0042] Various embodiments and / or forms are described below with reference to the accompanying drawings. In the following description, numerous specific details are disclosed for illustrative purposes to provide a general understanding of more than one form. However, those skilled in the art will understand that these forms can be implemented without specific details. Specific examples of more than one form will be described in detail in the following description and drawings. However, these forms are merely illustrative and may utilize a portion of the principles and methods of various forms; the descriptions are intended to encompass all forms and their equivalents. Specifically, the terms "embodiment," "example," "form," "illustration," etc., as used in this specification can be interpreted as meaning that any form or design described may be better or more advantageous than other forms or designs.

[0043] Furthermore, various forms and characteristics can be embodied in systems that include more than one device, terminal, server, equipment, component, and / or module. It should be understood and recognized that various systems may include additional devices, terminals, servers, equipment, components, and / or modules, and / or may not include all of the multiple devices, terminals, servers, equipment, components, and modules shown in the figure.

[0044] The terms "computer program," "component," "module," and "system" used in this specification are used interchangeably, and "computer" refers to related entities, hardware, firmware, software, combinations of software and hardware, or the execution of software. For example, a component can be a process executing on a processor, a processor, an object, a thread of execution, a program, and / or a computer, but is not limited thereto. For example, it can be an application program executing on a computer device and / or all components of the computing device. More than one component can be installed within a processor and / or a thread of execution. A component can be localized within a single computer. A component can also be distributed between two or more computers.

[0045] Furthermore, these components can be executed by various computer-readable media constructed to internally store various data. These components, for example, can communicate locally and / or remotely based on signals having more than one data packet (e.g., data emitted by a component interacting with other components on a local system or a distributed system, and data transmitted to other systems via networks such as the Internet).

[0046] Hereinafter, regardless of the symbols used in the drawings, the same or similar constituent elements will be assigned the same symbols, and repeated descriptions of these elements will be omitted. Furthermore, when describing the embodiments disclosed in this specification, detailed descriptions of well-known technologies will be omitted if it is determined that such detailed descriptions would obscure the essence of the invention. Moreover, the accompanying drawings are only for easier understanding of the embodiments disclosed in this specification, and the technical concepts disclosed in this specification are not limited to the drawings.

[0047] The terminology used in this specification is for illustrative purposes and not for limiting the invention. Unless otherwise specified, the singular includes the plural. The use of “comprises” and / or “comprising” in this specification does not exclude the presence or addition of more than one other constituent element in addition to the mentioned constituent elements.

[0048] The terms "first," "second," etc., can be used to describe various elements or components, but the elements or components are not limited to those terms. The terms are used to distinguish one element or component from others. Therefore, the first element or component mentioned below can also be a second element or component within the technical concept of this invention.

[0049] Unless otherwise defined, all terms used in this specification (including technical and scientific terms) are to be understood in the sense commonly understood by one of ordinary skill in the art to which this invention pertains. Furthermore, terms defined in commonly used dictionaries should not be interpreted ideally or excessively unless specifically defined otherwise.

[0050] Furthermore, the term "or" does not mean exclusive "or" but inclusive "or". That is, unless otherwise specific or contextually ambiguous, "X uses A or B" implies one of the natural connotations. That is, "X uses A or B" can be any of the above when X uses A or B; X uses B or X uses both A and B. And it should be understood that the term "and / or" as used in this specification refers to all possible combinations of more than one of the related items listed.

[0051] In addition, the terms “information” and “data” used in this specification are generally used interchangeably.

[0052] The suffixes “module” and “section” used in the following description of the constituent elements are merely assigned or used interchangeably for the convenience of writing the specification, and they do not have any distinguishing meaning or function in themselves.

[0053] BSRAM is divided into Read-Only Memory (ROM) (with only one read port), Single-Port RAM (SP) (one read port, one write port, and the read and write port addresses are the same), Pseudo-Dual-Port RAM (SDP) (one read port, one write port, and the read and write port addresses are different), and Dual-Port RAM (DP) (two read ports, two write ports, and the read and write ports have at most two sets of address lines). Therefore, at least one read port is required during memory mapping, and the total number of read and write ports cannot exceed two. The mapping process is based on the relationship between the number and addresses of the read and write ports, and different memory types can be mapped during the mapping process. Normally, the read and write data widths are the same. However, due to the diversity of user designs, there are situations where the read and write data widths differ, or other situations that can be merged. This situation occurs when the user has one or more write ports and one or more read ports. When multiple write ports or multiple read ports exist, they need to be optimized or merged under the premise of equivalence before mapping.

[0054] When the logic or connectivity of a user-designed memory can be optimized or merged, if the optimization or merging is performed correctly, it can be mapped to a simple RAM. If the optimization or merging is not performed, a large memory will be required for mapping or there may be mapping failures, resulting in a large memory footprint after synthesis, which will affect subsequent layout and routing.

[0055] Specifically, the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0056] Please see Figure 1 , Figure 1 This is a flowchart of a RAM mapping preprocessing method in the FPGA synthesis process provided by an embodiment of the present invention, as shown below. Figure 1 As shown, the RAM mapping preprocessing method in the FPGA synthesis process includes steps S10 to S20.

[0057] S10. Obtain the status data 1 of the read / write port in the memory, and the status data 2 of the memory;

[0058] In an embodiment of the present invention, the status data one includes the number of read / write ports and the address data of the read / write ports.

[0059] In an embodiment of the present invention, the second state data includes the initial state data of the memory.

[0060] S20. Based on state data one or state data two, reduce the number of read / write ports of the memory or reduce the memory capacity.

[0061] like Figure 2 As shown, in an embodiment of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0062] When the address line inputs of the read port and write port are the same, and the output of the read port is connected to the input of the write port, then the read port and write port of the memory are disconnected. This optimizes the memory by eliminating the read and write ports, reducing the number of memory modules.

[0063] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0064] When the clock and address signals of two write ports are identical, the two write ports are merged. Specifically, the clock and address signals are used as the merged clock and address signals, and the data bus and control signals are configured as follows: Figure 3 The connection is made using this method. The number of memory write ports is reduced by 1 after optimization.

[0065] Specifically, when the clock signals and address signals of two write ports are the same, the two write ports are merged, including:

[0066] The merged write port has two OR logic control terminals, one address terminal, and one input terminal;

[0067] The merged input terminal is dataIn1.

[0068] Alternatively, when the write port has the dataIn0 control signal, dataIn0 is input.

[0069] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0070] When two read ports with the same address signal exist in a memory, these two read ports are directly merged into one read port. The output data line of the read port is connected to the outputs of the original two read ports, thus reducing the number of read ports by one.

[0071] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0072] When the memory only has read ports and no write ports, and the initial value of the memory is either all 0 or all 1 in the upper half, then the address bits of the read port are narrowed, the lower bits remain unchanged, and the highest address bit is used as the selection signal for the data output terminal. The data bits remain unchanged, and the output terminal selects 0 or 1 when the highest address bit is 1; when the highest address bit is 0, the original data bits are selected for output, the data bits remain unchanged, and the address bits are reduced by 1. After optimization, a large memory is reduced to a smaller memory.

[0073] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0074] When the memory has only one read port, and the output bit of the read port is floating, the output bit is adapted and replaced. The address of the read port remains unchanged, the data bits are narrowed, and the initial value of the memory is removed accordingly.

[0075] When the memory has only one read port and one write port, and the depth and width of the write port are the same as those of the read port, if any output bit of the read port is floating, the output bits of both the read port and the write port are adapted and replaced. In this way, the address remains unchanged, the data bits become narrower, and the initial value is removed accordingly.

[0076] This invention optimizes or merges memory according to the above method, reducing the number of read / write ports or the memory capacity. This allows previously unmappable memory to be mapped correctly, or optimizes large memory into smaller memory. This optimization or merging has a specific order, and some optimizations may require one or more calls.

[0077] In chip design or FPGA design, before mapping the memory included in the design, the memory is first optimized or merged in the manner described above, so that the memory can be represented by reasonable memory elements, and the synthesized netlist chip occupies a small area.

[0078] For synthesis tools, when the user design includes memory, the memory can be optimized or merged according to the above method, mapping it into one or more memories, making full use of the FPGA's memory resources and greatly reducing the logic resources of the design.

[0079] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0080] In one embodiment, see Figure 4 As shown, an embodiment of the present invention also provides a RAM mapping preprocessing system in the FPGA synthesis process, which includes a data module 100 and a processing module 200.

[0081] The data module 100 is used to acquire the status data one of the read / write ports in the memory and the status data two of the memory.

[0082] In an embodiment of the present invention, the status data one includes the number of read / write ports and the address data of the read / write ports.

[0083] In an embodiment of the present invention, the second state data includes the initial state data of the memory.

[0084] The processing module 200 is used to reduce the number of read / write ports of the memory or reduce the memory capacity based on state data one or state data two.

[0085] See Figure 5 As shown, the processing module 200 includes processing subunit 1 201, processing subunit 202, processing subunit 3 203, processing subunit 4 204 and processing subunit 5 205.

[0086] The processing subunit 201 is configured to disconnect the read port and write port of the memory when the address line inputs of the read port and write port are the same, and the output of the read port is connected to the input of the write port. This optimizes the read port and write port of the memory, reducing the number of memory modules.

[0087] The second processing subunit 202 is used to merge two write ports when their clock signals and address signals are the same. Specifically, the clock signal and address signal are used as the merged clock signal and address signal, and the data bus and control signals are connected as shown in the figure below. The number of memory write ports is reduced by 1 after optimization.

[0088] Specifically, when the clock signals and address signals of two write ports are the same, the two write ports are merged, including:

[0089] The merged write port has two OR logic control terminals, one address terminal, and one input terminal;

[0090] The merged input terminal is dataIn1.

[0091] Alternatively, when the write port has the dataIn0 control signal, dataIn0 is input.

[0092] The second processing subunit 203 is used to merge two read ports with the same address signal into one read port when there are two read ports with the same address signal in a memory.

[0093] The second processing subunit 204 is used when the memory only has read ports and no write ports, and when the initial value of the memory is half of 0 or half of 1, it narrows the address bits of the read port, keeps the lower bits unchanged, and uses the highest address bit as the selection signal for the data output terminal. The data bits remain unchanged, and the output terminal selects 0 or 1 when it is 1; when the highest address bit is 0, it selects the original data bit for output, keeps the data bits unchanged, and reduces the address bits by 1. After optimization, the large memory is reduced to a smaller memory.

[0094] The second processing subunit 205 is used to adapt and replace the output bits when the memory has only one read port and the output bits of the read port are floating. The address of the read port remains unchanged, the data bits are narrowed, and the initial value of the memory is removed accordingly.

[0095] When the memory has only one read port and one write port, and the depth and width of the write port are the same as those of the read port, if any output bit of the read port is floating, the output bit is adapted and replaced. The output bits of both the read port and the write port are adapted and replaced. In this way, the address remains unchanged, the data bits become narrower, and the initial value is removed accordingly.

[0096] This invention optimizes or merges memory according to the above method, reducing the number of read / write ports or the memory capacity. This allows previously unmappable memory to be mapped correctly, or optimizes large memory into smaller memory. This optimization or merging has a specific order, and some optimizations may require one or more calls.

[0097] In chip design or FPGA design, before mapping the memory included in the design, the memory is first optimized or merged in the manner described above, so that the memory can be represented by reasonable memory elements, and the synthesized netlist chip occupies a small area.

[0098] For synthesis tools, when the user design includes memory, the memory can be optimized or merged according to the above method, mapping it into one or more memories, making full use of the FPGA's memory resources and greatly reducing the logic resources of the design.

[0099] In one embodiment, see Figure 6 As shown, an embodiment of the present invention also provides a computer device, including a processor 301, a communication interface 302, a memory 303 and a communication bus 304, wherein the processor 301, the communication interface 302 and the memory 303 communicate with each other through the communication bus 304.

[0100] Memory 303 is used to store computer programs;

[0101] Processor 301, when executing a computer program stored in memory 303, executes the RAM mapping preprocessing method in the FPGA synthesis process. When executing instructions, the processor implements the steps in the above method embodiment:

[0102] S10. Obtain the status data 1 of the read / write port in the memory, and the status data 2 of the memory;

[0103] In an embodiment of the present invention, the status data one includes the number of read / write ports and the address data of the read / write ports.

[0104] In an embodiment of the present invention, the second state data includes the initial state data of the memory.

[0105] S20. Based on state data one or state data two, reduce the number of read / write ports of the memory or reduce the memory capacity.

[0106] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0107] When the address line inputs of the read port and write port are the same, and the output of the read port is connected to the input of the write port, then the read port and write port of the memory are disconnected. This optimizes the memory by eliminating the read and write ports, reducing the number of memory modules.

[0108] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0109] When the clock and address signals of two write ports are identical, the two write ports are merged. Specifically, the clock and address signals are used as the merged clock and address signals, and the data bus and control signals are connected as shown in the diagram below. The optimized memory write port count is reduced by 1.

[0110] Specifically, when the clock signals and address signals of two write ports are the same, the two write ports are merged, including:

[0111] The merged write port has two OR logic control terminals, one address terminal, and one input terminal;

[0112] The merged input terminal is dataIn1.

[0113] Alternatively, when the write port has the dataIn0 control signal, dataIn0 is input.

[0114] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0115] When two read ports with the same address signal exist in a memory, these two read ports are directly merged into one read port. The output data line of the read port is connected to the outputs of the original two read ports, thus reducing the number of read ports by one.

[0116] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0117] When the memory only has read ports and no write ports, and the initial value of the memory is either all 0 or all 1 in the upper half, then the address bits of the read port are narrowed, the lower bits remain unchanged, and the highest address bit is used as the selection signal for the data output terminal. The data bits remain unchanged, and the output terminal selects 0 or 1 when the highest address bit is 1; when the highest address bit is 0, the original data bits are selected for output, the data bits remain unchanged, and the address bits are reduced by 1. After optimization, a large memory is reduced to a smaller memory.

[0118] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0119] When the memory has only one read port, and the output bit of the read port is floating, the output bit is adapted and replaced. The address of the read port remains unchanged, the data bits are narrowed, and the initial value of the memory is removed accordingly.

[0120] When the memory has only one read port and one write port, and the depth and width of the write port are the same as those of the read port, if any output bit of the read port is floating, the output bits of both the read port and the write port are adapted and replaced. In this way, the address remains unchanged, the data bits become narrower, and the initial value is removed accordingly.

[0121] This invention optimizes or merges memory according to the above method, reducing the number of read / write ports or the memory capacity. This allows previously unmappable memory to be mapped correctly, or optimizes large memory into smaller memory. This optimization or merging has a specific order, and some optimizations may require one or more calls.

[0122] In chip design or FPGA design, before mapping the memory included in the design, the memory is first optimized or merged in the manner described above, so that the memory can be represented by reasonable memory elements, and the synthesized netlist chip occupies a small area.

[0123] For synthesis tools, when the user design includes memory, the memory can be optimized or merged according to the above method, mapping it into one or more memories, making full use of the FPGA's memory resources and greatly reducing the logic resources of the design.

[0124] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0125] The communication interface is used for communication between the aforementioned terminal and other devices.

[0126] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0127] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0128] The computer equipment includes user equipment and network equipment. The user equipment includes, but is not limited to, computers, smartphones, and PDAs; the network equipment includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing, which is a type of distributed computing consisting of a super virtual computer composed of a group of loosely coupled computers. The computer equipment can operate independently to implement the present invention, or it can connect to a network and interact with other computer equipment within the network to implement the present invention. The network in which the computer equipment is located includes, but is not limited to, the Internet, wide area networks (WANs), metropolitan area networks (MANs), local area networks (LANs), and VPN networks.

[0129] The computer equipment includes user equipment and network equipment. The user equipment includes, but is not limited to, computers, smartphones, and PDAs; the network equipment includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing, which is a type of distributed computing consisting of a super virtual computer composed of a group of loosely coupled computers. The computer equipment can operate independently to implement the present invention, or it can connect to a network and interact with other computer equipment within the network to implement the present invention. The network in which the computer equipment is located includes, but is not limited to, the Internet, wide area networks (WANs), metropolitan area networks (MANs), local area networks (LANs), and VPN networks.

[0130] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0131] In one embodiment of the present invention, a storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps in the above method embodiments:

[0132] S10. Obtain the status data 1 of the read / write port in the memory, and the status data 2 of the memory;

[0133] In an embodiment of the present invention, the status data one includes the number of read / write ports and the address data of the read / write ports.

[0134] In an embodiment of the present invention, the second state data includes the initial state data of the memory.

[0135] S20. Based on state data one or state data two, reduce the number of read / write ports of the memory or reduce the memory capacity.

[0136] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0137] When the address line inputs of the read port and write port are the same, and the output of the read port is connected to the input of the write port, then the read port and write port of the memory are disconnected. This optimizes the memory by eliminating the read and write ports, reducing the number of memory modules.

[0138] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0139] When the clock and address signals of two write ports are identical, the two write ports are merged. Specifically, the clock and address signals are used as the merged clock and address signals, and the data bus and control signals are connected as shown in the diagram below. The optimized memory write port count is reduced by 1.

[0140] Specifically, when the clock signals and address signals of two write ports are the same, the two write ports are merged, including:

[0141] The merged write port has two OR logic control terminals, one address terminal, and one input terminal;

[0142] The merged input terminal is dataIn1.

[0143] Alternatively, when the write port has the dataIn0 control signal, dataIn0 is input.

[0144] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0145] When two read ports with the same address signal exist in a memory, these two read ports are directly merged into one read port. The output data line of the read port is connected to the outputs of the original two read ports, thus reducing the number of read ports by one.

[0146] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0147] When the memory only has read ports and no write ports, and the initial value of the memory is either all 0 or all 1 in the upper half, then the address bits of the read port are narrowed, the lower bits remain unchanged, and the highest address bit is used as the selection signal for the data output terminal. The data bits remain unchanged, and the output terminal selects 0 or 1 when the highest address bit is 1; when the highest address bit is 0, the original data bits are selected for output, the data bits remain unchanged, and the address bits are reduced by 1. After optimization, a large memory is reduced to a smaller memory.

[0148] In embodiments of the present invention, reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes:

[0149] When the memory has only one read port, and the output bit of the read port is floating, the output bit is adapted and replaced. The address of the read port remains unchanged, the data bits are narrowed, and the initial value of the memory is removed accordingly.

[0150] When the memory has only one read port and one write port, and the depth and width of the write port are the same as those of the read port, if any output bit of the read port is floating, the output bits of both the read port and the write port are adapted and replaced. In this way, the address remains unchanged, the data bits become narrower, and the initial value is removed accordingly.

[0151] This invention optimizes or merges memory according to the above method, reducing the number of read / write ports or the memory capacity. This allows previously unmappable memory to be mapped correctly, or optimizes large memory into smaller memory. This optimization or merging has a specific order, and some optimizations may require one or more calls.

[0152] In chip design or FPGA design, before mapping the memory included in the design, the memory is first optimized or merged in the manner described above, so that the memory can be represented by reasonable memory elements, and the synthesized netlist chip occupies a small area.

[0153] For synthesis tools, when the user design includes memory, the memory can be optimized or merged according to the above method, mapping it into one or more memories, making full use of the FPGA's memory resources and greatly reducing the logic resources of the design.

[0154] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Furthermore, any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include at least one of non-volatile and volatile memory.

[0155] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0156] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A RAM mapping preprocessing method in FPGA synthesis, characterized in that, The method includes: Obtain the status data 1 of the read / write port in the memory, and the status data 2 of the memory; Based on status data one or status data two, reduce the number of read / write ports of the memory or reduce the memory capacity, including: When the memory has only a read port and no write port, and the initial value of the memory is half of 0 or 1, then the address bits of the read port are narrowed, the lower bits remain unchanged, and the highest address bit is used as the selection signal for the data output terminal. The data bits remain unchanged, and the output terminal selects 0 or 1 when it is 1; when the highest address bit is 0, the original data bit is selected for output, the data bits remain unchanged, and the address bits are reduced by 1. When the memory has only one read port, and the output bits of the read port are floating, the output bits are adapted and replaced. The address of the read port remains unchanged, the data bits are narrowed, and the initial value of the memory is removed accordingly. When the memory has only one read port and one write port, and the depth and width of the write port are the same as those of the read port, and the output bits of the read port are floating, the output bits of both the read port and the write port are adapted and replaced.

2. The RAM mapping preprocessing method in the FPGA synthesis process as described in claim 1, characterized in that, The status data includes the number of read / write ports and the address data of the read / write ports.

3. The RAM mapping preprocessing method in the FPGA synthesis process as described in claim 2, characterized in that, The second state data includes the initial state data of the memory.

4. The RAM mapping preprocessing method in the FPGA synthesis process as described in claim 1, characterized in that, The number of read / write ports or the memory capacity are reduced based on state data one or state data two. include: When the address line inputs of the read port and the write port are the same, and the output of the read port is connected to the input of the write port, then disconnect the read port and the write port of the memory.

5. The RAM mapping preprocessing method in the FPGA synthesis process as described in claim 1, characterized in that, The step of reducing the number of read / write ports or reducing the memory capacity based on state data one or state data two includes: When the clock signals and address signals of two write ports are the same, the two write ports will be merged.

6. The RAM mapping preprocessing method in the FPGA synthesis process as described in claim 5, characterized in that, When the clock signals and address signals of two write ports are the same, the two write ports will be merged, including: The merged write port has two OR logic control terminals, one address terminal, and one input terminal; The merged input is dataIn1. Alternatively, when the write port has the dataIn0 control signal, dataIn0 is input.

7. The RAM mapping preprocessing method in the FPGA synthesis process as described in claim 1, characterized in that, Based on state data one or state data two, reduce the number of read / write ports of the memory or reduce the memory capacity; include: When two read ports with the same address signal exist in a memory, these two read ports are directly merged into one read port.

8. A RAM mapping preprocessing system in the FPGA synthesis process, characterized in that, The system includes: a data module and a processing module; The data module is used to acquire the status data one of the read / write ports in the memory, and the status data two of the memory; The processing module is used to reduce the number of read / write ports of the memory or reduce the memory capacity based on state data one or state data two. The data module is further configured to: when the memory has only a read port and no write port, and the upper half of the memory's initial value is either all 0 or all 1, narrow the address bits of the read port, keep the lower bits unchanged, use the highest address bit as the selection signal for the data output terminal, keep the data bits unchanged, and select 0 or 1 when the highest address bit is 1; when the highest address bit is 0, select the original data bit for output, keep the data bits unchanged, and decrease the address bits by 1; when the memory has only one read port, and some output bits of the read port are floating, adapt and replace the output bits, keep the read port's address unchanged, narrow the data bits, and remove the corresponding initial value of the memory; when the memory has only one read port and one write port, and the depth and width of the write port are the same as the read port, and some output bits of the read port are floating, adapt and replace the output bits of both the read port and the write port.

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