A convolution calculation circuit and a calculation method based on resistive random access memory

Abstract

The application relates to a convolution calculation circuit and a calculation method based on a resistive switching memory, wherein the calculation circuit comprises a memory calculation array, a digital-to-analog converter, an analog-to-digital converter, a word / bit line decoder and a controller; the memory calculation array is connected with the digital-to-analog converter in the bit line direction and connected with the analog-to-digital converter in the word line direction; the input of the digital-to-analog converter is a convolution input digital signal, and the output is connected to the memory calculation array; the input of the analog-to-digital converter is connected to the memory calculation array, and the output is a convolution output digital signal; the output of the word / bit line decoder is connected to the memory calculation array and used for selecting part or all of the memory calculation array; and the output of the controller is respectively connected to the memory calculation array, the digital-to-analog converter and the analog-to-digital converter and used for generating a control signal for realizing convolution calculation. The application can greatly improve the efficiency of convolution calculation.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a convolution calculation circuit and calculation method based on resistive random access memory. Background Technology

[0002] Convolutional computation has wide applications in image processing, such as image denoising, feature extraction, smoothing, filtering, edge detection, and image enhancement. In particular, convolutional operations play a crucial role in Convolutional Neural Networks (CNNs), and the convolution operation on the input image is fundamental to realizing the specific functions of CNNs. Traditional methods for implementing convolutional operations mainly utilize CMOS digital circuits such as CPUs, GPUs, FPGAs, and ASICs through software implementation. This approach, based on the von Neumann architecture, separates the core computation and storage components, making it difficult to perform large-scale parallel convolutional operations. In the context of the rapid development of big data and neural network algorithms, traditional software-based convolutional computation methods are increasingly unable to meet the growing demands of technological advancements in terms of computational speed, energy consumption, and hardware cost. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a convolution calculation circuit and calculation method based on resistive random access memory, which can significantly improve the efficiency of convolution calculation.

[0004] The technical solution adopted by this invention to solve its technical problem is as follows: A convolution calculation circuit based on resistive random access memory (RRAM) is provided, comprising: a memory array, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a word / bit line decoder, and a controller; the memory array is connected to the DAC in the bit line direction and to the ADC in the word line direction; the input of the DAC is a convolution input digital signal, and its output is connected to the memory array; the input of the ADC is connected to the memory array, and its output is a convolution output digital signal; the output of the word / bit line decoder is connected to the memory array and is used to select part or all of the memory array; the output of the controller is connected to the memory array, the DAC, and the ADC respectively, and is used to generate control signals for implementing convolution calculation.

[0005] The in-memory array includes local in-memory arrays in the M row bitline direction and the N column word line direction, where M represents the maximum adjustable number of parallel convolution computations and N represents the maximum adjustable number of convolution kernel elements. The local in-memory array includes non-volatile memory columns and logic switch units. The non-volatile memory columns are used to store parameters. The logic switch units are used to connect to the logic switch units of other local in-memory arrays in the word line direction via the first bus Vpavg and the second bus Vnavg, and to the non-volatile memory columns via the first bit line BLP and the second bit line BLN.

[0006] The non-volatile memory array includes C groups of memory cells, which are connected to other local memory arrays in the bit line direction via the first bit line (BLP) and the second bit line (BLN). Each memory cell includes two resistive random access memory (RRAM) devices and two gating devices. One end of one RRAM device is connected to the first bit line (BLP), and the other end is grounded through a gating device. One end of the other RRAM device is connected to the second bit line (BLN), and the other end is grounded through another gating device. The RRAM devices are used to store the differential signal of the convolution kernel weight information, and the gating devices are used to select the RRAM devices.

[0007] The resistive switching memory device is at least one of oxide-based resistive switching memory (RRAM), ferroelectric memory (FRAM), phase change memory (PCM), and magnetoresistive memory (MRAM).

[0008] The gating device is at least one of CMOS, BJT, Diode, and oxide-based switching devices.

[0009] The logic switching unit includes two NMOS transistors, two PMOS transistors, and four switching devices. The two NMOS transistors are controlled by a reset signal to reset the voltage of the first bit line BLP and the second bit line BLN. The two PMOS transistors are controlled by a pre-charge signal to charge the first bit line BLP and the second bit line BLN. The four switching devices are used to connect the first bit line BLP and the second bit line BLN to the first bus Vpavg and the second bus Vnavg to achieve charge balance of the bit lines in the word line direction.

[0010] The logic switching unit also converts the convolution input digital signal into a voltage signal on the first bit line BLP or the second bit line BLN via a global bit line.

[0011] The analog-to-digital converter is used to convert the voltage difference between the first bus Vpavg and the second bus Vnavg into a convolutional output digital signal.

[0012] The technical solution adopted by this invention to solve its technical problem is: to provide a convolution calculation method based on resistive random access memory, using the above-mentioned convolution calculation circuit based on resistive random access memory, including the following steps:

[0013] Based on the configuration information, part or all of the memory array is selected through the word / bit line decoder;

[0014] Read the weight parameters from the selected memory array;

[0015] Turn on the NMOS transistor controlled by the reset signal to reset the voltage of the first bit line BLP and the second bit line BLN in the selected memory array to zero;

[0016] According to the weight parameters, the PMOS transistor controlled by the precharge signal is turned on, and the digital-to-analog converter converts the convolution input digital signal into an analog voltage signal on the first bit line BLP or the second bit line BLN in the selected memory array.

[0017] According to the weighting parameters, the switching device is turned on, allowing the charge on the first bit line BLP and the second bit line BLN in the word line direction to be redistributed and balanced.

[0018] The analog-to-digital converter converts the analog voltage difference between the first bus Vpavg and the second bus Vnavg into a convolutional output digital signal.

[0019] When the analog-to-digital converter converts the analog voltage difference between the first bus Vpavg and the second bus Vnavg into a convolutional output digital signal, the sign of the convolutional output digital signal depends on the result of the first comparison. If the result of the first comparison is positive, the sign is positive; if the result of the first comparison is negative, the sign is negative.

[0020] Beneficial effects

[0021] By adopting the above-mentioned technical solution, this invention has the following advantages and positive effects compared with the prior art: This invention utilizes resistive random access memory (RRAM) to store the weight parameter information of convolution. Its non-volatile nature can protect important parameters from being lost due to power failure. The digital input information is converted into the voltage on the corresponding bit line in the memory array by a digital-to-analog converter (DAC). The simulation result of the convolution calculation is obtained through charge balancing. Finally, the final result is output through an analog-to-digital converter (ADC). This realizes the integration of computation and storage, which not only improves the calculation speed but also reduces hardware costs and energy consumption. At the same time, the parallel expansion is carried out by utilizing the large-scale integration feature of RRAM, which greatly improves the efficiency of convolution calculation. Attached Figure Description

[0022] Figure 1 This is a schematic diagram of a convolution calculation circuit based on resistive random access memory according to an embodiment of the present invention;

[0023] Figure 2 This is a schematic diagram of a local storage array in an embodiment of the present invention;

[0024] Figure 3 This is a signal timing diagram of the convolution calculation method based on resistive random access memory in an embodiment of the present invention. Detailed Implementation

[0025] The present invention will be further illustrated below with reference to specific embodiments. It should be understood that these embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Furthermore, it should be understood that after reading the teachings of this invention, those skilled in the art can make various alterations or modifications to the invention, and these equivalent forms also fall within the scope defined by the appended claims.

[0026] Embodiments of the present invention relate to a convolution calculation circuit based on resistive random access memory, such as... Figure 1 As shown, the system includes: a memory-in-memory array, a digital-to-analog converter (DAC), an analog-to-digital converter (ADC), a word / bit-line decoder, and a controller. The memory-in-memory array is connected to the DAC in the bit-line direction and to the ADC in the word-line direction. The DAC receives a convolution input digital signal as input and its output is connected to the memory-in-memory array. The ADC receives a convolution output digital signal as input and its output is connected to the memory-in-memory array. The word / bit-line decoder's output is connected to the memory-in-memory array and is used to select part or all of the memory-in-memory array. The controller's output is connected to the memory-in-memory array, the DAC, and the ADC, respectively, and is used to generate control signals for implementing convolution calculations.

[0027] In-memory arrays consist of M row-level and N column-level local arrays (LocalArrays), where M represents the maximum adjustable number of parallel convolution computations, and N represents the maximum adjustable number of convolution kernel elements. For example... Figure 2 As shown, the LocalArray includes a non-volatile memory column (NVMArray) and a logic switch unit (LocalMAV); the NVMArray is used to store parameters; the Local MAV is used to connect to the Local MAV of other local memory arrays in the word line direction through the first bus Vpavg and the second bus Vnavg, and is connected to the non-volatile memory column through the first bit line BLP and the second bit line BLN.

[0028] The NVMArray includes C groups of storage units, which are connected to other local memory arrays in the bit line direction via the first bit line (BLP) and the second bit line (BLN). Each storage unit includes two resistive random access memory (RRAM) devices and two gating devices. One end of one RRAM device is connected to the first bit line (BLP), and the other end is grounded through a gating device. One end of the other RRAM device is connected to the second bit line (BLN), and the other end is grounded through another gating device. The RRAM devices are used to store the differential signals of the convolution kernel weight information, and the gating devices are used to select the RRAM devices.

[0029] In this embodiment, the resistive random access memory device is at least one of oxide-based resistive random access memory (RRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), and magnetoresistive random access memory (MRAM); the gating device is at least one of CMOS, BJT, diode, and oxide-based switching device.

[0030] The Local MAV includes two NMOS transistors, two PMOS transistors, and four switching devices. The two NMOS transistors are controlled by a reset signal (RST) to reset the voltage of the first bit line BLP and the second bit line BLN. The two PMOS transistors are controlled by a precharge signal (PCHG) to charge the first bit line BLP and the second bit line BLN. The four switching devices are used to connect the first bit line BLP and the second bit line BLN to the first bus Vpavg and the second bus Vnavg to achieve charge balance of the bit lines in the word line direction.

[0031] The Local MAV further converts the convolution input digital signal into a voltage signal on either the first bit line (BLP) or the second bit line (BLN) via a Global Bit Line (GBL). The analog-to-digital converter is used to convert the voltage difference between the first bus Vpavg and the second bus Vnavg into a convolution output digital signal.

[0032] When performing convolution calculations using the aforementioned convolution calculation circuit based on resistive random access memory, such as Figure 3 As shown, it includes the following steps:

[0033] Based on the configuration information, part or all of the memory array is selected through the word / bit line decoder;

[0034] Read the weight parameters from the selected memory array;

[0035] Turn on the RST-controlled NMOS transistor to reset the voltage of the first bit line BLP and the second bit line BLN in the selected memory array to zero;

[0036] According to the weight parameters, the PMOS transistor controlled by PCHG is turned on, and the digital-to-analog converter converts the convolution input digital signal into an analog voltage signal on the first bit line BLP or the second bit line BLN in the selected memory array through GBL.

[0037] Based on the weight parameters, turn on the switching device EN. P / EN N This allows the charges on the first bit line (BLP) and the second bit line (BLN) in the word line direction to be redistributed and balanced (if the result is positive, then EN is turned on). P If the result is negative, then open EN. N );

[0038] Under the control of the signal SAEN, the analog-to-digital converter converts the analog voltage difference between the first bus Vpavg and the second bus Vnavg into a convolutional output digital signal. The sign of the convolutional output digital signal depends on the result of the first comparison. If the result of the first comparison is positive, the sign is positive; if the result of the first comparison is negative, the sign is negative.

[0039] It is easy to see that in this invention, the logic values ​​stored in the memory cells of the in-memory array serve as the convolution kernel, and the voltage on the bit lines of the digital-to-analog converter (DAC) output in the in-memory array serves as the input for the convolution to be calculated. The multiplication and accumulation in the convolution operation are completed by utilizing the charge balance on the Vpavg and Vnavg buses in the word line direction. The voltage difference between Vpavg and Vnavg in the in-memory array serves as the result of the convolution calculation. In this invention, the storage of the convolution kernel and the calculation of the convolution are performed in the same array, achieving the integration of computation and storage. This improves computation speed while reducing hardware costs and energy consumption. Furthermore, the parallel expansion is achieved by utilizing the large-scale integration capability of resistive random access memory (RRAM), significantly improving the efficiency of convolution calculation.

Claims

1. A convolution calculation circuit based on resistive random access memory, characterized in that, include: In-memory arrays, digital-to-analog converters, analog-to-digital converters, word / bit line decoders, and controllers; The in-memory array is connected to the digital-to-analog converter (DAC) in the bit-line direction and to the analog-to-digital converter (ADC) in the word-line direction. The DAC's input is a convolution input digital signal, and its output is connected to the in-memory array. The ADC's input is connected to the in-memory array, and its output is a convolution output digital signal. The output of the word / bit-line decoder is connected to the in-memory array for selecting part or all of the in-memory array. The controller's output is connected to the in-memory array, the DAC, and the ADC, respectively, for generating control signals to implement convolution calculations. The in-memory array includes M rows of bit-line arrays and N columns of word-line arrays, where M represents the maximum adjustable number of parallel convolution calculations, and N represents the maximum adjustable number of convolution kernel elements. The local memory array includes non-volatile memory columns and logic switching units. The non-volatile memory columns are used to store parameters. The logic switching units are used to connect to the logic switching units of other local memory arrays in the word line direction via a first bus Vpavg and a second bus Vnavg, and to the non-volatile memory columns via a first bit line BLP and a second bit line BLN. The logic values ​​stored in the memory array are used as convolution kernels. The voltage on the bit lines of the memory array output by the digital-to-analog converter is used as the input to the convolution to be calculated. The multiplication and accumulation in the convolution operation are completed by utilizing the charge balance on the first bus Vpavg and the second bus Vnavg in the word line direction. The voltage difference between the first bus Vpavg and the second bus Vnavg in the memory array is used as the result of the convolution calculation.

2. The convolution calculation circuit based on resistive random access memory according to claim 1, characterized in that, The non-volatile memory array includes C groups of memory cells, which are connected to other local memory arrays in the bit line direction via the first bit line (BLP) and the second bit line (BLN). Each memory cell includes two resistive random access memory (RRAM) devices and two gating devices. One end of one RRAM device is connected to the first bit line (BLP), and the other end is grounded through a gating device. One end of the other RRAM device is connected to the second bit line (BLN), and the other end is grounded through another gating device. The RRAM devices are used to store the differential signal of the convolution kernel weight information, and the gating devices are used to select the RRAM devices.

3. The convolution calculation circuit based on resistive random access memory according to claim 2, characterized in that, The resistive switching memory device is at least one of oxide-based resistive switching memory (RRAM), ferroelectric memory (FRAM), phase change memory (PCM), and magnetoresistive memory (MRAM).

4. The convolution calculation circuit based on resistive random access memory according to claim 2, characterized in that, The gating device is at least one of CMOS, BJT, Diode, and oxide-based switching devices.

5. The convolution calculation circuit based on resistive random access memory according to claim 1, characterized in that, The logic switching unit includes two NMOS transistors, two PMOS transistors, and four switching devices. The two NMOS transistors are controlled by a reset signal to reset the voltage of the first bit line BLP and the second bit line BLN. The two PMOS transistors are controlled by a pre-charge signal to charge the first bit line BLP and the second bit line BLN. The four switching devices are used to connect the first bit line BLP and the second bit line BLN to the first bus Vpavg and the second bus Vnavg to achieve charge balance of the bit lines in the word line direction.

6. The convolution calculation circuit based on resistive random access memory according to claim 1, characterized in that, The logic switching unit also converts the convolution input digital signal into a voltage signal on the first bit line BLP or the second bit line BLN via a global bit line.

7. The convolution calculation circuit based on resistive random access memory according to claim 1, characterized in that, The analog-to-digital converter is used to convert the voltage difference between the first bus Vpavg and the second bus Vnavg into a convolutional output digital signal.

8. A convolution calculation method based on resistive random access memory, characterized in that, The convolution calculation circuit based on resistive random access memory as described in any one of claims 1-7 includes the following steps: Based on the configuration information, part or all of the memory array is selected through the word / bit line decoder; Read the weight parameters from the selected memory array; Turn on the NMOS transistor controlled by the reset signal to reset the voltage of the first bit line BLP and the second bit line BLN in the selected memory array to zero; According to the weight parameters, the PMOS transistor controlled by the precharge signal is turned on, and the digital-to-analog converter converts the convolution input digital signal into an analog voltage signal on the first bit line BLP or the second bit line BLN in the selected memory array. According to the weighting parameters, the switching device is turned on, allowing the charge on the first bit line BLP and the second bit line BLN in the word line direction to be redistributed and balanced. The analog-to-digital converter converts the analog voltage difference between the first bus Vpavg and the second bus Vnavg into a convolutional output digital signal.

9. The convolution calculation method based on resistive random access memory according to claim 8, characterized in that, When the analog-to-digital converter converts the analog voltage difference between the first bus Vpavg and the second bus Vnavg into a convolutional output digital signal, the sign of the convolutional output digital signal depends on the result of the first comparison. If the result of the first comparison is positive, the sign is positive; if the result of the first comparison is negative, the sign is negative.

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