Display device

Abstract

The display device of the present invention aims to improve the performance of the display device. The peripheral wiring area (PFWA) of the display device (DSP1) includes: an insulating layer (31) located on a substrate (10); a wiring layer (WL1) located on the insulating layer (31); an insulating layer (32) located on the insulating layer (31) and covering the wiring layer (WL1); and a wiring layer (WL2) located on the insulating layer (32). In the wiring layer (WL1), a plurality of image signal wirings (VSW) are arranged. In the wiring layer (WL2), a plurality of touch detection wirings (TDW) arranged in a matrix in the X direction and the Y direction, and a conductor pattern (CCP) supplied with a fixed potential are formed. The conductor pattern (CCP) is arranged at a position overlapping with a portion of the plurality of image signal wirings (VSW) and is capacitively coupled with a portion of the plurality of image signal wirings (VSW).

Description

Technical Field

[0001] The present invention relates to a display device. Background Art

[0002] In Patent Document 1 (Japanese Patent Publication No. 2018-132606), as a noise countermeasure for high-frequency pulses for contact sensing, a structure in which a mesh shielding portion is arranged on a sensor power supply line is described. In addition, in Patent Document 2 (Japanese Patent Publication No. 2019-39985), a structure in which a shielding layer made of the same material as a transparent electrode is arranged on the upper layer of multiple connection lines connected to a signal selection circuit is described.

[0003] Prior art literature

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2018-132606

[0006] Patent Document 2: Japanese Patent Application Publication No. 2019-39985 Summary of the invention

[0007] Problems to be solved by the invention

[0008] As a use of the display device, there is a case where it is used as a portable terminal device with a wireless communication function between external devices. In the case of a display device with a wireless communication function, if the electromagnetic waves generated by the switching action for inputting a signal for the display function interfere with the frequency band of the wireless communication, it becomes noise for the wireless communication. Therefore, a technology for suppressing the generation of electromagnetic waves as a noise source is required.

[0009] An object of the present invention is to provide a technology for improving the performance of a display device.

[0010] Means used to solve problems

[0011] A display device as a technical solution of the present invention comprises: a first substrate having a first side extending in a first direction and a second side located on the opposite side of the first side in a second direction orthogonal to the first direction; a display area located between the first side and the second side in the second direction; a plurality of touch detection electrodes arranged in a matrix in the first direction and the second direction in the display area; a switch circuit area located between the first side and the display area in the second direction and provided with a signal selection circuit; a peripheral wiring area located between the first side and the switch circuit area in the second direction and provided with a plurality of peripheral wirings, the plurality of peripheral wirings including a plurality of image signal wirings connected to the signal selection circuit and a plurality of touch detection wirings connected to the plurality of touch detection electrodes; and a terminal area located between the first side and the peripheral wiring area in the second direction and provided with a plurality of terminals electrically connected to the plurality of peripheral wirings. The peripheral wiring area includes: a first insulating layer located on the first substrate; a first wiring layer located on the first insulating layer; a second insulating layer located on the first insulating layer and covering the first wiring layer; and a second wiring layer located on the second insulating layer. The first wiring layer is provided with the plurality of image signal wirings. The second wiring layer is provided with the plurality of touch detection wirings and a conductor pattern supplied with a first potential. The conductor pattern is provided at a position overlapping with a portion of the plurality of image signal wirings and is capacitively coupled with the portion of the plurality of image signal wirings. In the display area, the plurality of touch detection electrodes are formed on the second insulating layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] Figure 1 It is a plan view showing a display surface side of an example of a display device as one embodiment.

[0013] Figure 2 It is along Figure 1 Cross-sectional view of line A-A.

[0014] Figure 3 Yes means Figure 1 A circuit diagram showing an example of a circuit configuration around a pixel included in the display device shown.

[0015] Figure 4 yes Figure 2 An enlarged cross-sectional view of a display area of ​​a display device is shown.

[0016] Figure 5 Yes means Figure 1 2 is a plan view showing an example of a layout of common electrodes (touch detection electrodes) included in the display device shown.

[0017] Figure 6It is a schematic representation of the configuration in Figure 1 FIG. 1 is a diagram for explaining the operation of the signal selection circuit in the switch circuit area shown.

[0018] Figure 7 Yes means Figure 1 An enlarged cross-sectional view of an example of noise countermeasures in the peripheral wiring area shown.

[0019] Figure 8 yes Figure 1 An enlarged plan view of section B is shown.

[0020] Fig. 9 Yes means Figure 8 An enlarged plan view of a modified example of a portion of the wiring area shown.

[0021] Fig.10 Yes means Figure 8 An enlarged plan view of another modified example of a portion of the wiring area shown.

[0022] Fig.11 It means for Fig.10 An enlarged plan view of the study example.

[0023] Fig.12 It means for Figure 7 An enlarged cross-sectional view of a modified example.

[0024] Fig.13 It means for Figure 7 An enlarged cross-sectional view of another variation of .

[0025] Fig.14 It means for Figure 7 An enlarged cross-sectional view of another variation of .

[0026] Fig.15 Yes means Fig.10 An enlarged plan view of a modified example of multiple video signal wirings shown.

[0027] Fig.16 Yes means Fig.10 An enlarged plan view of another modified example of the plurality of image signal wirings shown.

[0028] Description of symbols

[0029] 10, 20 substrate

[0030] 10f, 20f front surface (face, main surface)

[0031] 10s1, 10s2, 10s3, 10s4 side

[0032] 20b Back side (face, main surface)

[0033] 11-16 Insulation film

[0034] 31, 32, 32h, 33 Insulation layer

[0035] AL1, AL2 oriented film

[0036] ASW signal selection circuit

[0037] ASWA Switch Circuit Area

[0038] ASWS signal selection signal

[0039] BM Shading Film

[0040] CCP, CCP1, CCP2, CCP3, CCP4 conductor pattern

[0041] CD common potential supply circuit

[0042] CDF Conductive Film

[0043] CE electrode (touch detection electrode)

[0044] CFB, CFG, CFR color filters

[0045] CL1, CL2, CL3, CL4, CL5 Conductive layer

[0046] CS capacitor element

[0047] DA display area

[0048] DM display module

[0049] DP Detection Circuit

[0050] DSP1, DSP2, DSP3, DSP4, DSP5, DSP6, DSPc Display device

[0051] GD Scan Drive Circuit (Gate Drive Circuit)

[0052] GL Scan signal line

[0053] Gsi scanning signal

[0054] LQ Liquid Crystal Layer

[0055] MP connection circuit

[0056] MW3, VCW Cabling

[0057] OD1, OD2 optical components

[0058] PE pixel electrode

[0059] PFA Surrounding Area

[0060] PFWA Peripheral Wiring Area

[0061] PFWA Switching Circuit Area

[0062] PX Pixel

[0063] PXs Sub-pixel

[0064] R1-R11 wiring area

[0065] SCF Semiconductor Film

[0066] SCP Semiconductor Devices

[0067] SD video signal driving circuit

[0068] SL Video Signal Cable

[0069] SLM seals (bonded parts)

[0070] TCF1, TCF2 transparent conductive film

[0071] TDW Touch Detection Wiring

[0072] TM1 terminal

[0073] TMA terminal area

[0074] TMM Communication Module

[0075] Tr1 transistor (transistor element)

[0076] VS Image signal (video signal)

[0077] VSW image signal wiring

[0078] W1, W2 Wiring width

[0079] W3 Width

[0080] WL1, WL2 wiring layers DETAILED DESCRIPTION

[0081] Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings. In addition, the disclosure is only an example, and forms that can be easily thought of by those skilled in the art for appropriate changes that maintain the spirit of the invention are of course included in the scope of the present invention. In addition, the drawings schematically show the width, thickness, shape, etc. of each part compared to the actual form in order to make the description clearer, but this is only an example and does not limit the interpretation of the present invention. In addition, in this specification and each figure, the same or related reference numerals are given to the same elements as those described in the previous figures, and detailed descriptions may be appropriately omitted.

[0082] In addition, in the following embodiments, as an example of a display device, a liquid crystal display device having a liquid crystal layer as an electro-optical layer is used for description. However, the technology described below can be applied to various modifications other than the liquid crystal display device. For example, the electro-optical layer may be an organic light-emitting element layer, an inorganic light-emitting element layer including micro-LEDs, a MEMS (Micro Electro Mechanical Systems) shutter or an electrophoretic element layer, etc., as long as it is a layer including an element whose optical characteristics change by applying electrical energy.

[0083] In addition, liquid crystal display devices are generally classified into the following two types according to the direction of application of the electric field used to change the orientation of the liquid crystal molecules in the liquid crystal layer. That is, as the first category, there is a so-called longitudinal electric field mode in which an electric field is applied in the thickness direction (or out-of-plane direction) of the display device. In the longitudinal electric field mode, there are, for example, a TN (Twisted Nematic) mode, a VA (Vertical Alignment) mode, and the like. In addition, as the second category, there is a so-called transverse electric field mode in which an electric field is applied in the plane direction (or in-plane direction) of the display device. In the transverse electric field mode, there are, for example, an IPS (In-Plane Switching) mode, and an FFS (Fringe Field Switching) mode which is one of the IPS modes, and the like. The technology described below can be applied to both the longitudinal electric field mode and the transverse electric field mode, but in the embodiment described below, a display device in the transverse electric field mode is described as an example.

[0084] <Structure of Display Device>

[0085] First, the structure of the display device will be described. Figure 1 FIG. 1 is a plan view showing a display surface side of an example of a display device according to the present embodiment. Figure 1 In FIG. 1 , the boundary between the display area DA and the peripheral area PFA, the switch circuit area ASWA, the peripheral wiring area PFWA, and the terminal area TMA are indicated by double-dashed lines. Figure 1 In FIG. 1 , a shadow is given to the area where the seal SLM is arranged. Figure 1 , four video signal wirings VSW arranged at the end of the video signal wiring group among a large number of video signal wirings VSW are representatively described. Figure 2 It is along Figure 1 A cross-sectional view of the A-A line. Figure 4 As shown in FIG. 1 , between the substrate 10 and the substrate 20, there are a plurality of conductive layers and insulating layers in addition to the liquid crystal layer LQ. Figure 2 Illustration omitted. Figure 3 Yes means Figure 1 A circuit diagram showing an example of a circuit configuration around a pixel in a display region included in the display device shown. Figure 4 yes Figure 2 An enlarged cross-sectional view of a display area of ​​a display device is shown. Figure 4 In the figure, since the thickness direction of the substrate 10 is indicated ( Figure 4 The example of the positional relationship between the scanning signal line GL and the image signal line SL in the Z direction shown in FIG. Figure 4 The scanning signal lines GL in different cross sections are indicated by dotted lines.

[0086] like Figure 1 As shown, the display device DSP1 of this embodiment includes a substrate 10, a display area DA, a switch circuit area ASWA, a peripheral wiring area PFWA, and a terminal area TMA. The substrate 10 includes a side 10s1 extending in the X direction (first direction) and a side 10s2 located on the opposite side of the side 10s1 in the Y direction (second direction) orthogonal to the X direction. In addition, the substrate 10 includes a side 10s3 extending in the Y direction and a side 10s4 located on the opposite side of the side 10s3 in the X direction.

[0087] The display area DA is located between the side 10s1 and the side 10s2 in the Y direction. In the display area DA, an image is formed in response to an input signal supplied from the outside. The display area DA is an effective area for the display device DSP1 to display an image in a plan view when observing the display surface. In addition, the display device DSP1 has a peripheral area (non-display area) PFA around the display area DA in a plan view. Figure 1 In the example shown, the peripheral area PFA is arranged between the side 10s2 and the display area DA, between the side 10s3 and the display area DA, and between the side 10s4 and the display area DA. However, as a modified example, there is also a case where the peripheral area PFA is not arranged between the side 10s2 and the display area DA, between the side 10s3 and the display area DA, and between the side 10s4 and the display area DA, and the display area DA extends to the peripheral end of the substrate 10.

[0088] The switch circuit area ASWA is located between the side 10s1 and the display area DA in the Y direction. A signal selection circuit ASW (see below) composed of a plurality of switch elements is arranged in the switch circuit area ASWA. Figure 6 ). The signal selection circuit ASW will be described in detail later.

[0089] The peripheral wiring area PFWA is located between the side 10s1 and the switch circuit area ASWA in the Y direction. In the switch circuit area PFWA, a plurality of peripheral wirings including a plurality of image signal wirings connected to the signal selection circuit and a plurality of touch detection wirings connected to the plurality of touch detection electrodes are arranged. The details of the image signal wirings and the touch detection wirings will be described later.

[0090] The terminal area TMA is located between the side 10s1 and the peripheral wiring area PFWA in the Y direction. A plurality of terminals TM1 electrically connected to a plurality of peripheral wirings are arranged in the terminal area TMA (see Figure 2 ). The plurality of terminals TM1 arranged in the terminal area TMA and the image signal (video signal) VS (refer to Figure 3 ) and a control circuit for controlling the driving signal. Figure 2 In the example shown, a semiconductor device SCP is mounted on the terminal TM1, and a control circuit for controlling the image signal and the drive signal is formed in the semiconductor device SCP. As an example, the semiconductor device SCP is an external drive circuit such as a driver IC chip. In addition, as a modified example, there is also the following case: the semiconductor device SCP is formed on a flexible wiring substrate (not shown), the terminal TM1 is connected to a terminal of the flexible wiring board, and the terminal TM1 is connected to the control circuit ( Figure 3 The scanning driving circuit GD, the image signal driving circuit SD and the common potential supply circuit CD shown are connected.

[0091] like Figure 2 As shown, the display device DSP1 includes a substrate 10 and a substrate 20 which are bonded opposite to each other with a liquid crystal layer LQ interposed therebetween. The substrate 10 and the substrate 20 are opposed to each other in the thickness direction (Z direction) of the display device DSP1. The substrate 10 includes a front surface 10f which is opposed to the liquid crystal layer LQ (and the substrate 20). The substrate 10 includes a back surface 10b which is on the opposite side of the front surface 10f. In addition, the substrate 20 includes a back surface 20b which is opposed to the front surface 10f (and the liquid crystal layer LQ) of the substrate 10. The substrate 20 includes a front surface 20f which is on the opposite side of the back surface 20b. The substrate 10 includes a plurality of transistors (transistor elements) Tr1 (see FIG. 1 ) which are switching elements (active elements) arranged in an array. Figure 3 ) array substrate. In addition, the substrate 20 is a substrate provided on the display surface side. The substrate 20 can be referred to as an opposing substrate in the sense of a substrate arranged opposite to the array substrate.

[0092] In addition, the liquid crystal layer LQ is located between the front surface 10f of the substrate 10 and the back surface 20b of the substrate 20. The liquid crystal layer LQ is an electro-optical layer that controls the transmission state of visible light. It has a function of modulating the light passing therethrough by controlling the state of the electric field formed around the liquid crystal layer LQ through the switching element. The display area DA at the substrate 10 and the substrate 20 is as shown in FIG. Figure 2 As shown, it overlaps with the liquid crystal layer LQ.

[0093] In addition, the substrate 10 and the substrate 20 are bonded together via a sealing member (adhesive member) SLM. Figure 1 As shown, the seal member SLM is arranged in the peripheral area PFA so as to surround the display area DA. Figure 2 As shown, a liquid crystal layer LQ is provided inside the sealant SLM. The sealant SLM functions as a sealant for sealing the liquid crystal between the substrate 10 and the substrate 20. In addition, the sealant SLM functions as an adhesive for bonding the substrate 10 and the substrate 20 together.

[0094] In addition, the display device DSP1 has an optical element OD1 and an optical element OD2. The optical element OD1 is arranged on the back surface 10b side of the substrate 10. The optical element OD2 is arranged on the front surface 20f side of the substrate 20, in other words, on the display surface side. The optical element OD1 and the optical element OD2 each include at least a polarizing plate, and may also include a phase difference plate as needed. In addition, although omitted in the figure, the display device DSP1 has a light source unit. The light source unit is arranged, for example, on the back side of the optical element OD1 (the position on the opposite side of the substrate 10) or in the peripheral area PFA on the substrate 10.

[0095] The substrate 10 and the substrate 20 are transparent plates having visible light transmittance (visible light transmittance characteristics). As a substrate for the transparent plate, a glass substrate can be exemplified. In addition, as constituent materials of the substrate 10 and the substrate 20, resin materials containing polymers such as polyimide, polyamide, polycarbonate or polyester (visible light transmittance resin materials) can also be used. In addition, in the case of a substrate composed of a resin material such as polyimide, the substrate has flexibility. In the case where the substrate 10 has flexibility, a portion of the substrate 10 (for example, the peripheral area PFA) can be bent or folded. In the case where the substrates 10 and 20 have flexibility, the area of ​​the peripheral area PFA in a plan view can be reduced. In this case, the occupancy rate of the effective display area in a plan view can be increased.

[0096] like Figure 3 As shown in FIG. 1 , a plurality of pixels (pixels) PX are arranged in the display area DA. Figure 3In the example shown, each of the plurality of pixels PX has a plurality of sub-pixels (sub-pixels) PXs. The plurality of sub-pixels PXs include, for example, sub-pixels PXs for red, blue, and green. By controlling the tones of the plurality of sub-pixels PXs, a color image can be displayed. The number of types of sub-pixels PXs constituting one pixel PX is Figure 3 In addition to the three examples shown in the figure, various modifications can be applied.

[0097] Each of the plurality of sub-pixels PXs includes a transistor Tr1 as a switching element for controlling the on / off of an electric field applied to the liquid crystal layer LQ. The transistor Tr1 controls the operation of the sub-pixel PXs. As described below, the transistor Tr1 is a thin film transistor (TFT) formed on the substrate 10 .

[0098] In addition, if Figure 3 As shown, the display device DSP1 includes a plurality of scanning signal lines GL extending in the X direction in the display area DA, and a plurality of scanning signal lines GL intersecting the X direction in the display area DA. Figure 3 The scanning signal line GL is a gate line connected to the gate of the transistor Tr1. In addition, the image signal line SL is a source line connected to the source of the transistor Tr1. The plurality of scanning signal lines GL extend in the X direction and are arranged, for example, at equal intervals in the Y direction. The plurality of image signal lines SL extend in the Y direction and are arranged, for example, at equal intervals in the X direction.

[0099] The plurality of scanning signal lines GL are connected to the scanning drive circuit (gate drive circuit) GD, respectively. The scanning signal Gsi output from the scanning drive circuit GD is input to the gate of the transistor Tr1 via the scanning signal line GL. In addition, the plurality of image signal lines SL are connected to the image signal drive circuit SD, respectively. The image signal VS output from the image signal drive circuit SD is input to the source of the transistor Tr1 via the image signal line SL. The scanning drive circuit GD and the image signal drive circuit SD are composed of, for example, Figure 2 Alternatively, as a modified example, a video signal driving circuit SD is formed in Figure 1 The situation on the substrate 10 is shown.

[0100] The plurality of image signal lines SL are connected to the pixel electrode PE via the transistor Tr1. Specifically, the image signal line SL is connected to the source of the transistor Tr1, and the pixel electrode PE is connected to the drain of the transistor Tr1. When the transistor Tr1 is turned on, the pixel electrode PE is supplied with the image signal VS from the image signal line SL. In addition, the pixel electrode PE is connected to the source of the transistor Tr1 via the dielectric layer ( Figure 3The capacitor element CS shown in the figure is connected to the electrode CE. During the display period of displaying an image on the display area DA, the plurality of electrodes CE as common electrodes are respectively supplied with a fixed potential from the common potential supply circuit CD. The fixed potential supplied to the electrode CE is a potential common to the plurality of sub-pixels PXs (hereinafter referred to as a common potential). During the display period, an electric field is formed in each sub-pixel PXs in accordance with the potential difference between the common potential supplied to the electrode CE and the potential supplied to the pixel electrode PE, and the liquid crystal molecules included in the liquid crystal layer LQ are driven by the electric field.

[0101] Figure 3 The scanning drive circuit GD, the image signal drive circuit SD, and the common potential supply circuit CD shown in FIG. 1 are led out to the Figure 1 The terminal area TMA shown is electrically connected to the semiconductor device SCP.

[0102] like Figure 4 As shown, there are a plurality of conductive layers CL1 to CL5, a plurality of insulating films 11 to 16, and an alignment film AL1 between the substrate 10 and the liquid crystal layer LQ. The plurality of conductive layers CL1 to CL5, the plurality of insulating films 11 to 16, and the alignment film AL1 are formed on the front surface 10f of the substrate 10. In addition, there are a light shielding film BM, color filters CFR, CFG and CFB, an insulating film OC1, and an alignment film AL2 between the substrate 20 and the liquid crystal layer LQ. The light shielding film BM, the color filters CFR, CFG, CFB, the insulating film OC1, and the alignment film AL2 are formed on the back surface 20b of the substrate 20.

[0103] exist Figure 4 In each of the conductive layers CL1, CL2 and CL3 shown, a conductor pattern (metal wiring) of a light-shielding metal is formed. The conductive layer CL1 includes a metal film composed of, for example, a metal such as molybdenum (Mo), tungsten (W) or an alloy thereof. The conductor patterns of the conductive layers CL2 and CL3 include metal films of a multilayer structure such as a laminated film obtained by sandwiching an aluminum (Al) film such as a titanium (Ti) film or a titanium nitride (TiN) film. In addition, the conductive layers CL4 and CL5 mainly include conductive oxide materials (transparent conductive materials) such as ITO (Indium tinoxide) or IZO (Indium Zinc Oxide). In this specification, a conductor film formed of a material having both visible light transmittance and conductivity such as ITO and IZO is referred to as a transparent conductive film.

[0104] The insulating film is between the conductive layers CL1 to CL5. The insulating film 11 and the insulating film 12 are between the conductive layer CL1 and the substrate 10. The insulating film 13 is between the conductive layer CL1 and the conductive layer CL2. The insulating film 14 is between the conductive layer CL3 and the conductive layer CL4. The insulating film 15 is between the conductive layer CL4 and the conductive layer CL5. The alignment film AL1 is between the conductive layer CL5 and the liquid crystal layer LQ. The insulating films 11, 12, 13 and 16 are respectively inorganic insulating films. As inorganic insulating films, examples such as silicon nitride (SiN) films, silicon oxide (SiO) films, aluminum oxide (AlOx) films or their stacked films can be exemplified. In addition, the insulating film 14 and the insulating film 15 are organic insulating films. The insulating film composed of an organic material can be formed thicker than the insulating film composed of an inorganic material, so that the upper surface (front surface) can be flattened. The insulating film 14 and the insulating film 15 are used as a flattening film to flatten the unevenness of the conductor pattern formed on the base layer. Therefore, the thickness of the insulating film 14 and the thickness of the insulating film 15 are thicker than the thickness of each of the inorganic insulating films 11, 12, and 13. Examples of the organic insulating film include acrylic photosensitive resins and the like.

[0105] A plurality of scanning signal lines GL are respectively formed on the conductive layer CL1 on the substrate 10. An insulating film 11 and an insulating film 12 are stacked on the substrate 10, and the scanning signal lines GL are formed on the insulating film 12. A plurality of video signal lines SL are respectively formed on the conductive layer CL2 on the substrate 10. Insulating films 11, 12, and 13 are stacked on the substrate 10, and the video signal lines SL are formed on the insulating film 13.

[0106] A layer is formed between the insulating film 11 and the insulating film 12. Figure 3 The semiconductor layer of the transistor (transistor element) Tr1 shown in FIG. Figure 4 Different cross-sections, so in Figure 4 There is no semiconductor layer shown in the figure. The source region of the semiconductor layer is electrically connected to the image signal line SL formed in the conductive layer CL2. The drain region of the semiconductor layer is electrically connected to the pixel electrode PE of the conductive layer CL5. In the plan view, the scanning signal line GL extends between the source region and the drain region of the semiconductor layer. In addition, the scanning signal line GL overlaps with the channel region of the semiconductor layer and functions as the gate electrode of the transistor Tr1. The insulating film 12 between the channel region and the scanning signal line GL functions as a gate insulating film. A TFT having a structure in which a gate electrode is arranged on the upper side of the channel region of the transistor Tr1 as in the above example is called a top gate method. However, there are various modifications in the TFT method, for example, a bottom gate method in which a gate electrode is arranged on the lower side of the channel region may also be adopted. Alternatively, there is a method in which gate electrodes are arranged on both the upper and lower sides of the channel region.

[0107] Wiring MW3 is arranged in the conductive layer CL3. Wiring MW3 is a metal wiring made of metal like the scanning signal line GL and the image signal line SL. Wiring MW3 is arranged at a position overlapping with the image signal line SL in the thickness direction (Z direction). Wiring MW3 is electrically connected to the electrode CE formed in the conductive layer CL4. In this case, wiring MW3 can be used as wiring for supplying a potential to the electrode CE. As described later, the electrode CE is used as a detection electrode for detecting an input position (touch position) by using a change in electrostatic capacitance in the display device DSP1 as a touch panel. Wiring MW3 electrically connects the electrode CE for detecting the input position to the detection circuit. In this case, wiring MW3 is used as a signal transmission path for transmitting a drive signal and a detection signal used in detecting a touch position.

[0108] The conductive layer CL4 includes a transparent conductive film TCF1 having visible light transmittance, and is located between the substrate 10 and the substrate 20. An electrode CE is formed in the conductive layer CL4. The plurality of transparent conductive films TCF1 formed in the conductive layer CL4 include the electrode CE. The electrode CE is formed on the insulating film 15 as a planarizing film in the display area DA. The insulating film 15 is connected to the substrate 10 described later. Figure 7 The insulating layer 32 shown corresponds to the Figure 3 In the figure, an electrode CE is shown, but in Figure 1 In the display area DA shown in FIG. 1 , the plurality of electrodes CE are arranged to be spaced apart from each other. In addition, as described above, the electrode CE is supplied with a common potential for the plurality of sub-pixels PXs. Figure 3 As shown in FIG. 1 , the electrode CE is arranged in the range of a plurality of sub-pixels PXs. In the case of this embodiment, as described later, the electrode CE is used as a detection electrode for input position detection. Figure 1 In the display area DA shown, a plurality of electrodes CE are arranged to be spaced apart from each other. The details of the layout of the electrodes CE in a plan view will be described later.

[0109] The conductive layer CL5 includes a transparent conductive film TCF2 that is transparent to visible light and is located between the conductive layer CL4 and the substrate 20. A plurality of pixel electrodes PE are formed in the conductive layer CL5. The plurality of transparent conductive films TCF2 formed in the conductive layer CL5 include a plurality of pixel electrodes PE. An insulating film 16 as an inorganic insulating film is provided between the conductive layer CL5 on which the pixel electrodes PE are formed and the conductive layer CL4 on which the electrodes CE are formed. The insulating film 16 functions as a dielectric layer and is formed Figure 3 The capacitive element CS is shown.

[0110] The plurality of pixel electrodes PE are covered with an alignment film AL1. The alignment film AL1 is an organic insulating film having a function of aligning the initial alignment of liquid crystal molecules contained in the liquid crystal layer LQ, and is made of, for example, polyimide resin. The alignment film AL1 is in contact with the liquid crystal layer LQ.

[0111] In addition, if Figure 3 As shown, on the back surface (main surface, surface) 20 b of the substrate 20 , a light shielding film BM, color filters CFR, CFG, CFB, an insulating film OC1 , and an alignment film AL2 are formed.

[0112] The color filters CFR, CFG, and CFB are formed on the back surface 20b side facing the substrate 10. Figure 4 In the example shown, color filters CFR, CFG, and CFB of three colors, red (R), green (G), and blue (B), are periodically arranged. In a color display device, for example, a color image is displayed with pixels of the three colors, red (R), green (G), and blue (B), as one group. The plurality of color filters CFR, CFG, and CFB of the substrate 20 are arranged at the positions corresponding to the pixels PX (see FIG. 1 ) having the pixel electrodes PE formed on the substrate 10. Figure 1 ) are located opposite to each other. In addition, the types of color filters are not limited to the three colors of red (R), green (G), and blue (B).

[0113] In addition, a light shielding film BM is arranged at each boundary of the color filters CFR, CFG, and CFB of each color. The light shielding film BM is called a black matrix, and is made of, for example, a black resin or a low-reflective metal. The light shielding film BM of the display area DA is formed in a grid shape in a plan view, for example. In other words, the light shielding film BM extends in the X direction and the Y direction. In detail, the light shielding film BM has a plurality of portions extending in the Y direction and a plurality of portions extending in the X direction intersecting the Y direction. By dividing each pixel PX with a black matrix, light leakage and color mixing can be suppressed.

[0114] The light-shielding film BM overlaps with the scanning signal line GL, the image signal line SL, and the wiring MW3, which are metal wirings, in the display area DA. By arranging the metal wirings with light-shielding properties at a position overlapping with the light-shielding film BM, it is difficult to identify the metal wirings in the display screen. On the other hand, at least a portion of the electrode CE and the pixel electrode PE is arranged at a position that does not overlap with the light-shielding film BM. The electrode CE and the pixel electrode PE are formed of a conductive material that is transparent to visible light. Therefore, although the electrode CE and the pixel electrode PE are arranged at a position that does not overlap with the light-shielding film BM, in each sub-pixel PXs, visible light is not shielded by the electrode CE and the pixel electrode PE.

[0115] In addition, the light shielding film BM is also formed in the peripheral area PFA of the substrate 20 (see Figure 1). The peripheral area PFA overlaps with the light-shielding film BM. The display area DA is defined as an area that is closer to the inside than the peripheral area PFA. In addition, the peripheral area PFA is a region that overlaps with the light-shielding film BM that shields light irradiated from the backlight unit (light source, omitted in the figure). The light-shielding film BM is also formed in the display area DA, but in the display area DA, a plurality of openings are formed in the light-shielding film BM. Usually, among the openings formed in the light-shielding film BM and exposing the color filter, the end of the opening formed on the side closest to the peripheral portion is defined as the boundary between the display area DA and the peripheral area PFA.

[0116] Figure 4 The insulating film OC1 shown covers the color filters CFR, CFG, and CFB. The insulating film OC1 functions as a protective film that prevents impurities from diffusing from the color filters to the liquid crystal layer. The insulating film OC1 is an organic insulating film made of, for example, an acrylic photosensitive resin.

[0117] The insulating film OC1 is covered with an alignment film AL2. The alignment film AL2 is an organic insulating film having a function of aligning the initial alignment of liquid crystal molecules contained in the liquid crystal layer LQ, and is made of, for example, polyimide resin. In addition, the alignment film AL2 is in contact with the liquid crystal layer LQ.

[0118] <Touch panel function>

[0119] Next, the touch panel function included in the display device DSP1 of the present embodiment will be described. Figure 5 Yes means Figure 1 FIG. 1 is a plan view showing an example of a layout of common electrodes (touch detection electrodes) included in the display device shown in FIG. Figure 5 , four touch detection wirings TDW arranged at the end of the touch detection wiring group among a large number of touch detection wirings TDW are representatively described.

[0120] The display device DSP1 is a sensor-equipped display device having a touch panel function for detecting an input position using a change in electrostatic capacitance in a sensor region overlapping the display region DA. Figure 1 The display area DA shown includes a sensor area as a detection device having a touch panel function for detecting changes in electrostatic capacitance. Figure 5 As shown in FIG. 1 , the display device DSP1 has a plurality of electrodes CE separated from each other. The plurality of electrodes CE are arranged in a matrix in the X direction and the Y direction in the display area DA. Each electrode CE is schematically represented in a rectangular or square shape in a plan view. As described above, the electrode CE is formed by a conductor layer CL4, for example, made of a conductive material having visible light transmittance such as ITO. Figure 5As shown, the plurality of electrodes CE are arranged in a matrix in the display area DA in the X direction and the Y direction. The plurality of electrodes CE function as contact electrodes for detecting that a dielectric such as a finger contacts or approaches a part of the display area DA. That is, the display device DSP1 of this embodiment has a plurality of electrodes (touch detection electrodes) CE arranged in the display area DA.

[0121] A connection circuit MP is provided on the short side of the peripheral area PFA. In addition, a touch detection circuit (detection control circuit) DP for controlling the touch panel function is provided on the short side of the peripheral area PFA. The touch detection circuit DP is formed, for example, Figure 1 The semiconductor device SCP (see Figure 2 ). The connection circuit MP and the detection circuit DP are electrically connected via a plurality of touch detection wirings TDW. The configuration of the connection circuit MP and the detection circuit DP is not limited to Figure 5 In the example shown, for example, the connection circuit MP and the detection circuit DP may be provided on the substrate 10 of the display device DSP1. In addition, the connection circuit MP may be a built-in circuit formed on the substrate 10, or may be formed on a driver IC (for example, a driver IC) mounted on the substrate 10. Figure 2 Alternatively, in the terminal area TMA (refer to Figure 1 ) is connected to a flexible wiring board not shown in the figure, a connection circuit MP and a detection circuit DP may be provided on a control substrate or a flexible wiring board outside the module.

[0122] The electrode CE is electrically connected to the detection circuit DP via the wiring MW3, the connecting circuit MP and the touch detection wiring TDW. The wiring MW3 and the touch detection wiring TDW supply a driving signal to the electrode CE, and transmit a signal corresponding to the change in electrostatic capacitance to the analog front end. For example, the driving circuit built into the detection circuit DP is connected to the plurality of electrodes CE respectively via the touch detection wiring TDW, the connecting circuit MP and the wiring MW3 configured in the peripheral area PFA. In the present embodiment, the plurality of wirings MW3 and the plurality of touch detection wirings TDW are distinguished as follows. That is, the plurality of wirings MW3 are wirings for touch detection formed in the display area DA. On the other hand, the plurality of touch detection wirings TDW are wirings for touch detection formed in the peripheral area PFA. The plurality of wirings MW3 and the plurality of touch detection wirings TDW are electrically connected via the connecting circuit MP. The plurality of wirings MW3 extend respectively along the Y direction, and the plurality of wirings MW3 are arranged in the X direction.

[0123] The detection circuit DP includes a circuit for supplying a drive signal for detecting a change in electrostatic capacitance during the detection period of the touch panel function operation of the display device DSP1, and a circuit for receiving a detection signal output from the electrode CE. The connection circuit MP is provided between the electrode CE and the detection circuit DP. The connection circuit MP is a circuit for switching the connection and disconnection between the electrode CE as the object of detection drive and the detection circuit DP based on a control signal supplied from the detection circuit DP. The connection circuit MP has an analog front end.

[0124] exist Figure 4 The insulating film 15 shown in the figure has an opening (contact hole) not shown in the figure formed at a position where the electrode CE overlaps with the wiring MW3, and the electrode CE and the wiring MW3 are electrically connected via the opening. Figure 5 In the example shown, one wiring MW3 is electrically connected to one electrode CE. However, one electrode CE may be electrically connected to a plurality of wirings MW3. In this case, a bundle of a plurality of wirings MW3 connected to one electrode CE constitutes a transmission path for a drive signal and a detection signal for touch detection.

[0125] In the case of the display device DSP1, the liquid crystal layer LQ (see Figure 2 ) is driven to display an image, and the detection period is driven to detect the input position by driving the electrode CE. During the display period, the electrode CE acts as a common electrode. Therefore, during the display period, a common potential for forming an electric field for driving the liquid crystal layer LQ is supplied to the plurality of electrodes CE arranged in the range of a plurality of pixels. In other words, during the display period, a fixed potential (for example, the first potential) is supplied to the plurality of touch detection wirings TDW, the plurality of wirings MW3 and the plurality of electrodes CE, respectively. In addition, the electrode CE acts as a driving electrode for detecting the input position in the sensor area during the detection period. Therefore, during the detection period, a driving signal for detecting the input position is input from the detection circuit DP to the electrode CE. In addition, the electrode CE acts as a detection electrode for detecting the input position in the sensor area during the detection period. Therefore, during the detection period, the electrode CE outputs a detection signal corresponding to the input driving signal.

[0126] The detection signal from the electrode CE changes according to the influence of the electrostatic capacitance around the electrode CE. When an input tool such as a finger approaches the vicinity of one of the multiple electrodes CE, the electrostatic capacitance around the electrode CE changes due to the influence of the input tool. In this case, the detection signal output from the electrode CE close to the input tool becomes a waveform different from the detection signals output from the other electrodes CE. The detection circuit DP receives the detection signals supplied from the multiple electrodes CE respectively, and determines the input position based on these detection signals.

[0127] In the case of the electrode CE of this embodiment, it has both the function of a driving electrode to which a driving signal is supplied and the function of a detection electrode to which a detection signal is output. However, as a modification, the driving electrode and the detection electrode may be provided separately. For example, when the electrode CE is used as a driving electrode, the detection electrode may be provided separately from the electrode CE.

[0128] <Signal selection circuit>

[0129] Then configure Figure 1 The signal selection circuit in the switching circuit area ASWA shown is explained. Figure 6 It is a schematic representation of the configuration in Figure 1 FIG. 1 is an explanatory diagram of the operation of the signal selection circuit in the switch circuit area shown in FIG. 1. In the present embodiment, the plurality of image signal lines SL and the plurality of image signal wirings VSW are distinguished as follows. That is, the plurality of image signal lines SL are wirings for image signal transmission formed in the display area DA. On the other hand, the plurality of image signal wirings VSW are wirings for image signal transmission formed in the peripheral area PFA. The plurality of image signal lines SL and the plurality of image signal wirings VSW are connected via Figure 6 The signal selection circuit ASW shown is electrically connected.

[0130] like Figure 6 As shown in FIG. 1 , a plurality of signal selection circuits ASW are arranged in the switch circuit area ASWA. The signal selection circuit ASW includes a plurality of ( Figure 6 In the example shown, there are three switching elements. The plurality of switching elements provided in the signal selection circuit ASW are connected to the video signal lines SL, respectively. Figure 6 In the example shown, the signal selection circuit ASW composed of three sets of switch elements is connected to three video signal lines SL. On the other hand, one signal selection circuit ASW is connected to one video signal wiring VSW.

[0131] The signal selection circuit ASW selects each of the three switch elements in turn based on the signal selection signal ASWS input from the image signal driving circuit SD, and sets them to the conducting (ON) state. When one of the three switch elements is turned on, the other two switch elements are turned off (OFF). The image signal VS (refer to Figure 3 ) is transmitted to one of the three video signal lines SL via the switch element that has become the on state. Since the three switch elements are sequentially turned on, the video signal VS is sequentially supplied to the three video signal lines SL.

[0132] In this way, by interposing the signal selection circuit ASW between the video signal line SL in the display area DA and the video signal wiring VSW in the peripheral wiring area PFWA, the video signal wiring VSW arranged in the peripheral wiring area PFWA can be reduced. Figure 6 As shown in FIG. 1 , the number of the plurality of video signal wirings VSW is less than the number of the plurality of video signal lines SL. Figure 6 In the example shown, the number of the plurality of video signal wirings VSW is 1 / 3 of the number of the plurality of video signal lines SL. By reducing the number of wirings arranged in the peripheral wiring area PFWA, the Figure 1 The area of ​​the peripheral region PFA is shown.

[0133] <Noise Countermeasures>

[0134] As described above, the signal selection circuit ASW has the advantage of being able to reduce the area of ​​the peripheral area PFA, but the inventors of the present invention have found that the electromagnetic waves generated by the switching operation of the signal selection circuit ASW may become noise. As a use of the display device DSP1, there is a case where it is used as a portable terminal device having a wireless communication function with an external device. For example, in Figure 2 In the example shown, the display device includes a display module DM including substrates 10 and 20, and a communication module TMM having a wireless communication function. If the electromagnetic waves generated by the switching operation of the signal selection circuit ASW interfere with the frequency band of the wireless communication performed by the communication module TMM, it becomes noise for the wireless communication. Therefore, the inventors of the present invention have studied a technology for suppressing the generation of electromagnetic waves accompanied by the switching operation of the signal selection circuit ASW, or the diffusion of the generated electromagnetic waves.

[0135] Figure 6 The reason why electromagnetic waves accompanying the switching action of the signal selection circuit ASW shown in the figure are particularly easy to be generated is that the image signal wiring VSW is arranged in the peripheral wiring area PFWA. Therefore, the inventors of the present invention have studied a method of taking noise countermeasures around multiple image signal wirings VSW. As a result of the study, it was found that by configuring a conductor pattern that is capacitively coupled with multiple image signal wirings VSW around multiple image signal wirings VSW, it is possible to suppress the generation of electromagnetic waves accompanying the switching action of the signal selection circuit ASW, or the diffusion of the generated electromagnetic waves. Figure 7 The concept of the noise countermeasure in this embodiment will be described.

[0136] Figure 7 Yes means Figure 1 An enlarged cross-sectional view of an example of a noise countermeasure in the peripheral wiring area shown in FIG. Figure 7, a circuit symbol of a capacitor is used to schematically illustrate a state in which a conductor pattern formed in the wiring layer WL1 and a conductor pattern formed in the wiring layer WL2 are capacitively coupled.

[0137] like Figure 7 As shown, the peripheral wiring area PFWA includes an insulating layer 31 on the substrate 10, a wiring layer WL1 on the insulating layer 31, an insulating layer 32 located on the insulating layer 31 and covering the wiring layer WL1, and a wiring layer WL2 on the insulating layer 32. The insulating layer 31 is, for example, Figure 4 The inorganic insulating film shown is composed of a stacked film of insulating film 11, insulating film 12 and insulating film 13. The insulating layer 32 is, for example, Figure 4 The insulating film 14 shown in FIG. 1 corresponds to an organic insulating film (planarizing film). The insulating layer 33 is, for example, Figure 4 The insulating film 15 shown corresponds to an organic insulating film. Figure 4 The conductive layer CL2 shown corresponds to the wiring layer WL2. Figure 4 The conductive layer CL3 shown corresponds to .

[0138] like Figure 7 As shown in FIG. 1 , a plurality of video signal wirings VSW are arranged in the wiring layer WL1. A plurality of touch detection wirings TDW and a conductor pattern CCP are formed in the wiring layer WL2. Figure 6 During the display period when the signal selection circuit ASW shown in the figure operates, a fixed potential (for example, a potential that is the same as the common potential supplied to the touch detection wiring TDW) is supplied to the conductor pattern CCP. In addition, the conductor pattern CCP is arranged at a position overlapping with a part of the plurality of image signal wirings VSW, and is capacitively coupled with a part of the plurality of image signal wirings VSW.

[0139] like Figure 7 As shown in FIG. 1 , another portion of the plurality of image signal wirings VSW (hereinafter referred to as other portion) overlaps with the touch detection wiring TDW. As described above, the touch detection wiring TDW is used as a signal to the touch detection wiring TDW during the display period. Figure 5 The plurality of electrodes CE shown in FIG. 1 are respectively provided with transmission paths for common potential. Figure 6 During the display period when the signal selection circuit ASW shown in the figure operates, a common potential is supplied to the touch detection wiring TDW. Therefore, when a noise current flows through the image signal wiring VSW capacitively coupled to the touch detection wiring TDW among the plurality of image signal wirings VSW, the noise component can be reduced by the decoupling function of the capacitor coupled to the image signal wiring VSW through which the noise current flows.

[0140] However, the number of touch detection wirings TDW is less than the number of image signal wirings VSW. In other words, the number of image signal wirings VSW is greater than the number of touch detection wirings TDW. Therefore, not all image signal wirings VSW overlap with touch detection wirings TDW. Therefore, in this embodiment, by configuring a conductor pattern CCP at a position that overlaps with an image signal wiring VSW that is configured at a position that does not overlap with the touch detection wiring TDW among a plurality of image signal wirings VSW, it is possible to reduce the noise component flowing in each of the plurality of image signal wirings VSW. Figure 7 The conductor pattern CCP shown in FIG. 1 is capacitively coupled to a portion of the plurality of video signal wirings VSW and is Figure 6 The signal selection circuit ASW shown in the figure is supplied with a fixed potential during the display period when the signal selection circuit ASW operates. Thus, when a noise current flows through the image signal wiring VSW capacitively coupled to the conductor pattern CCP, the noise component can be reduced by the decoupling function of the capacitor coupled to the image signal wiring VSW through which the noise current flows.

[0141] There are various forms of the shape of the conductor pattern CCP as a noise countermeasure. Hereinafter, several regions are given as examples of regions where the conductor pattern CCP should be arranged, and a preferred form of the conductor pattern CCP in each region is described. Figure 8 yes Figure 1 An enlarged plan view of section B is shown. Figure 8 Although it is a plan view, in order to facilitate observation of the range in which the touch detection wiring TDW and the image signal wiring VSW are configured and the extending direction of the touch detection wiring TDW and the image signal wiring VSW, the touch detection wiring TDW and the image signal wiring VSW and the conductor pattern CCP are shaded respectively.

[0142] like Figure 8As shown, the peripheral wiring area PFWA can be classified into multiple areas according to the presence or extension direction of the touch detection wiring TDW and the image signal wiring VSW. The peripheral wiring area PFWA includes a wiring area R1 where multiple image signal wirings VSW extend in directions inclined relative to the X direction and the Y direction. The peripheral wiring area PFWA includes a wiring area R2 located between the terminal area TMA and the wiring area R1 in the Y direction and where multiple image signal wirings VSW extend in the Y direction. The peripheral wiring area PFWA includes a wiring area R3 located between the edge 10s1 and the wiring area R1 in the Y direction and where multiple image signal wirings VSW are not configured. In addition, the wiring area R7 described later is also located between the edge 10s1 and the wiring area R1 in the Y direction like the wiring area R3, and multiple image signal wirings VSW are not configured. However, in this embodiment, the wiring area R3 and the wiring area R7 are distinguished and described. In addition, the peripheral wiring area PFWA includes a wiring area R9 in the wiring area R1 where multiple touch detection wirings TDW are not configured. In the wiring area R9, noise easily spreads from multiple image signal wirings VSW. Therefore, it is preferable that in the wiring area R9, a conductor pattern CCP as a noise countermeasure generated from the image signal wiring VSW is configured at a position overlapping with the multiple image signal wirings VSW. Next to the wiring area R9, there is a wiring area R3 where multiple image signal wirings VSW and multiple touch detection wirings TDW are not configured. The conductor pattern CCP1 is configured in a manner that crosses the boundary line of the wiring area R3 and the wiring area R1 (more specifically, the wiring area R9). In other words, the conductor pattern CCP includes the conductor pattern CCP1 configured in a manner that crosses the boundary line of the wiring area R3 and the wiring area R1. As a result, the generation of noise from the multiple image signal wirings VSW configured in the wiring area R9 can be reduced.

[0143] The above structure can also be expressed as follows. That is, the peripheral wiring area PFWA includes a wiring area R9 in the wiring area R1 where the plurality of touch detection wirings TDW are not configured. The plurality of conductor patterns CCP include a conductor pattern CCP1 configured in the wiring area R9. In the case of this expression, in addition to the case where the conductor pattern CCP1 is configured across the wiring area R3 and the wiring area R9, it also includes the case where the conductor pattern CCP1 is configured in the wiring area R9 and is not configured in the wiring area R3.

[0144] In addition, the peripheral wiring area PFWA includes a wiring area R4 in the wiring area R2 in which a plurality of touch detection wirings TDW are arranged adjacent to each other in the wiring layer WL2. The peripheral wiring area PFWA includes a wiring area R5 and a wiring area R6 in the wiring area R2 in which a plurality of touch detection wirings TDW are not arranged and which are located between the wiring area R1 and the terminal area TMA in the Y direction. In the X direction, the wiring area R4 is located between the wiring area R5 and the wiring area R6. In other words, in the X direction, the wiring area R5 and the wiring area R6 are located on opposite sides of each other, sandwiching the wiring area R4. The wiring area R5 and the wiring area R6 are respectively areas in which a plurality of image signal wirings VSW are arranged and in which the touch detection wiring TDW is not arranged. Therefore, it is preferred that, in each of the wiring area R5 and the wiring area R6, a conductor pattern CCP2 as a noise countermeasure generated from the image signal wiring VSW is arranged at a position overlapping with the plurality of image signal wirings VSW. Figure 8 In the illustrated example, the conductor pattern CCP includes conductor patterns CCP2 arranged in the wiring region R5 and the wiring region R6 .

[0145] In addition, the peripheral wiring area PFWA includes a wiring area R7 located next to the wiring area R6 in the X direction and between the side 10s1 and the wiring area R1 in the Y direction, and in which a plurality of image signal wirings VSW are not configured. In the wiring area R7, the image signal wiring VSW and the touch detection wiring TDW are not configured. In addition, the peripheral wiring area PFWA includes a wiring area R10 in the wiring area R1 in which a plurality of touch detection wirings TDW are not configured. In the wiring area R10, as in the wiring area R9, noise is easily diffused from the plurality of image signal wirings VSW. Therefore, it is preferable that in the wiring area R10, a conductor pattern CCP as a noise countermeasure generated from the image signal wiring VSW is configured at a position overlapping with the plurality of image signal wirings VSW. Next to the wiring area R10, there is a wiring area R7 in which a plurality of image signal wirings VSW and a plurality of touch detection wirings TDW are not configured. The conductor pattern CCP3 is configured in a manner that straddles the boundary line between the wiring area R7 and the wiring area R1 (specifically, the wiring area R10). In other words, the conductor pattern CCP includes the conductor pattern CCP3 arranged so as to straddle the boundary line between the wiring region R7 and the wiring region R1 . This can reduce the generation of noise from the plurality of video signal wirings VSW arranged in the wiring region R10 .

[0146] The above-mentioned structure of the wiring area R10 can also be expressed as follows. That is, the peripheral wiring area PFWA includes a wiring area R8 in the wiring area R1 where multiple touch detection wirings TDW extend in the Y direction. The peripheral wiring area PFWA includes a wiring area R9 and a wiring area R10 in the wiring area R1 where multiple touch detection wirings TDW are not configured. In a plan view, the wiring area R8 is configured between the wiring area R9 and the wiring area R10. The multiple conductor patterns CCP include a conductor pattern CCP3 configured in the wiring area R10. In the case of this expression, in addition to the case where the conductor pattern CCP3 is configured across the wiring area R7 and the wiring area R10, it also includes the case where the conductor pattern CCP3 is configured in the wiring area R10 and is not configured in the wiring area R7.

[0147] In addition, the peripheral wiring area PFWA includes a wiring area R4 in the wiring area R2, in which a plurality of touch detection wirings TDW are arranged adjacent to each other in the wiring layer WL2. The peripheral wiring area PFWA includes a wiring area R8 in the wiring area R1, in which a plurality of touch detection wirings TDW extend in the Y direction. In the wiring area R4 and the wiring area R8, the plurality of touch detection wirings TDW extend in the Y direction respectively, so the distance between adjacent touch detection wirings TDW is large. Therefore, from the viewpoint of suppressing the generation of noise from a portion of the plurality of image signal wirings VSW arranged in the gap between adjacent touch detection wirings TDW, it is preferred to configure a conductor pattern CCP in this portion. Figure 8 In the example shown, the conductor pattern CCP4 is arranged so as to straddle the boundary line between the wiring region R4 and the wiring region R8. In other words, the conductor pattern CCP includes a plurality of conductor patterns CCP4 arranged so as to straddle the boundary line between the wiring region R4 and the wiring region R8. Thus, the generation of noise from the plurality of image signal wirings VSW arranged in the wiring region R4 and the wiring region R8 can be reduced.

[0148] In addition, the peripheral wiring area PFWA includes a wiring area R11 in which a plurality of touch detection wirings TDW extend in directions inclined relative to the X direction and the Y direction, respectively, in the wiring area R1. In the area where the extension direction of the touch detection wiring TDW is inclined relative to the X direction and the Y direction, respectively, the distance between adjacent touch detection wirings TDW becomes smaller than that in the area (for example, the wiring area R4 and the wiring area R8) where the plurality of touch detection wirings TDW extend in the Y direction. Therefore, no conductor pattern CCP is configured between adjacent touch detection wirings TDW. In the wiring area R10, even if the conductor pattern CCP is not configured, since most of the plurality of image signal wirings VSW overlap with the touch detection wiring TDW, the risk of noise generation is relatively low.

[0149] In addition, Figure 8 In the example shown in FIG. 1 , a conductor pattern CCP is arranged in each of wiring region R4, wiring region R5, wiring region R6, wiring region R8, wiring region R9, and wiring region R10. However, as a modified example, Figure 8 The case where the conductor pattern CCP is arranged in one or more of the wiring regions R4, R5, R6, R8, R9, and R10 shown in the figure. In this case, in the wiring region where the conductor pattern CCP is arranged, the generation of noise from the plurality of image signal wirings VSW can be reduced.

[0150] <Wiring Areas R9 and R10>

[0151] Next, for the use Figure 8 The details of each wiring area described above will also be described in conjunction with the modified example. Fig. 9 Yes means Figure 8 FIG. 2 is an enlarged plan view of a modification of a portion of the wiring region (the periphery of the boundary between the wiring region R9 and the wiring region R3 ) shown. Fig. 9 Although it is a plan view, in order to facilitate identification of the touch detection wiring TDW and the video signal wiring VSW, the touch detection wiring TDW and the video signal wiring VSW, and the conductor pattern CCP are shaded.

[0152] exist Fig. 9 In the example shown, Figure 8 The conductor pattern CCP1 shown in the figure is different in that the conductor pattern CCP1 is formed into a plurality of elongated wiring patterns. The conductor pattern CCP includes a plurality of conductor patterns CCP1 extending in the Y direction in a manner that straddles the boundary line between the wiring region R3 and the wiring region R1. Figure 8 As shown, the conductor pattern CCP1 is a large-area conductor pattern CCP that is uniformly expanded in the wiring region R3 and the wiring region R9. Alternatively, although not shown, a mesh-shaped conductor pattern CCP may be used as the conductor pattern CCP1.

[0153] The plurality of conductor patterns CCP1 extend from the wiring region R3 in the Y direction. In addition, the plurality of conductor patterns CCP1 extend to the vicinity of the boundary between the wiring region R9 and the wiring region R11, but are not formed in the wiring region R11. The wiring region R11 is provided with a plurality of touch detection wirings TDW. In other words, the plurality of conductor patterns, in other words, the plurality of conductor patterns CCP1 extend to the vicinity of the touch detection wiring TDW.

[0154] In addition, if Fig. 9As shown in FIG. 1 , in the wiring region R3, a wiring VCW is arranged in the wiring layer WL1 along the boundary line between the wiring region R3 and the wiring region R1. The wiring (first potential wiring) VCW is used to Figure 1 The wiring of the peripheral area PFA electromagnetically shielded around the display area DA shown. The wiring VCW is arranged in the peripheral area PFA in a manner to surround the display area DA. In addition, a fixed potential is supplied to the wiring VCW during the above-mentioned display period and touch detection period. The plurality of conductor patterns CCP1 are electrically connected to each other via the wiring VCW. In this case, a fixed potential is supplied to the plurality of conductor patterns CCP1 via the wiring VCW. Therefore, by capacitively coupling the plurality of conductor patterns CCP1 with the plurality of image signal wirings VSW in the wiring area R9, the generation of noise from the plurality of image signal wirings VSW can be suppressed.

[0155] In addition, Figure 8 and Fig. 9 There are various variations of the method of supplying a fixed potential to the conductor pattern CCP1 shown. Fig. 9 By utilizing a wiring that is arranged for another purpose and supplied with a fixed potential, as in the wiring VCW shown in the figure, a fixed potential can be easily supplied to the conductor pattern CCP1.

[0156] also, Fig. 9 As Figure 8 The wiring area R9 shown in FIG. 1 is an enlarged plan view of the periphery of the boundary between the wiring area R3 and the wiring area R9. Figure 8 The wiring area R10 and the wiring area R7 shown in the figure can also be applied to the boundary area. In this case, in the description of this paragraph, the wiring area R9 can be renamed as the wiring area R10, the wiring area R3 can be renamed as the wiring area R7, and the conductor pattern CCP1 can be renamed as the conductor pattern CCP3 and applied. In addition, when the wiring VCW is configured in the wiring area R7, the conductor pattern CCP3 and the wiring VCW can be easily electrically connected. In addition, when the wiring VCW is not configured in the wiring area R7, it is preferred that a conductor pattern such as a wiring or an electrode to which a certain fixed potential is supplied at least during the display period is formed in the wiring area R7, and the conductor pattern is connected to the conductor pattern CCP3.

[0157] <Wiring Areas R4 and R8>

[0158] Next, Figure 8 The details of the structure around the wiring region R4 and the wiring region R8 shown will be described. Fig.10 Yes means Figure 8 FIG. 2 is an enlarged plan view of a modified example of another portion of the wiring region (the periphery of the boundary between the wiring region R4 and the wiring region R8 ). Fig.11 It means for Fig.10 An enlarged plan view of the study example. Fig.10 and Fig.11 Although each is a plan view, in order to facilitate identification of the touch detection wiring TDW and the video signal wiring VSW, the touch detection wiring TDW and the video signal wiring VSW are shaded.

[0159] As in Fig.11 As shown in the display device DSPc as a research example, when the wiring area R4 and the wiring area R8 are not subjected to noise countermeasures, the area of ​​the portion of the plurality of image signal wirings VSW that does not overlap with the touch detection wiring TDW is large. Therefore, from the viewpoint of suppressing the generation of noise from the portion of the plurality of image signal wirings VSW arranged in the gap between the adjacent touch detection wirings TDW, it is preferable to arrange the conductor pattern CCP in this portion (see Figure 8 or Fig.10 ).exist Fig.10 In the case of the display device DSP1 shown, a conductor pattern CCP4 is arranged between adjacent touch detection wirings TDW. The conductor pattern CCP4 is arranged so as to straddle the boundary between wiring region R4 and wiring region R8. This can reduce the generation of noise from a plurality of video signal wirings VSW arranged in wiring region R4 and wiring region R8.

[0160] In addition, Fig.10 In the example shown, a plurality of conductor patterns CCP4 are respectively formed in the wiring layer WL2. In addition, a plurality of conductor patterns CCP4 are respectively connected to one of a plurality of touch detection wirings TDW in the wiring layer WL2. In other words, one touch detection wiring TDW is branched into a plurality of conductive patterns CCP4. As described above, during the display period, a fixed potential (e.g., the first potential) is respectively supplied to a plurality of touch detection wirings TDW. When the conductor pattern CCP4 is electrically connected to the touch detection wiring TDW, a fixed potential is also supplied to the conductor pattern CCP4 during the display period. Therefore, even if the conductor pattern CCP4 is not connected to other fixed potential supply sources, it can be used as a pattern for noise countermeasures.

[0161] The location where the conductor pattern CCP4 is connected to the touch detection wiring TDW is not particularly limited. However, from the viewpoint of obtaining the noise countermeasure effect brought about by the conductor pattern CCP4, the conductor pattern CCP4 is preferably extended to Figure 8 The vicinity of the terminal area TMA is shown.

[0162] In addition, Fig.10In the example shown in FIG. 1 , in the wiring region R8, between two touch detection wirings TDW adjacent to each other among the plurality of touch detection wirings TDW, one or more conductor patterns CCP4 among the plurality of conductor patterns CCP4 are arranged (in Fig.10 There are two conductor patterns CCP4). However, the number of conductive patterns CCP4 and the thickness of the lines can be appropriately changed. For example, a thicker conductive pattern CCP4 or two or more thinner conductive patterns CCP4 can be used. In this case, the following effects can be obtained. Fig.10 When the conductor pattern CCP4 is electrically connected to the touch detection wiring TDW as in the example shown in FIG. 1 , it is necessary to consider the influence of the conductor pattern CCP4 on the false detection during the touch detection period. Figure 5 As the area of ​​the touch detection wire TDW in the peripheral wiring area PFWA increases, erroneous detection is more likely to occur. Therefore, from the perspective of reducing erroneous detection, it is preferable to reduce the area of ​​the touch detection wire TDW in the peripheral wiring area PFWA.

[0163] In such Fig.10 When the conductor pattern CCP4 is connected to the touch detection wiring TDW as shown, the conductor pattern CCP4 can be regarded as a part of the touch detection wiring TDW in the circuit. Therefore, from the perspective of reducing the area of ​​the conductor pattern CCP4 and making multiple image signal wirings VSW overlap in a large range, it is preferable to divide the conductor pattern CCP4 arranged between adjacent touch detection wirings TDW into multiple parts.

[0164] Of course, as for Fig.10 In a modification of the example shown in FIG. 1 , there is also a method in which the conductor pattern CCP4 is not connected to the touch detection wiring TDW, and a fixed potential is supplied to the conductor pattern CCP4 from a path different from the touch detection wiring TDW. Figure 8 As shown in FIG. 1 , even if a conductor pattern CCP4 having a width wider than the wiring width of the touch detection wiring TDW is arranged between adjacent touch detection wirings TDW, the occurrence of false detection can be suppressed. In addition, it is correct that it is preferable to reduce the area of ​​the touch detection wiring TDW in the peripheral wiring area PFWA in order to suppress the occurrence of false detection, but according to the setting conditions of the touch detection circuit, even in Figure 8 When the conductor pattern CCP4 shown in FIG. 1 is connected to the touch detection wiring TDW, there is also a case where no false detection occurs. Figure 8 The conductor pattern CCP4 shown is connected to the touch detection wiring TDW.

[0165] <Method of adding capacitors other than wiring layer WL2>

[0166] Next, it is explained that in addition to using Figure 7 to Figure 10 In addition to the noise countermeasures using the conductor pattern CCP described above, Figure 7 The method shown is a method in which a conductor pattern is arranged in a layer other than the wiring layer WL2 and capacitively coupled to a plurality of video signal wirings VSW. Fig.12 It means for Figure 7 An enlarged cross-sectional view of a modified example. Fig.13 It means for Figure 7 An enlarged cross-sectional view of another variation of . Fig.14 It means for Figure 7 An enlarged cross-sectional view of another variation of .

[0167] Fig.12 The display device DSP2 shown is similar to Figure 7 The display device DSP1 shown in FIG. 1 is different from the display device DSP2. That is, the peripheral wiring area PFWA of the display device DSP2 further includes a semiconductor film SCF formed between the substrate 10 and the wiring layer WL1. The semiconductor film SCF is arranged at a position overlapping with a part of the plurality of image signal wirings VSW, and is capacitively coupled with a part of the plurality of image signal wirings VSW. The semiconductor film SCF is composed of Figure 3 The channel layer of the transistor Tr1 shown is made of the same material as the semiconductor layer (not shown). The semiconductor film SCF is, for example, a film made of polycrystalline silicon and is disposed in a portion corresponding to the insulating film 11 and the insulating film 12. In addition, a fixed potential is supplied to the semiconductor film SCF. There is no limitation on the type of potential supplied to the semiconductor film SCF. For example, the semiconductor film SCF and the Fig. 9 The wiring VCW shown is electrically connected. Fig. 9 In the peripheral wiring area PFWA shown in FIG. 1 , a semiconductor film SCF supplied with a fixed potential is arranged at a position overlapping with a plurality of video signal wirings VSW. Fig.12 As schematically indicated by giving a circuit symbol of a capacitor in FIG. 1 , each of the plurality of image signal wirings VSW is capacitively coupled to the semiconductor film SCF. Thus, in the peripheral wiring area PFWA, noise generated from the plurality of image signal wirings VSW can be reduced. Fig.12 In the example shown, the semiconductor film SCF is formed in the entire peripheral wiring area PFWA, but there are various modifications of the shape of the semiconductor film SCF. For example, there is a case where the semiconductor film SCF is divided into a plurality of parts in the peripheral wiring area PFWA. In addition, the semiconductor film SCF is formed in the display area DA (see Figure 1 ) are electrically separated from the semiconductor layers in the semiconductor film. For example, the semiconductor film SCF is formed only in Figure 1 The peripheral area PFA shown is not formed in the display area DA.

[0168] also, Fig.13 The display device DSP3 shown is similar to Figure 7 The display device DSP1 shown in FIG. 1 is different from the display device DSP3. That is, the peripheral wiring area PFWA of the display device DSP3 further includes a conductive film CDF formed between the substrate 10 and the wiring layer WL1. The conductive film CDF is arranged at a position overlapping with a part of the plurality of image signal wirings VSW, and is capacitively coupled with a part of the plurality of image signal wirings VSW. The conductive film CDF is used, for example, to connect the peripheral area PFA (see Figure 1 ) A metal film used for a light-shielding film. In addition, a fixed potential is supplied to the conductor film CDF. There is no limitation on the type of potential supplied to the conductor film CDF. For example, the conductor film CDF and Fig. 9 The wiring VCW shown is electrically connected. Fig. 9 In the peripheral wiring area PFWA shown in FIG. 1 , a conductor film CDF supplied with a fixed potential is arranged at a position overlapping with a plurality of video signal wirings VSW. Fig.13 As schematically indicated by giving a circuit symbol of a capacitor in FIG. 1 , each of the plurality of image signal wirings VSW is capacitively coupled to the conductor film CDF. Thus, in the peripheral wiring area PFWA, noise generated from the plurality of image signal wirings VSW can be reduced. Fig.13 In the example shown, the conductor film CDF is formed in the entire peripheral wiring area PFWA, but there are various modifications to the shape of the conductor film CDF. For example, there is a case where the conductor film CDF is divided into a plurality of parts in the peripheral wiring area PFWA. In addition, for example, the conductor film CDF is formed only in Figure 1 The peripheral area PFA shown is not formed in the display area DA.

[0169] also, Fig.14 The display device DSP6 shown is similar to Figure 7 The display device DSP1 shown is different. That is, Fig.14 The insulating layer 32h shown is Figure 7 The thickness of the insulating layer 32 shown in FIG. 32 is different. The thickness of the insulating layer 32h is formed thinner than the thickness of the insulating layer 32. The insulating layer 32h is equivalent to Figure 4 The insulating film 14 shown in the figure is an insulating film of an organic resin, but is formed thinner than the insulating film 14 in the display area DA and the insulating layer 32h in the peripheral area PFWA. By forming the insulating layer 32h thinner, when a noise current flows through the image signal wiring VSW that is capacitively coupled to the touch detection wiring TDW among the multiple image signal wirings VSW, the decoupling function of the capacitor coupled to the image signal wiring VSW through which the noise current flows can be made thinner. Figure 7 The insulating layer 32h is large, which can reduce the noise component. Figure 4 The thickness of the insulating layer 32h is preferably 1000 mm / s. Figure 4 The thickness of the insulating film 14 shown is approximately half.

[0170] like Fig.12 The display device DSP2 shown, Fig.13 The display device DSP3 shown, or Fig.14 As in the display device DSP6 shown in FIG. 1 , by using the conductor pattern formed in other layers in addition to the conductor pattern CCP formed in the wiring layer WL2 to couple with the plurality of image signal wirings VSW capacitively, the value of the capacitance coupled with the image signal wiring VSW can be increased. As a result, the noise suppression effect can be improved. Fig.12 and Fig.13 In the example shown, the Figure 8 The embodiment of the area corresponding to the wiring area R4 and the wiring area R8 shown in the figure. Fig.12 and Fig.13 The variation shown is for Figure 8 The wiring region R9, wiring region R10, wiring region R11, etc. shown in the figure can also be applied.

[0171] Fig.12 The display device DSP2 shown in FIG. Fig.13 The display device DSP3 shown in the figure is different from the display device DSP3 shown in the figure in the figure. Figures 1 to 10 The display device DSP1 described above is the same, so duplicate descriptions will be omitted.

[0172] Next, the increase in utilization Figure 7 The circuit symbol of the capacitor shown schematically represents another way of expressing the value of capacitance. Fig.15 Yes means Fig.10 An enlarged plan view of a modified example of multiple video signal wirings shown. Fig.16 Yes means Fig.10 An enlarged plan view of another modified example of the plurality of image signal wirings shown. Fig.15 and Fig.16 They are respectively Fig.10 An enlarged plan view of a portion corresponding to the wiring region R4 is shown.

[0173] Fig.15 The display device DSP4 and Fig.16 The display device DSP5 shown is respectively different from the following aspects Fig.10The display device DSP1 shown in FIG. 1 is different. That is, in the display device DSP4, in the wiring region R4, the wiring width W1 of each of the plurality of image signal wirings VSW is wider than the wiring width W2 of each of the plurality of image signal wirings VSW in the wiring region R8. In addition, in the display device DSP5, in the wiring region R4, the plurality of image signal wirings VSW are respectively meandered. The width (meaning width) W3 of the meandering portion of the image signal wiring VSW is wider than the wiring width W2 of each of the plurality of image signal wirings VSW in the wiring region R8.

[0174] exist Figure 7 The capacitance value of the capacitor schematically shown in becomes larger in proportion to the facing area of ​​the video signal wiring VSW and the conductor pattern CCP. Fig.15 The display device DSP4 and Fig.16 In the case of the display device DSP5 shown in FIG. 1 , the area of ​​the video signal wiring VSW is increased in the wiring region R4 to realize the connection between the video signal wiring VSW and the conductor pattern CCP (see FIG. 1 ). Figure 7 By increasing the value of the coupling capacitance formed between the video signal wiring VSW and the conductor pattern CCP, the noise suppression effect can be improved.

[0175] In addition, Fig.15 and Fig.16 In the example, the image signal wiring VSW and the conductor pattern CCP (see Figure 7 ) is shown as an example of a method for increasing the facing area, but there are other methods for increasing the facing area. Fig.15 and Fig.16 There are various other modifications. For example, the shape of the image signal wiring VSW may be a mesh pattern. Alternatively, there is also a shape of the image signal wiring VSW that is different from the Fig.10 The conductor pattern CCP4 shown has the same shape.

[0176] Fig.15 The display device DSP4 and Fig.16 The display device DSP5 shown in the figure is different from the one using Figures 1 to 10 The display device DSP1 described above is the same, so duplicate descriptions are omitted.

[0177] In the scope of the concept of the present invention, those skilled in the art can think of various variations and modifications, and it should be understood that these variations and modifications also belong to the scope of the present invention. For example, those skilled in the art appropriately add, delete or design changes the components of the above-mentioned embodiments, or add, omit or change the conditions of the processes, as long as they have the gist of the present invention, they are also included in the scope of the present invention.

[0178] Industrial Applicability

[0179] The present invention can be used in a display device.

Claims

1. A display device, characterized in that: have: A first substrate having a first side extending in a first direction and a second side located on the opposite side of the first side in a second direction orthogonal to the first direction; A display area is located between the first side and the second side in the second direction; A plurality of touch detection electrodes are arranged in a matrix in the display area in the first direction and the second direction; A switch circuit region is located between the first side and the display region in the second direction and is provided with a signal selection circuit; a peripheral wiring region, located between the first side and the switch circuit region in the second direction, and configured with a plurality of peripheral wirings, the plurality of peripheral wirings including a plurality of image signal wirings connected to the signal selection circuit and a plurality of touch detection wirings connected to the plurality of touch detection electrodes; as well as a terminal region located between the first side and the peripheral wiring region in the second direction and provided with a plurality of terminals electrically connected to the plurality of peripheral wirings; The above peripheral wiring area includes: A first insulating layer, located on the first substrate; A first wiring layer, located on the first insulating layer; a second insulating layer, located on the first insulating layer and covering the first wiring layer; and A second wiring layer, located on the second insulating layer; The plurality of image signal wirings are arranged in the first wiring layer; The plurality of touch detection wirings and a conductor pattern supplied with a first potential are formed in the second wiring layer; The conductor pattern is arranged at a position overlapping with a part of the plurality of image signal wirings, and is capacitively coupled with the part of the plurality of image signal wirings; In the display area, the plurality of touch detection electrodes are formed on the second insulating layer.

2. The display device according to claim 1, wherein: The number of the plurality of image signal wirings is greater than the number of the plurality of touch detection wirings; In the second wiring layer, a plurality of the conductor patterns to which the first potential is supplied are formed; The above peripheral wiring area includes: a first wiring region in which the plurality of image signal wirings extend in directions inclined with respect to the first direction and the second direction; a second wiring region located between the terminal region and the first wiring region in the second direction and in which the plurality of image signal wirings extend in the second direction; and a third wiring region located between the first side and the first wiring region in the second direction and in which the plurality of image signal wirings are not arranged; The plurality of conductor patterns include a first conductor pattern arranged so as to straddle a boundary line between the third wiring region and the first wiring region.

3. The display device according to claim 2, wherein: The plurality of conductor patterns include a plurality of first conductor patterns extending in the second direction so as to straddle a boundary line between the third wiring region and the first wiring region.

4. The display device according to claim 3, characterized in that In the third wiring region, a first potential wiring is arranged in the first wiring layer along a boundary line between the third wiring region and the first wiring region; The plurality of first conductor patterns are electrically connected to one another via the first potential wirings.

5. The display device according to claim 2, wherein: The above peripheral wiring area includes: a fourth wiring region in which the plurality of touch detection wirings are arranged adjacent to each other in the second wiring layer in the second wiring region; and a fifth wiring region and a sixth wiring region in the second wiring region, which are not provided with the plurality of touch detection wirings and are located between the first wiring region and the terminal region in the second direction; In the first direction, the fourth wiring region is located between the fifth wiring region and the sixth wiring region; The plurality of conductor patterns include second conductor patterns respectively arranged in the fifth wiring region and the sixth wiring region.

6. The display device according to claim 5, characterized in that The peripheral wiring area includes a seventh wiring area located next to the sixth wiring area in the first direction and between the first side and the first wiring area in the second direction, and where the plurality of image signal wirings are not arranged; The plurality of conductor patterns include a third conductor pattern extending in the second direction so as to straddle a boundary line between the seventh wiring region and the first wiring region.

7. The display device according to claim 2, wherein: The above peripheral wiring area includes: a fourth wiring region in which the plurality of touch detection wirings are arranged adjacent to each other in the second wiring layer in the second wiring region; and an eighth wiring region in the first wiring region, where the plurality of touch detection wirings extend in the second direction; The plurality of conductor patterns include a plurality of fourth conductor patterns arranged so as to straddle a boundary line between the fourth wiring region and the eighth wiring region.

8. The display device according to claim 7, characterized in that: The plurality of fourth conductor patterns are respectively electrically connected to any one of the plurality of touch detection wires.

9. The display device according to claim 8, wherein: In the eighth wiring region, two or more fourth conductor patterns among the plurality of fourth conductor patterns are arranged between two touch detection wires that are adjacent to each other among the plurality of touch detection wires.

10. The display device according to claim 1, wherein: The number of the plurality of image signal wirings is greater than the number of the plurality of touch detection wirings; In the second wiring layer, a plurality of the conductor patterns to which the first potential is supplied are formed; The above peripheral wiring area includes: a first wiring region in which the plurality of image signal wirings extend in directions inclined with respect to the first direction and the second direction; a second wiring region located between the terminal region and the first wiring region in the second direction and in which the plurality of image signal wirings extend in the second direction; and a ninth wiring region in the first wiring region where the plurality of touch detection wirings are not arranged; The plurality of conductor patterns include a first conductor pattern arranged in the ninth wiring region.

11. The display device according to claim 10, wherein: The number of the plurality of image signal wirings is greater than the number of the plurality of touch detection wirings; In the second wiring layer, a plurality of the conductor patterns to which the first potential is supplied are formed; The above peripheral wiring area also includes: an eighth wiring region in the first wiring region, where the plurality of touch detection wirings extend in the second direction; and a tenth wiring region in the first wiring region where the plurality of touch detection wirings are not arranged; The eighth wiring area is located between the ninth wiring area and the tenth wiring area; The plurality of conductor patterns include a second conductor pattern arranged in the tenth wiring region.

12. The display device according to any one of claims 1 to 11, characterized in that: The peripheral wiring region further comprises a semiconductor film formed between the first substrate and the first wiring layer; The semiconductor film is disposed at a position overlapping with a portion of the plurality of video signal wirings, and is capacitively coupled to the portion of the plurality of video signal wirings.

13. The display device according to any one of claims 1 to 11, characterized in that: The peripheral wiring region further comprises a conductor film formed between the first substrate and the first wiring layer; The conductive film is disposed at a position overlapping with a portion of the plurality of video signal wirings, and is capacitively coupled to the portion of the plurality of video signal wirings.

Images