Failure unit test method and device, storage medium and electronic equipment

Abstract

The present disclosure relates to a failed cell test method, a failed cell test device, a computer readable storage medium and an electronic device, and relates to the technical field of integrated circuits. The failed cell test method comprises: writing test data into a storage array of a memory; sending a target word line jump instruction to the memory to control the storage array to open a word line surrounding a target word line; sending a refresh instruction to the memory to control the storage array to perform a refresh operation on the word line surrounding the target word line; reading data in the target word line, and comparing the read data with the test data written in the target word line to determine a failed cell in the storage array. A test method for effectively detecting a failed cell is provided.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular, to a failed cell testing method, a failed cell testing device, a computer readable storage medium and an electronic device. BACKGROUND

[0002] Dynamic Random Access Memory (DRAM) is a commonly used semiconductor memory device in computers, and has been widely used in the computer field and electronic industry due to its simple structure, high density, low power consumption, low price and other advantages.

[0003] In a cell to cell test between storage array units of a DRAM product, a potential voltage difference can be used to test cell leakage to detect chips with potential risks.

[0004] However, as time goes on, the potential voltage difference between cells will decrease, and the detection effect of the failed cell leakage will also decrease.

[0005] It should be noted that the information disclosed in the above background section is only used to strengthen the understanding of the background of the present disclosure, and therefore can include information that does not constitute prior art known to those of ordinary skill in the art. SUMMARY

[0006] The purpose of the present disclosure is to provide a failed cell testing method, a failed cell testing device, a computer readable storage medium and an electronic device, and to provide an effective test method for detecting failed cells.

[0007] Other characteristics and advantages of the present disclosure will become apparent from the following detailed description, or will be learned by practice of the present disclosure.

[0008] According to a first aspect of the present disclosure, a failed cell testing method is provided, the method comprising: writing test data into a storage array of a memory; sending a target word line jump instruction to the memory to control the storage array to open word lines around the target word line; sending a refresh instruction to the memory to control the storage array to perform a refresh operation on the word lines around the target word line; reading data in the target word line and comparing the read data with the test data written in the target word line to determine a failed cell in the storage array.

[0009] In an example embodiment of the present disclosure, the sending the target word line jump instruction to the memory to control the memory array to open the word lines surrounding the target word line includes: sending the target word line jump instruction to a row decoder of the memory, the row decoder being configured to decode the word lines surrounding the target word line according to the target word line jump instruction to obtain a surrounding word line decoding address; and sending the surrounding word line decoding address to a word line driver through the row decoder, the word line driver being configured to open the word lines surrounding the target word line in the memory array according to the surrounding word line decoding address.

[0010] In an example embodiment of the present disclosure, the sending the target word line jump instruction to the row decoder of the memory includes: writing the target word line jump instruction to a memory controller; and sending the target word line jump instruction to the row decoder through the memory controller.

[0011] In an example embodiment of the present disclosure, the sending the refresh instruction to the memory to control the memory array to perform a refresh operation on the word lines surrounding the target word line includes: sending the refresh instruction to a memory controller through a processor, the memory controller being configured to control the memory array to perform a refresh operation on the opened word lines surrounding the target word line according to the refresh instruction.

[0012] In an example embodiment of the present disclosure, the comparing the read data with the test data written in the target word line to determine the failed cell in the memory array includes: determining flipped data in the target word line according to a comparison result of the read data and the test data; and determining the failed cell in the target word line according to a storage cell where the flipped data is located.

[0013] In an example embodiment of the present disclosure, the writing test data into the memory array of the memory includes: writing data 0 into the target word line and writing data 1 into the word lines surrounding the target word line.

[0014] In an example embodiment of the present disclosure, the row decoder is configured to decode the word lines surrounding the target word line according to the target word line jump instruction to obtain a surrounding word line decoding address, including: the row decoder being configured to control a preset address line of the memory to be at a corresponding potential according to the target word line jump instruction, and not to decode a corresponding target word line according to the preset address line at the corresponding potential.

[0015] In an example embodiment of the present disclosure, the method further comprises: when the target word line is an odd number word line, controlling preset address lines of the memory to be at high potential by the target word line jump instruction, so as to control the row decoder to not resolve the odd number word line.

[0016] In an example embodiment of the present disclosure, the method further comprises: when the target word line is an even number word line, controlling preset address lines of the memory to be at low potential by the target word line jump instruction, so as to control the row decoder to not resolve the even number word line.

[0017] In an example embodiment of the present disclosure, the controlling the storage array to open word lines around the target word line comprises: when the target word line is one word line in a plurality of continuous word lines, opening the rest of the word lines except the target word line.

[0018] In an example embodiment of the present disclosure, the method further comprises: when the target word line is one word line in a plurality of continuous word lines, controlling a plurality of preset address lines of the memory to be at corresponding potential by the target word line jump instruction, so as to control the row decoder to resolve only the rest of the word lines except the target word line.

[0019] In an example embodiment of the present disclosure, the method further comprises: when the target word line is one word line in four continuous word lines, controlling a first address line and a second address line of the memory to be at low potential at the same time by the target word line jump instruction, so as to control the row decoder to skip the target word line and directly resolve a next word line of the target word line.

[0020] According to a second aspect of the present disclosure, there is provided a failed cell testing device, comprising: a data writing module configured to write test data into a storage array of a memory; a word line opening module configured to send a target word line jump instruction to the memory, so as to control the storage array to open word lines around the target word line; a refreshing module configured to send a refreshing instruction to the memory, so as to control the storage array to perform a refreshing operation on the word lines around the target word line; and a failed cell determining module configured to read data in the target word line, and compare the read data with the test data written in the target word line, so as to determine a failed cell in the storage array.

[0021] According to a third aspect of the present disclosure, there is provided a computer readable storage medium having a computer program stored thereon, wherein the computer program is executed by a processor to implement the failed cell testing method described above.

[0022] According to a fourth aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to perform the above-mentioned failed cell test method via executing the executable instructions.

[0023] The technical solutions provided by the present disclosure can include the following beneficial effects:

[0024] In the exemplary embodiments of the present disclosure, by writing test data into the storage array of the memory, leakage can be generated between the target word line and the word lines in the periphery of the target word line. Then, by sending a target word line jump instruction to the memory, the storage array can be controlled to only open the word lines in the periphery of the target word line. Thus, when sending a refresh instruction to the memory, the storage array can be controlled to only perform refresh operations on the word lines in the periphery of the target word line. By refreshing the word lines in the periphery of the target word line, the leakage capability of the word lines in the periphery of the target word line to the target word line can be increased, thereby facilitating the flipping of the test data written in the failed storage cells in the target word line, and further facilitating the detection of the failed cells by comparing the read data with the test data originally written in the target word line after reading the data in the target word line. Thus, the effectiveness of the failed cell test can be improved.

[0025] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and are not limiting to the present disclosure. BRIEF DESCRIPTION OF DRAWINGS

[0026] The accompanying drawings, which are incorporated into and form a part of the specification, illustrate an embodiment consistent with the present disclosure and, together with the description, serve to explain the principles of the disclosure. Obviously, the drawings in the following description are only some embodiments of the present disclosure, and other drawings can be obtained by those skilled in the art without creative labor on the basis of these drawings. In the drawings:

[0027] Figure 1 A structural schematic diagram of a storage cell according to an exemplary embodiment of the present disclosure is schematically shown;

[0028] Figure 2 A structural schematic diagram of a storage array according to an exemplary embodiment of the present disclosure is schematically shown;

[0029] Figure 3 A networking schematic diagram of a memory system according to an exemplary embodiment of the present disclosure is schematically shown;

[0030] Figure 4 A step flowchart of a failed cell test method according to an exemplary embodiment of the present disclosure is schematically shown;

[0031] Figure 5 Fig. 1 schematically illustrates an internal structure diagram of a memory according to an example embodiment of the present disclosure;

[0032] Figure 6 Fig. 2 schematically illustrates a structure diagram of a refresh target word line peripheral word line according to an example embodiment of the present disclosure;

[0033] Figure 7 Fig. 3 schematically illustrates another structure diagram of a refresh target word line peripheral word line according to an example embodiment of the present disclosure;

[0034] Figure 8 Fig. 4 schematically illustrates a block diagram of a failed cell test apparatus according to an example embodiment of the present disclosure;

[0035] Figure 9 Fig. 5 schematically illustrates a module diagram of an electronic device according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] Example embodiments now will be described more fully hereinafter with reference to the accompanying drawings. Example embodiments, may, however, be implemented in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the example embodiments to those skilled in the art. Like reference numerals refer to like elements throughout the figures, and descriptions of the same elements will not be repeated.

[0037] Moreover, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided to give a thorough understanding of embodiments of the disclosure. One skilled in the relevant art will recognize, however, that the embodiments of the disclosure can be practiced without one or more of the specific details, or

[0038] The block diagrams in the drawings show only the functionality of the embodiments and do not imply that the functions must be implemented in a specific order or that they must be implemented in every possible implementation. In addition, the block diagrams do not show the various internal components of the devices that implement the functionality. For the sake of presentation, the detailed description uses cross-referencing between features. However, it is to be understood that the features can be combined in any suitable manner. In addition, the various illustrative blocks are not necessarily implemented in the order indicated in the figures. Furthermore, these illustrative blocks are not necessarily implemented in the same manner or order as they are presented in the figures.

[0039] Semiconductor memory is used in computers, servers, hand-held devices such as mobile phones, printers, and many other electronic devices and applications. Semiconductor memory includes a plurality of memory cells in a memory array, each memory cell storing at least one bit of information. DRAM is an example of such semiconductor memory. The present solution is preferably used in DRAM. Thus, the following embodiments are described with reference to DRAM as a non-limiting example.

[0040] In a DRAM integrated circuit device, an array of memory cells is typically arranged in rows and columns such that a particular memory cell can be addressed by specifying its row and column of the array. In a read operation, a corresponding sense amplifier is selected to enable the output of data in the memory cell.

[0041] Referring to Figure 1 , each memory cell 100 in a DRAM typically includes a capacitor 110, a transistor 120, a word line (WL) 130, and a bit line (BL) 140, the gate of the transistor 120 is connected to the word line 130, the drain of the transistor 120 is connected to the bit line 140, the source of the transistor 120 is connected to the capacitor 110, a voltage signal on the word line 130 can control the opening or closing of the transistor 120, and then the data information stored in the capacitor 110 is read through the bit line 140, or the data information is written into the capacitor 110 through the bit line 140 for storage.

[0042] For a memory array, it is typically composed of a plurality of memory cells, referring to Figure 2 , a bit line BL corresponds to a plurality of spaced-apart word lines WL. The word line WL can control the opening and closing of the corresponding transistor 120. When there is a leakage in the memory cell cell composed of the word line 130, the bit line 140 and the transistor 120, the electrons stored in the memory cell cell will leak out through the weak point, resulting in distortion of the potential stored in the memory cell cell.

[0043] Generally, the leakage of the memory cell cell refers to the leakage of the charge in the memory cell cell to the adjacent memory cell. For example, during the packaging process, deformation may occur due to high temperature, which may cause the adjacent two memory cells to be shorted together or very close, resulting in a larger leakage path between the two memory cells and a higher probability of failure of the two memory cells.

[0044] Generally, as time goes on, the ability of the leakage from the failed cell to the adjacent memory cell will become weaker, and if a refresh operation is performed at this time, the data in the failed cell will also be refreshed to the original value, resulting in the failure to effectively screen out the failed cell.

[0045] Based on this, the disclosure example embodiment provides a failed cell test method.

[0046] Although the following description focuses on DRAM devices, those skilled in the art will appreciate that the claimed disclosure can be implemented to support any memory device type that requires multiple cells to be refreshed or otherwise maintained at intervals to preserve their contents. Those skilled in the art will also appreciate that although the following description focuses on memory devices in which the storage cells are organized in a two-dimensional row-column array, the storage cells can be organized in a variety of ways, including organized into multiple banks with or without interleaving, organized into arrays of more than two dimensions, organized to be content-addressable, and so on. In addition, although at least a portion of the following discussion focuses on memory within a computer system, those skilled in the art will appreciate that the claimed disclosure can be implemented in conjunction with other electronic devices or systems having memory devices.

[0047] Reference Figure 3 A networking diagram of a memory system provided by an embodiment of the disclosure is shown. As shown in Figure 3 The memory system 300 includes a processor 310, a memory controller 320, and a memory 330. The processor 310 reads and writes data in the memory 330 through the memory controller 320.

[0048] Generally, the refresh instruction can be sent directly by the memory controller 320 to the memory 330 and control the memory 330 to perform the refresh operation. The memory access instruction is sent by the processor 310 to the memory controller 320, and then sent by the memory controller 320 to the memory 330 for execution. The memory controller 320 controls the execution order of the refresh instruction and the memory access instruction. Generally, when performing the refresh operation, the memory controller 320 will pause sending the memory access instruction to the memory 330. Only after the refresh operation is completed, the received memory access instruction will be sent to the memory 330 for memory access operation.

[0049] The processor 310 and the memory controller 320 can be integrated in the same chip or implemented by two different chips when implemented. Generally, a storage space in the memory 330 is pre-set as a refresh data space 331. The refresh data space 331 can be a continuous area or multiple scattered areas. The operating system cannot use these memory areas when allocating memory for the application program.

[0050] In actual application, the memory 330 can be implemented by a DRAM chip. When the memory 330 is implemented by a DRAM chip, the memory controller 320 can be implemented by a DRAM controller.

[0051] Reference Figure 4 The diagram illustrates a flowchart of a failure unit testing method according to an embodiment of the present disclosure. In one feasible implementation, the failure unit testing method may include:

[0052] Step S410: Write test data into the memory array;

[0053] Step S420: Send a target word line switching instruction to the memory to control the memory array to open the word lines around the target word line;

[0054] Step S430: Send a refresh command to the memory to control the memory array to perform a refresh operation on the word lines surrounding the target word line;

[0055] Step S440: Read the data in the target word line and compare the read data with the test data written in the target word line to determine the failed cells in the storage array.

[0056] The failure cell testing method provided in this disclosure creates leakage current between the target word line and its surrounding word lines by writing test data into the memory array. Then, by sending a target word line switching instruction to the memory, the memory array can be controlled to only open the word lines surrounding the target word line. This allows the memory array to perform refresh operations only on the word lines surrounding the target word line when a refresh instruction is sent. Refreshing the word lines surrounding the target word line increases the leakage current capability from the surrounding word lines to the target word line, thus facilitating the flipping of test data written into the failed memory cell in the target word line. After reading the data in the target word line, the failed cell in the memory array can be determined by comparing the read data with the previously written test data in the target word line, which is beneficial for failure cell detection and improves the effectiveness of failure cell testing.

[0057] The failure unit testing method will be described in detail below with reference to specific implementation methods:

[0058] In step S410, test data is written to the memory array.

[0059] In the exemplary embodiments of this disclosure, after the system platform starts up and the operating system is loaded, the environment for accessing the memory is available, and at this time, access operations can be performed on the data addresses in the memory.

[0060] In practical applications, accessing a data address in the memory refers to reading data from the memory (Read) or writing data into the memory (Write). This can be achieved by sending a memory access instruction, i.e., sending a read command or a write command. The memory access instruction is sent by the processor 310 to the memory controller 320, which then sends it to the memory 330 for execution.

[0061] In the process of writing test data into the memory array in the exemplary embodiments of the present disclosure, data "0" can be written into the target word line, and data "1" can be written into the word lines surrounding the target word line, so that the charges in the storage cells on the word lines surrounding the target word line can leak into the storage cells on the target word line through the leakage paths, thereby facilitating the data flipping of the failed storage cells on the target word line for subsequent determination of the failed cells. For example, when the target word line is an even word line (even WL), data "0" can be written into the even word line, and data "1" can be written into the odd word line (odd WL), so that the charges in the storage cells on the odd word line can leak into the storage cells on the even word line through the leakage paths, thereby facilitating the data flipping of the failed storage cells on the even word line. Similarly, when the target word line is an odd word line, data "1" can be written into the odd word line, and data "0" can be written into the even word line, so that the charges in the storage cells on the even word line can leak into the storage cells on the odd word line through the leakage paths, thereby facilitating the data flipping of the failed storage cells on the odd word line.

[0062] In addition, when the target word line is one of a plurality of consecutive word lines, data "0" can be written into the target word line, and data "1" can be written into the remaining word lines of the plurality of consecutive word lines, so that the charges in the storage cells on the remaining word lines can leak into the storage cells on the target word line through the leakage paths, thereby facilitating the data flipping of the failed storage cells on the target word line for subsequent determination of the failed cells.

[0063] In step S420, a target word line jump instruction is sent to the memory to control the memory array to open the word lines surrounding the target word line.

[0064] In the exemplary embodiments of this disclosure, the target word line skip instruction refers to an instruction that skips the target word line and only opens the word lines surrounding the target word line. For example, when the target word line is an even-numbered word line, the target word line skip instruction is an instruction to skip even-numbered word lines (skip even WL) and open odd-numbered word lines; when the target word line is an odd-numbered word line, the target word line skip instruction is an instruction to skip odd-numbered word lines (skip odd WL) and open even-numbered word lines; when the target word line is one of multiple consecutive word lines, the target word line skip instruction is an instruction to skip the target word line and open the remaining word lines among the multiple consecutive word lines. For example, when the target word line is one of four consecutive word lines, the target word line skip instruction is the skip 1 / 4WL instruction.

[0065] exist Figure 3 Based on the memory system shown, referring to Figure 5 The diagram illustrates the internal structure of a memory according to an embodiment of this disclosure. Figure 3 As shown, the memory system 300 includes: a processor 310, a memory controller 320, and a memory 330. And... Figure 5 In this memory, 330 includes a row decoder 331, a word line driver 332, a memory array 333, and an address latch 334. The input of the row decoder 331 is connected to the output of the memory controller 320. The output of the row decoder 331 is connected to the input of the word line driver 332. The output of the word line driver 332 is connected to the memory array 333, which can also be directly connected to the memory controller 320. Additionally, the output of the address latch 334 is connected to the input of the row decoder 331.

[0066] In an exemplary embodiment of this disclosure, during the process of sending a target word line transition instruction to the memory to control the memory array to open the word lines surrounding the target word line, the first step is to write the target word line transition instruction to the memory controller 320. This target word line transition instruction is equivalent to a row decoding control signal. After writing the target word line transition instruction to the memory controller 320, the memory controller 320 can send the target word line transition instruction to the row decoder 331. Upon receiving the target word line transition instruction, the row decoder 331 will decode the word lines surrounding the target word line in the memory array according to the target word line transition instruction to obtain the surrounding word line decoding address. This is equivalent to decoding the odd-numbered word lines when the target word line is an even-numbered word line to obtain the odd-numbered word line decoding address; decoding the even-numbered word lines when the target word line is an odd-numbered word line to obtain the even-numbered word line decoding address; and decoding the remaining word lines (excluding the target word line) when the target word line is one of multiple consecutive word lines to obtain the decoding addresses of the remaining word lines.

[0067] After obtaining the peripheral word line decode address, the peripheral word line decode address can be sent to the word line driver 332 through the row decoder 331, and the word line driver 332 can open the word lines surrounding the target word line in the storage array according to the peripheral word line decode address.

[0068] In the exemplary embodiments of the present disclosure, in the process of decoding the word lines surrounding the target word line in the storage array according to the target word line jump instruction to obtain the peripheral word line decode address, the preset address line of the memory can be controlled to be at a corresponding potential through the row decode control signal of the target word line jump instruction, and the row decoder will not parse the corresponding target word line according to the preset address line at the corresponding potential, thereby achieving the purpose of only parsing the word lines surrounding the target word line to obtain the peripheral word line decode address.

[0069] Generally, the address lines A0-A N are temporarily stored in the address latch 334, and the address lines A0-A Figure 5 It can be seen that the address latch 334 is connected to the row decoder 331, and the row decoder 331 can call the address lines A0-A N signals temporarily stored in the address latch 334, and control the preset address line to be at a corresponding potential according to the target word line jump instruction, and then parse the corresponding target word line according to the preset address line at the corresponding potential.

[0070] In actual applications, for example, when the target word line is an odd number word line, the preset address line of the memory, such as the address line A0, can be controlled to be at a high potential through the target word line jump instruction, so as to control the row decoder 331 not to parse the odd number word line, thereby achieving the purpose of only parsing the even number word line; however, when the target word line is an even number word line, the preset address line of the memory, such as the address line A0, can be controlled to be at a low potential through the target word line jump instruction, so as to control the row decoder 331 not to parse the even number word line, thereby achieving the purpose of only parsing the odd number word line.

[0071] In the example embodiment of the present disclosure, when the target word line is one of a plurality of continuous word lines, the plurality of preset address lines of the memory can be controlled to be at a corresponding potential by the target word line jump instruction, so as to control the row decoder to only analyze the remaining word lines except the target word line, thereby achieving the purpose of not analyzing the target word line. For example, when the target word line is one of four continuous word lines, the first address line and the second address line of the memory can be controlled to be at a low potential at the same time by the target word line jump instruction, so as to control the row decoder to skip the target word line and directly analyze the next word line of the target word line, wherein the first address line can be A0, the second address line can be A1, etc. Controlling the first address line and the second address line to be at a low potential at the same time is only an example, and the first address line and the second address line can also be controlled to be at a high potential at the same time or other conditions, which are not specially limited in the example embodiment of the present disclosure.

[0072] In step S430, a refresh instruction is sent to the memory to control the memory array to perform a refresh operation on the word lines around the target word line.

[0073] Generally, DRAM mainly stores data by using the charge in the capacitor. With the continuous improvement of the manufacturing precision of DRAM, the integration of each component in DRAM is also increasing, which may interfere with the adjacent memory cells when reading and writing a certain memory cell in DRAM. The current will flow into or out of the adjacent memory cells, that is, the charge in the capacitor will continuously lose due to the existence of leakage, so that the DRAM can only maintain the data for a very short time. Therefore, the data in the capacitor must be read out and rewritten regularly to compensate for the lost charge, which is called refresh. Through refresh, the data loss in the memory cell can be prevented.

[0074] DRAM is usually composed of a plurality of banks, and each bank is a two-dimensional memory array, which is transversely called a row and longitudinally called a column. In the refresh process, DRAM selects a row (also called a memory row) each time, extracts all the data of the row to a sense amplifier (also called a row buffer), which is called an active operation; then the corresponding data is read and written in the row buffer, and the data in the row buffer is rewritten to the memory array, which is called a pre-charge operation. Through the active operation and the pre-charge operation, the entire refresh process is realized.

[0075] The refresh operation is similar to the read operation, but no data is output. After the read amplifier reads out the data in the memory cell, a recovery operation is performed to make the data be rewritten to the memory cell. Therefore, the data is “refreshed”. The refresh operation is performed by starting the word line according to the row address and starting the read amplifier.

[0076] For DRAM, the general refresh instruction includes two kinds: Auto Refresh (AR) and Self Refresh (SR); wherein, SR is to refresh the whole array in sequence continuously after obtaining the refresh instruction, and AR can set the refresh interval and automatically refresh according to the refresh interval.

[0077] During the operation of the DRAM chip, when the self-refresh SR entry instruction is received, the chip automatically performs the refresh operation periodically. During the self-refresh SR, the reception of other commands sent to the chip is interrupted, and the refresh is performed. After the self-refresh SR exit instruction is received, the chip is allowed to receive and execute other commands. For the auto-refresh AR, multiple refreshes are performed under the control of the auto-refresh AR instruction, and the number of rows refreshed each time is limited. Usually, the whole array needs to be refreshed multiple times to refresh the whole array once. For example, the whole array has 100 rows, and the number of rows refreshed by AR each time is 4 rows. Therefore, 25 auto-refreshes are required to refresh the whole array.

[0078] Generally, the above general refresh instruction is stored in the memory controller, and the memory is directly controlled by the memory controller to execute the above general refresh instruction.

[0079] In the exemplary embodiment of the present disclosure, the refresh instruction is an external refresh instruction, which is sent to the memory controller 320 by the processor 310. After receiving the refresh instruction, the memory controller 320 controls the memory array 333 to perform the refresh operation only on the word lines around the target word line to be opened, and does not perform the refresh on the target word line, so as to maintain or increase the leakage capability of the storage units on the word lines around the target word line to the storage units on the target word line, increase the possibility of data flipping of the failed storage units on the target word line, and improve the effectiveness of the failed unit detection.

[0080] The external refresh instruction provided by the exemplary embodiment of the present disclosure specifically performs the refresh process as the above general refresh instruction, that is, includes the activation operation and the pre-charge operation. As shown in Figure 6 When the target word line is the odd word line 1, 3, 5, 7, the even word line 0, 2, 4, 6 is refreshed; as shown in Figure 7 When the target word line is one of the four continuous word lines, for example, when the target word line is the word line 0 in the word lines 0, 1, 2, 3, only the word lines 1, 2, 3 can be refreshed; when the target word line is the word line 4 in the word lines 4, 5, 6, 7, only the word lines 5, 6, 7 can be refreshed.

[0081] In step S440, data in the target word line is read, and the read data is compared with the test data written in the target word line to determine the failed cell in the storage array.

[0082] In the exemplary embodiment of the present disclosure, the data of the storage cells in the target word line can be read after a preset time of performing the refresh operation on the word lines around the target word line. Specifically, the data of the storage cells in the target word line can be read by sending a read command to the memory, which will not be described herein.

[0083] After the data of the storage cells in the target word line is read, the read data can be compared with the test data originally written in the storage cells, and the flipped data in the target word line can be determined according to the comparison result of the read data and the test data. The failed storage cell in the target word line can be determined according to the storage cell where the flipped data is located. For example, if the data "0" is written in each storage cell of the target word line, the storage cell whose data is changed to "1" can be determined as the failed storage cell when the data of each storage cell in the target word line is read.

[0084] In summary, the failed cell test method provided by the embodiment of the present disclosure can write test data in the storage array of the memory, for example, write data "0" in each storage cell of the target word line and write data "1" in each storage cell of the word line around the target word line, so that the electric charges of each storage cell of the word line around the target word line can leak to the storage cells of the target word line through the leakage path. Then, the target word line jump instruction can be sent to the memory to control the storage array to only open the word line around the target word line. Thus, the refresh operation can be performed on the word line around the target word line when the refresh instruction is sent to the memory. The refresh operation on the word line around the target word line can increase the leakage ability of the storage cells of the word line around the target word line to the storage cells of the target word line, which is conducive to the flipping of the test data written in the failed storage cell of the target word line. Then, the data of the storage cells in the target word line can be read, and the failed cell in the storage array can be determined by comparing the read data with the test data originally written in the target word line. Thus, the detection of the failed cell is facilitated, and the effectiveness of the failed cell test is improved.

[0085] It should be noted that although the steps of the method in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order or that all the steps shown must be performed to achieve the desired result. Additionally or alternatively, some steps can be omitted, multiple steps can be combined into one step, one step can be divided into multiple steps, and the like.

[0086] In addition, in the example embodiment, a failed cell testing device is also provided. Referring to Figure 8 The failed cell testing device 800 can include a data writing module 810, a word line opening module 820, a refresh module 830, and a failed cell determining module 840, wherein:

[0087] The data writing module 810 can be configured to write test data into a storage array of the memory;

[0088] The word line opening module 820 can be configured to send a target word line jump instruction to the memory to control the storage array to open word lines surrounding the target word line;

[0089] The refresh module 830 can be configured to send a refresh instruction to the memory to control the storage array to perform a refresh operation on the word lines surrounding the target word line;

[0090] The failed cell determining module 840 can be configured to read data in the target word line and compare the read data with the test data written in the target word line to determine a failed cell in the storage array.

[0091] In an example embodiment of the present disclosure, the word line opening module 820 can be configured to send the target word line jump instruction to a row decoder of the memory, the row decoder is configured to decode the word lines surrounding the target word line according to the target word line jump instruction to obtain a surrounding word line decoding address; and send the surrounding word line decoding address to a word line driver through the row decoder, the word line driver is configured to open the word lines surrounding the target word line in the storage array according to the surrounding word line decoding address.

[0092] In an example embodiment of the present disclosure, the word line opening module 820 can be configured to write the target word line jump instruction to a memory controller; and send the target word line jump instruction to a row decoder through the memory controller.

[0093] In an example embodiment of the present disclosure, the refresh module 830 can be configured to send the refresh instruction to a memory controller through a processor, and the memory controller is configured to control the storage array to perform the refresh operation on the opened word lines surrounding the target word line according to the refresh instruction.

[0094] In an example embodiment of the present disclosure, the failed cell determining module 840 can be configured to determine data in the target word line that has occurred flip according to a comparison result of the read data and the written test data; and determine a failed cell in the target word line according to a storage cell where the data has occurred flip.

[0095] In an example embodiment of the present disclosure, the data writing module 810 can be configured to write data 0 into the target word line and write data 1 into the word lines surrounding the target word line.

[0096] In an example embodiment of the present disclosure, the word line opening module 820 can be configured to control the preset address lines of the memory to be at corresponding potentials according to the target word line jump instruction, and control the row decoder not to resolve the corresponding target word line according to the preset address lines at the corresponding potentials.

[0097] In an example embodiment of the present disclosure, the word line opening module 820 can be configured to control the preset address lines of the memory to be at high potentials according to the target word line jump instruction when the target word line is an odd number word line, so as to control the row decoder not to resolve the odd number word line.

[0098] In an example embodiment of the present disclosure, the word line opening module 820 can be configured to control the preset address lines of the memory to be at low potentials according to the target word line jump instruction when the target word line is an even number word line, so as to control the row decoder not to resolve the even number word line.

[0099] In an example embodiment of the present disclosure, the word line opening module 820 can be configured to open the remaining word lines except the target word line when the target word line is one of the multiple continuous word lines.

[0100] In an example embodiment of the present disclosure, the word line opening module 820 can be configured to control the multiple preset address lines of the memory to be at corresponding potentials according to the target word line jump instruction when the target word line is one of the multiple continuous word lines, so as to control the row decoder to resolve only the remaining word lines except the target word line.

[0101] In an example embodiment of the present disclosure, the word line opening module 820 can be configured to control the first address line and the second address line of the memory to be at low potentials at the same time according to the target word line jump instruction when the target word line is one of the four continuous word lines, so as to control the row decoder to skip the target word line and directly resolve the next word line of the target word line.

[0102] The specific details of the virtual modules of each device side described above have been described in detail in the corresponding method side, and therefore, will not be described here.

[0103] It should be noted that although several modules or units of the device side are mentioned in the above detailed description, such division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. Conversely, the features and functions of one module or unit described above can be further divided into multiple modules or units.

[0104] In an example embodiment of the present disclosure, an electronic device capable of implementing the above method is also provided.

[0105] Those skilled in the art can understand that each aspect of the present application can be implemented as a system, a method or a program product. Therefore, each aspect of the present application can be specifically implemented as a complete hardware embodiment, a complete software embodiment (including firmware, microcode, etc.), or an embodiment combining hardware and software aspects, which can be collectively referred to as "circuitry", "module" or "system" here.

[0106] The electronic device 900 according to this embodiment of the present application will be described below with reference to Figure 9 Figure 9 The electronic device 900 is merely an example and should not impose any limitation on the functions and use range of the embodiments of the present application.

[0107] As shown in Figure 9 The electronic device 900 is in the form of a general computing device. The components of the electronic device 900 can include, but are not limited to, the at least one processing unit 910, the at least one storage unit 920, a bus 930 connecting different system components (including the storage unit 920 and the processing unit 910), and a display unit 940.

[0108] The storage unit 920 stores program code which can be executed by the processing unit 910, so that the processing unit 910 performs the steps according to various exemplary embodiments of the present application described in the "Exemplary Method" section of the present specification. For example, the processing unit 910 can perform the steps S410 of writing test data into a storage array of a memory, S420 of sending a target word line jump instruction to the memory to control the storage array to open word lines surrounding the target word line, S430 of sending a refresh instruction to the memory to control the storage array to perform a refresh operation on the word lines surrounding the target word line, and S440 of reading data in the target word line and comparing the read data with the test data written in the target word line to determine failed cells in the storage array, as shown in Figure 4

[0109] The storage unit 920 can include a readable medium in the form of a volatile storage unit, such as a random access memory (RAM) 9201 and / or a cache memory 9202, and can further include a read-only memory (ROM) 9203.

[0110] The storage unit 920 can further include a program / utility 9204 having a set of program modules 9205, including but not limited to an operating system, one or more application programs, other program modules, and program data, each of which can include implementation of a network environment or some combination thereof.

[0111] ​​Bus 930 can be one or more of several types of bus structure including a storage bus or a memory bus, a peripheral bus, a graphics bus, a processor or local bus using any of a variety of bus architectures including a memory, using a variety of bus architectures including Industry Standard Architecture (ISA), Micro Channel Architecture (MCA), Extended ISA (EISA), Advanced Graphics Port (AGP), Peripheral Component Interconnect (PCI), Peripheral Component Interconnect Extended (PCI-X), PCI Express, Video Electronics Standards Association (VESA), and the like.

[0112] Electronic device 900 can also communicate with one or more external devices 970 such as a keyboard or pointing device, a Bluetooth device, a camera, a printer, a scanner, or a networking device. Communication with one or more devices can occur via an input / output (I / O) interface 950. Still yet, electronic device 900 can communicate with one or more networks, such as a local area network (LAN), a general wide area network (WAN), or a public network such as the Internet, via a network adapter 960. As depicted, network adapter 960 communicates with the other components of electronic device 900 via bus 930. It should be appreciated that although not shown, other hardware and / or software components could be used in conjunction with electronic device 900. These include, but are not limited to, microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data archival storage systems, etc.

[0113] Those skilled in the art will readily understand that the example embodiments described herein can be implemented by software and / or by hardware coupled to software. Thus, the techniques that result from the embodiments of the present disclosure can be embodied in computer- readable storage medium (which can be a CD-ROM, a floppy disk, a USB drive, a hard disk drive, or a flash drive, for example), or in transmitted or received data signals, including carrier waves, that encode a sequence of instructions for executing on a processor to implement the described methods.

[0114] In the example embodiments of the present disclosure, a computer-readable storage medium is also provided, which stores a program product capable of implementing the method described above. In some possible embodiments, various aspects of the present disclosure can also be implemented in the form of a program product, which includes program codes for causing an end device to perform the steps described in the “Example Method” section above according to various example embodiments of the present disclosure when the program product is run on the end device.

[0115] A program product for implementing the above-described method according to the embodiments of the present application can take a portable compact disc read only memory (CD-ROM) and include a program code, and can be run on a terminal device such as a personal computer. However, the program product of the present application is not limited thereto, and in the present document, a readable storage medium can be any tangible medium that contains or stores a program that can be used by or in connection with an instruction execution system, apparatus, or device.

[0116] The program product can take any combination of one or more readable media. The readable media can be a readable signal medium or a readable storage medium. The readable storage medium, for example, can be, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include an electrical connection having one or more wires, a portable disc, a hard disk, a random access memory (RAM), a read only memory (ROM), an erasable programmable read only memory (EPROM or flash memory), an optical fiber, a portable compact disc read only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0117] The computer readable signal medium can include a data signal propagated in baseband or propagated as a carrier wave, in which the readable program code is embodied. Such propagated data signal can take multiple forms, including but not limited to an electromagnetic signal, an optical signal, or any suitable combination of the above. The readable signal medium can also be any readable medium that is not a readable storage medium and that can transmit, propagate, or transport the program for use by or in connection with an instruction execution system, apparatus, or device.

[0118] The program code contained on the readable medium can be transmitted using any suitable medium, including but not limited to wireless, wired, optical fiber, RF, and the like, or any suitable combination of the above.

[0119] The program code may be implemented in any of various ways, including procedure-based, narrative-based, object-based, and / or architectural-based versions. In procedure-based implementations, the program code is implemented in a series of isolated procedures, which rely primarily on extrinsic (or global) variables to communicate with one another. In narrative-based implementations, the program code is implemented at various levels by an interpreter or virtual machine. In object-based versions, the program code is implemented as a series of objects, which interact to perform the functionality of the present application. In architectural-based versions, the program code is implemented based on a component model, which organizes functionality into components that are interconnected to achieve the functionality of the present application.

[0120] Furthermore, the above-described diagrams are only schematic and are non-limiting. As such, the present application is intended to encompass all changes and modifications of the herein described methods which do not constitute departures from the true spirit and scope of the application. For example, the order of the steps of the methods can be modified, and the use of some steps can be eliminated, without departing from the true spirit and scope of the application. Also, it is understood that the steps of the methods can be performed in parallel, asynchronously, or in any order, unless otherwise indicated.

[0121] Other embodiments of the present disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the application disclosed herein. It is intended that the present disclosure cover any and all variations of the present disclosure which come within the scope of the claims and a concept of equivalents thereof. The specification and examples given are intended as illustrative only and not limiting of the true scope and spirit of the present disclosure.

[0122] It is to be understood that the present disclosure is not limited to the precise construction described and as shown in the attached drawings, and that various modifications and changes can be effected therein by those skilled in the art without departing from the scope of the application. The scope of the application is to be defined by the claims appended hereto.

Claims

1. A method for testing failed units, characterized in that, The method includes: Write test data into the memory array; Send a target word line transition instruction to the memory to control the memory array to open the word lines surrounding the target word line; Send a refresh command to the memory to control the memory array to perform a refresh operation on the word lines surrounding the target word line; Data in the target word line is read and compared with the test data written in the target word line to determine the failed cells in the storage array.

2. The method according to claim 1, characterized in that, Sending a target word line transition instruction to the memory to control the memory array to open word lines surrounding the target word line includes: The target word line transition instruction is sent to the row decoder of the memory. The row decoder is used to decode the word lines around the target word line according to the target word line transition instruction to obtain the decoding address of the surrounding word lines. The row decoder sends the peripheral word line decoding address to the word line driver, which is used to open the word line surrounding the target word line in the storage array according to the peripheral word line decoding address.

3. The method according to claim 2, characterized in that, The line decoder that sends the target word line transition instruction to the memory includes: Write the target word line transition instruction to the memory controller; The target word line transition instruction is sent to the line decoder via the memory controller.

4. The method according to claim 1, characterized in that, Sending a refresh command to the memory to control the memory array to perform a refresh operation on the word lines surrounding the target word line includes: The processor sends the refresh instruction to the memory controller, and the memory controller controls the memory array to perform a refresh operation on the word lines around the opened target word line according to the refresh instruction.

5. The method according to claim 1, characterized in that, The step of comparing the read data with the test data written in the target word line to determine the failed cells in the storage array includes: Based on the comparison between the read data and the written test data, the data that has been flipped in the target word line is determined; The failed cell in the target word line is determined based on the storage cell where the flipped data is located.

6. The method according to claim 1, characterized in that, Writing test data into the memory array includes: Write the data "0" into the target word line, and write the data "1" into the word lines surrounding the target word line.

7. The method according to claim 2, characterized in that, The line decoder is used to decode the word lines surrounding the target word line according to the target word line transition instruction, and obtain the decoding addresses of the surrounding word lines, including: The row decoder is used to control the preset address lines of the memory to be at the corresponding potential according to the target word line transition instruction, and to not parse the corresponding target word line according to the preset address lines at the corresponding potential.

8. The method according to claim 7, characterized in that, The method further includes: When the target word line is an odd number line, the preset address line of the memory is controlled to be at a high potential by the target word line transition instruction, so as to control the row decoder not to parse the odd number line.

9. The method according to claim 7, characterized in that, The method further includes: When the target word line is an even number line, the preset address line of the memory is controlled to be at a low potential by the target word line transition instruction, so as to control the row decoder not to parse the even number line.

10. The method according to claim 2, characterized in that, The control of the memory array to open the word lines surrounding the target word line includes: When the target character line is one of multiple consecutive character lines, open the remaining character lines except for the target character line.

11. The method according to claim 7, characterized in that, The method further includes: When the target word line is one of multiple consecutive word lines, the target word line transition instruction controls multiple preset address lines of the memory to be at corresponding potentials, so as to control the row decoder to only parse the remaining word lines other than the target word line.

12. The method according to claim 11, characterized in that, The method further includes: When the target word line is one of four consecutive word lines, the first address line and the second address line of the memory are simultaneously at a low potential by means of the target word line jump instruction, so as to control the row decoder to skip the target word line and directly parse the next word line of the target word line.

13. A failure unit testing device, characterized in that, The device includes: The data writing module is used to write test data into the storage array of the memory. A word line opening module is used to send a target word line transition instruction to the memory to control the memory array to open the word lines around the target word line; A refresh module is used to send refresh instructions to the memory to control the memory array to perform refresh operations on the word lines around the target word line; The failure cell determination module is used to read the data in the target word line and compare the read data with the test data written in the target word line to determine the failure cells in the storage array.

14. A computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the failure unit testing method according to any one of claims 1-12.

15. An electronic device, characterized in that, include: processor; as well as Memory for storing the executable instructions of the processor; The processor is configured to execute the failure unit testing method according to any one of claims 1-12 by executing the executable instructions.

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