A method for manufacturing a semiconductor device and a semiconductor device

Abstract

The application discloses a preparation method of a semiconductor device and the semiconductor device, and aims at reducing the leakage current of the semiconductor device. The preparation method of the semiconductor device provided by the embodiment of the application comprises the following steps: providing a substrate and forming a first dielectric layer on one side of the substrate; the substrate comprises an array area and a peripheral area outside the array area; forming an initial mask pattern on the side of the first dielectric layer away from the substrate; and adopting at least twice of a patterning process on the initial mask pattern, so as to form a first mask pattern in the array area and a second mask pattern in the peripheral area, wherein the first mask pattern has a first height, the second mask pattern has a second height, and the second height is greater than the first height; and each time of the patterning process is performed on the array area and the peripheral area.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and in particular to a method for preparing a semiconductor device and a semiconductor device. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a type of semiconductor memory widely used in many computer systems. As the feature sizes of semiconductor integrated circuit devices continue to shrink, the critical dimensions of DRAM are also shrinking, and the manufacturing process is becoming more complex, placing increasingly stringent demands on the electrical properties of semiconductor integrated circuit devices.

[0003] In the prior art, during the manufacturing process of semiconductor devices, the pattern of the periphery of the array area is usually obtained in a single-exposure graphic process. However, due to the optical proximity effect, the pattern of the periphery of the array area formed by a single exposure is prone to rounded corners, resulting in poor morphology of the pattern of the periphery of the array area and increased leakage current of the semiconductor device. Summary of the Invention

[0004] The embodiments of the present application provide a method for manufacturing a semiconductor device and a semiconductor device, so as to reduce leakage current of the semiconductor device.

[0005] An embodiment of the present application provides a method for manufacturing a semiconductor device, comprising:

[0006] Providing a substrate and forming a first dielectric layer on one side of the substrate; the substrate includes an array area and a peripheral area outside the array area;

[0007] forming an initial mask pattern on the first dielectric layer;

[0008] The initial mask pattern is subjected to at least two patterning processes to form a first mask pattern in the array area and a second mask pattern in the peripheral area, wherein the first mask pattern has a first height and the second mask pattern has a second height, which is greater than the first height; wherein each patterning process exposes the array area and the peripheral area.

[0009] In some embodiments, forming an initial mask pattern on a side of the first dielectric layer facing away from the substrate specifically includes:

[0010] forming a first mask layer on the first dielectric layer;

[0011] removing the first mask layer in the array area by a patterning process;

[0012] forming a second mask layer covering the array area and the peripheral area;

[0013] A graphic process is adopted to form an initial pattern of the array area on the second mask layer in the array area and retain the first mask layer and the second mask layer in the peripheral area to obtain an initial mask pattern.

[0014] In some embodiments, the thickness H1 of the second mask layer and the total thickness H2 of the first mask layer and the second mask layer in the peripheral region satisfy: H1 / H2 is greater than or equal to 1 / 4 and less than or equal to 3 / 4.

[0015] In some embodiments, the thickness of the second mask layer is equal to the first height;

[0016] The total thickness of the first mask layer and the second mask layer is equal to the second height.

[0017] In some embodiments, the material of the first mask layer and the material of the second mask layer are the same.

[0018] In some embodiments, the material of the first mask layer and the material of the second mask layer include polyethylene.

[0019] In some embodiments, the initial mask pattern is subjected to at least two patterning processes to form a first mask pattern in the array region and a second mask pattern in the peripheral region, specifically comprising:

[0020] Patterning the initial mask pattern using a first patterning process to form a first sub-mask pattern in the array region and a second sub-mask pattern in the peripheral region, wherein the first sub-mask pattern has a first height and the second sub-mask pattern has a second height;

[0021] The first sub-mask pattern and the second sub-mask pattern are patterned using a second patterning process to form a first mask pattern having a first height in the array area, and at the same time form a second mask pattern in the peripheral area, wherein the second mask pattern includes a stepped structure having a first plane and a second plane, the first plane has a second height, the second plane has a third height, and the third height is less than the second height.

[0022] In some embodiments, the sum of the third height H4 and the first height H5 is equal to the second height H3.

[0023] In some embodiments, the first height H5 and the second height H3 satisfy: H5 / H3 is greater than or equal to 1 / 4 and less than or equal to 3 / 4.

[0024] In some embodiments, the initial mask pattern of the array region includes a plurality of first patterns spaced apart along a first direction, the first patterns being continuous patterns in a second direction; the first direction and the second direction intersect;

[0025] The initial mask pattern of the peripheral region includes a second pattern that is continuous in the first direction and the second direction.

[0026] In some embodiments, patterning the initial mask pattern using a first patterning process to form a first sub-mask pattern in the array region and simultaneously forming a second sub-mask pattern in the peripheral region includes:

[0027] Patterning the initial mask pattern in the array area in the second direction to form first sub-mask patterns arranged at first intervals in the second direction;

[0028] The initial mask pattern of the peripheral area is patterned in the first direction or the second direction, and a portion of the initial mask pattern is removed in a direction perpendicular to the substrate to form a second sub-mask pattern with a height difference in the peripheral area, and the second sub-mask pattern does not expose the first dielectric layer of the peripheral area; wherein the second sub-mask pattern with the height difference has a first plane and a second plane.

[0029] In some embodiments, the initial mask pattern is patterned using a second patterning process to form a first sub-mask pattern in the array region and a second sub-mask pattern in the peripheral region, specifically including:

[0030] Performing patterning on the first sub-mask patterns in the array area in the second direction to form first mask patterns arranged at first intervals in the second direction;

[0031] The initial mask pattern in the peripheral area is patterned in the first direction or the second direction, and part of the second sub-mask pattern is removed in a direction perpendicular to the substrate to form a second mask pattern in the peripheral area, and the second mask pattern exposes part of the first dielectric layer in the peripheral area.

[0032] In some embodiments, the first patterning process specifically includes:

[0033] forming a third mask layer, a fourth mask layer and a photoresist in sequence on the initial mask pattern;

[0034] Applying an exposure and development process to the photoresist to form a first photoresist pattern;

[0035] forming a first covering layer on the first photoresist pattern, wherein the first covering layer covers the first photoresist pattern, sidewalls of the first photoresist pattern, and a portion of the fourth mask layer not covered by the first photoresist pattern, to form a first opening;

[0036] Using a dry etching process, the first cover layer, the fourth mask layer, the third mask layer, and the initial mask pattern in the first opening area are removed to form a first sub-mask pattern in the array area and a second sub-mask pattern in the peripheral area.

[0037] removing the remaining first covering layer, the first photoresist pattern, the fourth mask layer, and the third mask layer;

[0038] The second patterning process specifically includes:

[0039] forming a fifth mask layer, a sixth mask layer and a photoresist in sequence on the first sub-mask pattern and the second sub-mask pattern;

[0040] Applying an exposure and development process to the photoresist to form a second photoresist pattern;

[0041] forming a second covering layer on the second photoresist pattern, wherein the second covering layer covers the second photoresist pattern, sidewalls of the second photoresist pattern, and the sixth mask layer not covered by the photoresist pattern to form a second opening;

[0042] Using a dry etching process, the second covering layer, the sixth mask layer, the fifth mask layer, and the first sub-mask pattern or the second sub-mask pattern in the second opening area are removed, and the first mask pattern is formed in the array area, while the second mask pattern is formed in the peripheral area;

[0043] The remaining second covering layer, the pattern of the second photoresist, the sixth mask layer and the fifth mask layer are removed.

[0044] In some embodiments, the material of the third mask layer and the fifth mask layer includes a bottom anti-reflective coating;

[0045] The material of the fourth mask layer and the sixth mask layer includes silicon oxynitride;

[0046] The materials of the first cover layer and the second cover layer include silicon dioxide.

[0047] An embodiment of the present application provides a semiconductor device, which is manufactured using the method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0048] The semiconductor device and preparation method thereof provided in the embodiments of the present application obtain a complete mask pattern through at least two graphical processes including exposure, that is, the mask pattern in the peripheral area is split, and the complex mask pattern is split into several simple patterns for exposure in batches, thereby reducing the optical proximity effect, avoiding the appearance of rounded corners in the mask pattern in the peripheral area, and improving the morphology of the mask pattern in the peripheral area, thereby improving the production yield of the mask pattern in the peripheral area, and further reducing the leakage current of the semiconductor device. BRIEF DESCRIPTION OF THE DRAWINGS

[0049] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0050] Figure 1 A schematic flow chart of a method for manufacturing a semiconductor device according to an embodiment of the present application;

[0051] Figure 2 A schematic diagram of an initial mask pattern provided in an embodiment of the present application;

[0052] Figure 3 A schematic diagram of a process for forming an initial mask pattern at a cross section corresponding to AA' provided in an embodiment of the present application;

[0053] Figure 4 A schematic diagram of a process for forming an initial mask pattern at a cross section corresponding to BB' provided in an embodiment of the present application;

[0054] Figure 5 A schematic diagram of a process for forming an initial mask pattern at a cross section corresponding to CC' provided in an embodiment of the present application;

[0055] Figure 6 A schematic flow chart of step S1022 in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0056] Figures 7 to 9 A schematic flow chart of step S1024 in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0057] Figure 10 A schematic diagram of a first mask pattern provided in an embodiment of the present application;

[0058] Figures 11 to 13 A schematic flow chart of step S1031 in a method for manufacturing a semiconductor device provided in an embodiment of the present application;

[0059] Figures 14 to 16 This is a flow chart of step S1032 in a method for preparing a semiconductor device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0060] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions of the embodiments of the present application will be clearly and completely described below in conjunction with the drawings of the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. And in the absence of conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. Based on the described embodiments of the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0061] Unless otherwise defined, the technical or scientific terms used in this application should have the usual meaning understood by people with ordinary skills in the field to which this application belongs. The words "first", "second" and similar terms used in this application do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0062] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual scale and are only for the purpose of illustrating the contents of this application. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0063] The present invention provides a method for preparing a semiconductor device according to the present invention. Figure 1 Shown, including:

[0064] S101, providing a substrate and forming a first dielectric layer on one side of the substrate; the substrate includes an array area and a peripheral area outside the array area;

[0065] S102, forming an initial mask pattern on the first dielectric layer;

[0066] S103. Perform at least two patterning processes on the initial mask pattern to form a first mask pattern in the array area and a second mask pattern in the peripheral area, wherein the first mask pattern has a first height, and the second mask pattern has a second height, which is greater than the first height; wherein each patterning process exposes the array area and the peripheral area.

[0067] It should be noted that the optical proximity effect is caused by nonlinear spatial filtering during partially coherent imaging, which results in a certain distortion of the energy and phase distribution of the image intensity spectrum relative to the ideal image spectrum. This ultimately significantly reduces the imaging quality, triggering the optical proximity effect. The ideal image intensity spectrum distribution depends on the characteristic size, shape, and distribution of the lines on the mask. Corners or sharp lines contribute more high-frequency components to the spectrum. However, due to diffraction limitations, these high-frequency components cannot pass through the system to the corresponding corners of the actual aerial image plane. This inevitably leads to a mismatch in the light intensity distribution at the corners of the aerial image, causing rounding or distortion at the corners of the actual aerial image lines.

[0068] The method for preparing a semiconductor device provided in an embodiment of the present application obtains a complete mask pattern through at least two graphical processes including exposure, that is, the mask pattern in the peripheral area is split, and the complex mask pattern is split into several simple patterns for exposure in batches, thereby reducing the optical proximity effect, avoiding the appearance of rounded corners in the mask pattern in the peripheral area, and improving the morphology of the mask pattern in the peripheral area, thereby improving the yield of the mask pattern production in the peripheral area, and further reducing the leakage current of the semiconductor device.

[0069] It should be noted that in the semiconductor device preparation method provided in the embodiment of the present application, the initial mask pattern is patterned to form a first mask pattern and a second mask pattern. Subsequently, the first mask pattern and the second mask pattern can be used as masks to transfer the first mask pattern and the second mask pattern to the first dielectric layer and the substrate in sequence. The area on the substrate corresponding to the first mask pattern and the second mask pattern is the semiconductor active area, and the area outside the first mask pattern and the second mask pattern on the substrate is the conductor area, namely the source and drain contact area.

[0070] In some embodiments, step S101 forms a first dielectric layer on one side of the substrate. For example, step S101 deposits a first dielectric layer material to form the first dielectric layer.

[0071] In some embodiments, as Figure 2 、 Figure 3 、 Figure 4 、 Figure 5 As shown, forming an initial mask pattern on the side of the first dielectric layer facing away from the substrate specifically includes:

[0072] S1021, forming a first mask layer 5 on the first dielectric layer 4;

[0073] S1022, removing the first mask layer 5 of the array area 1 by a patterning process;

[0074] S1023, forming a second mask layer 31 covering the array area 1 and the peripheral area 2;

[0075] S1024 , using a patterning process, forming an initial array area pattern on the second mask layer 31 of the array area 1 and retaining the first mask layer 5 and the second mask layer 31 of the peripheral area 2 to obtain an initial mask pattern 6 .

[0076] It should be noted that Figure 2 For example, it can be the orthographic projection of the initial mask pattern on the substrate. Figure 3 The structure formed in step S1024 can be, for example, Figure 2 The cross-sectional view of AA', Figure 4 The structure formed in step S1024 can be, for example, Figure 2 The cross-section of BB', Figure 5The structure formed in step S1024 can be, for example, Figure 2 Cross-sectional view of CC'.

[0077] The method for preparing a semiconductor device provided in an embodiment of the present application removes the first mask layer in the array area after forming the first mask layer for the first time, and then forms a second mask layer covering the array area and the peripheral area. In this way, the thickness of the initial mask pattern in the peripheral area is greater than the thickness of the initial mask pattern in the array area, which facilitates the subsequent formation of the second mask pattern in the peripheral area through at least two patterning processes.

[0078] In some embodiments, after forming the first mask layer on the side of the first mask layer away from the first dielectric layer, the thickness H1 of the first mask layer in the array area and the total thickness H2 of the two first mask layers in the peripheral area satisfy: H1 / H2 is greater than or equal to 1 / 4 and less than or equal to 3 / 4.

[0079] In some embodiments, the thickness of the second mask layer is equal to the first height;

[0080] The total thickness of the first mask layer and the second mask layer is equal to the second height.

[0081] In some embodiments, the material of the first mask layer and the material of the second mask layer are the same.

[0082] In some embodiments, the material of the first mask layer and the material of the second mask layer include polyethylene (POLY).

[0083] In a specific implementation, for example, a deposition process can be used to form the first and second mask layers. Specifically, in step S1021, a first mask layer material can be deposited on the side of the first dielectric layer facing away from the substrate to form the first mask layer. In step S1023, a second mask layer material is deposited to form a second mask layer covering the array region and the peripheral region.

[0084] It should be noted that the patterning process includes, for example, steps such as photoresist coating, exposure, development, etching, and photoresist removal. Figure 6 As shown, step S1022 uses a patterning process to remove the first mask layer in the array area, specifically including:

[0085] S1022-1, depositing a photoresist 7 on the side of the first mask layer 5 facing away from the substrate 3;

[0086] S1022-2, forming a pattern of the photoresist 7 by using exposure and development processes;

[0087] S1022-3, remove the first mask layer 5 of the array area 1 by an etching process.

[0088] In some embodiments, as Figure 7 、 Figure 8 、 Figure 9 As shown, step S1024 uses a patterning process to form an initial pattern in the array area on the first mask layer in the array area and retain the first mask layer in the peripheral area, specifically including:

[0089] S1024-1, alternately depositing two groups of seventh mask layers 32 and eighth mask layers 33 on the side of the initial mask pattern 6 facing away from the substrate 3, and coating a photoresist 7 on the side of the uppermost eighth mask layer 33 facing away from the substrate 3;

[0090] S1024-2, using an exposure and development process to form a pattern of the photoresist 7, wherein the pattern of the photoresist 7 forms a plurality of third openings 10 in the photoresist 7 in the array region;

[0091] S1024-3, using the pattern of the photoresist 7 as a mask, sequentially etching a set of the eighth mask layer 33 and the seventh mask layer 32 near the photoresist 7 using an etching process to form a third mask pattern 16 in the array area 1, and removing the photoresist 7; wherein the third mask pattern 16 has a plurality of fourth openings 12;

[0092] S1024-4, depositing a third covering layer 34 covering the array area and the peripheral area, wherein the third covering layer 34 forms a fifth opening 13 in an area corresponding to the fourth opening 12;

[0093] S1024-5. In array area 1, an etching process is used to remove the third covering layer 34, the third mask pattern 16, and the set of eighth mask layers 33 and seventh mask layers 32 on the side of the third mask pattern 16 facing the substrate 3, except for the third covering layer 34 covering the sidewall portion of the third mask pattern 16. A fourth mask pattern 17 is formed on the set of eighth mask layers 33 and seventh mask layers 32 on the side of the third mask pattern 16 facing the substrate 3.

[0094] S1024-6, removing the third covering layer 34 on the fourth mask pattern 17 and the peripheral region 2, where the fourth mask pattern 17 has a sixth opening 14;

[0095] S1024-7, depositing a fourth covering layer 35 to form a seventh opening 15 in a region corresponding to the sixth opening 14;

[0096] S1024-8, using an etching process, remove the fourth cover layer 35 in the peripheral area 2 and a set of the eighth mask layer 33 and the seventh mask layer 32 adjacent to the fourth cover layer 35, and remove the fourth mask pattern 17 and the fourth cover layer 35 covering the fourth mask pattern 17 and the fourth cover layer 35 in the area of ​​the seventh opening 15. The fourth cover layer 35 covering the sidewalls of the fourth mask pattern 17 is retained in the array area 1 to form a fifth mask pattern 18.

[0097] S1024-9, using the fifth mask pattern 18 as a mask, an etching process is used to form an initial pattern of the array area on the first mask layer 5, and at the same time, an etching process is used to remove the eighth mask layer 33 and the seventh mask layer 32 of the peripheral area 2; then, the fifth mask pattern 18 of the array area is removed.

[0098] The method for preparing a semiconductor device provided in an embodiment of the present application alternately arranges multiple layers of the seventh mask layer and the eighth mask layer in sequence, and subsequently uses the first cover layer and the second cover layer to form an initial pattern of the array area in the array area using a pitch multiplication process. This can avoid the influence of exposure accuracy on the initial pattern of the array area, thereby realizing the production of small-size patterns and improving the production yield of the initial pattern of the array area.

[0099] It should be noted that the thickness of the eighth mask layer may be, for example, smaller than the thickness of the seventh mask layer. The first cover layer and the second cover layer may comprise the same material.

[0100] In some embodiments, step S103 and the initial mask pattern are patterned at least twice to form a first mask pattern in the array region and a second mask pattern in the peripheral region, specifically including:

[0101] S1031, patterning the initial mask pattern using a first patterning process to form a first sub-mask pattern in the array area and a second sub-mask pattern in the peripheral area, wherein the first sub-mask pattern has a first height and the second sub-mask pattern has a second height;

[0102] S1032. Use a second patterning process to pattern the first sub-mask pattern and the second sub-mask pattern to form a first mask pattern with a first height in the array area, and at the same time form a second mask pattern in the peripheral area, wherein the second mask pattern includes a stepped structure having a first plane and a second plane, the first plane has a second height, the second plane has a third height, and the third height is less than the second height.

[0103] The semiconductor device fabrication method provided in the embodiments of the present application forms a mask pattern in both the array region and the peripheral region during each patterning process of the initial mask pattern. That is, the peripheral region mask pattern is formed simultaneously with the array region mask pattern. By splitting the peripheral region mask pattern for multiple patterning processes, the process flow is streamlined to the greatest extent possible, thereby reducing manufacturing costs.

[0104] In some embodiments, the sum of the third height H4 and the first height H5 is equal to the second height H3.

[0105] In some embodiments, the first height H5 and the second height H3 satisfy: H5 / H3 is greater than or equal to 1 / 4 and less than or equal to 3 / 4.

[0106] In some embodiments, as Figure 2 As shown, the initial mask pattern of the array area 1 includes a plurality of first patterns 36 spaced apart along the first direction X, and the first pattern 36 is a continuous pattern in the second direction Y; the first direction X and the second direction Y intersect; for example, the first direction X and the second direction Y are perpendicular;

[0107] The initial mask pattern of the peripheral region 2 includes a second pattern 37 that is continuous in the first direction X and the second direction Y.

[0108] It should be noted that the semiconductor device manufacturing method provided in the embodiment itself requires two patterning processes to be performed on the array region. Figure 10 The first mask pattern shown, wherein Figure 2 Based on the initial mask pattern shown, the first patterning process removes Figure 10 The second mask layer of the first area 19 is formed to obtain a first sub-mask pattern, and the second patterning process removes the second mask layer of the second area 20 based on the first sub-mask pattern. Figure 10 Only part of the array area including the AA' and BB' regions is shown.

[0109] In some embodiments, step S1031 of patterning the initial mask pattern using a first patterning process to form a first sub-mask pattern in the array region and simultaneously forming a second sub-mask pattern in the peripheral region includes:

[0110] Patterning the initial mask pattern in the array region in the second direction to form first sub-mask patterns arranged at first intervals in the second direction;

[0111] An initial mask pattern in the peripheral area is patterned in a first direction or a second direction, and a portion of the initial mask pattern is removed in a direction perpendicular to the substrate to form a second sub-mask pattern with a height difference in the peripheral area, and the second sub-mask pattern does not expose the first dielectric layer of the peripheral area; wherein the second sub-mask pattern with a height difference includes a stepped structure having a first plane and a second plane.

[0112] In the array area, the first patterning process removes the initial mask pattern in the first area, disconnecting the first pattern in the first area and forming a first sub-mask pattern. In the peripheral area, the first patterning process removes part of the initial mask pattern and forms a second sub-mask pattern with a stepped structure having a first plane and a second plane in the peripheral area.

[0113] In some embodiments, step S1032 uses a second patterning process to pattern the initial mask pattern, forming a first sub-mask pattern in the array region and a second sub-mask pattern in the peripheral region, specifically including:

[0114] Performing patterning on the first sub-mask patterns in the array area in the second direction to form first mask patterns arranged at first intervals in the second direction;

[0115] The initial mask pattern in the peripheral area is patterned in the first direction or the second direction, and part of the second sub-mask pattern is removed in a direction perpendicular to the substrate to form a second mask pattern in the peripheral area, and the second mask pattern exposes part of the first dielectric layer in the peripheral area.

[0116] For the array region, the second patterning process removes the first sub-mask pattern in the second region, so that the first sub-mask pattern that is disconnected in the first region is disconnected in the second region, thereby obtaining the first mask pattern.

[0117] In some embodiments, as Figure 11 、 Figure 12 、 Figure 13 As shown, step S1031 adopts the first patterning process and specifically includes:

[0118] S1031-1, sequentially forming a third mask layer 8, a fourth mask layer 9 and a photoresist 7 on the initial mask pattern 6;

[0119] S1031-2, performing an exposure and development process on the photoresist 7 to form a first photoresist pattern 21;

[0120] S1031-3, forming a first covering layer 11 on the first photoresist pattern 21, the first covering layer 11 covers the first photoresist pattern 21, the sidewalls of the first photoresist pattern 21, and the fourth mask layer 9 not covered by the first photoresist pattern 21, to form a first opening 22;

[0121] S1031-4, using a dry etching process to remove the first covering layer 11, the fourth mask layer 9, the third mask layer 8, and the initial mask pattern 6 in the area of ​​the first opening 22, forming a first sub-mask pattern 23 in the array area 1, and simultaneously forming a second sub-mask pattern 24 in the peripheral area 2; the first sub-mask pattern 23 has a first height H5; the second sub-mask pattern 24 covers the first dielectric layer 4 in the peripheral area, and the second sub-mask pattern 24 has a height difference, that is, the second sub-mask pattern 24 has a first plane and a second plane, the first plane has a second height H3, the second plane has a third height H4, and the third height H4 is less than the second height H3;

[0122] S1031 - 5 , removing the remaining first covering layer 11 , the first photoresist pattern 21 , the fourth mask layer 9 and the third mask layer 8 .

[0123] In some embodiments, as Figure 14 、 Figure 15 、 Figure 16As shown, step S1032 adopts the second patterning process and specifically includes:

[0124] S1032-1, sequentially forming a fifth mask layer 38, a sixth mask layer 39 and a photoresist 7 on the first sub-mask pattern 23 and the second sub-mask pattern 24;

[0125] S1032-2, performing an exposure and development process on the photoresist 7 to form a second photoresist pattern 27;

[0126] S1032-3, forming a second covering layer 40 on the second photoresist pattern 27, the second covering layer 40 covers the second photoresist pattern 27, the sidewalls of the second photoresist pattern 27 and the sixth mask layer 39 not covered by the second photoresist pattern 27, to form a second opening 28;

[0127] S1032-4, using a dry etching process to remove the second cover layer 40, the sixth mask layer 39, the fifth mask layer 38, and the first sub-mask pattern 23 or the second sub-mask pattern 24 in the area of ​​the second opening 28, forming the first mask pattern 29 in the array area 1, and forming the second mask pattern 30 in the peripheral area 2; wherein the second mask pattern includes a stepped structure having a first plane and a second plane;

[0128] S1032 - 5 , removing the remaining second covering layer 40 , the second photoresist pattern 27 , the sixth mask layer 39 and the fifth mask layer 38 .

[0129] It should be noted that Figure 11 、 Figure 14 Can be opposite edge Figure 2 Schematic diagram of the subsequent preparation process of the cross section AA', Figure 12 、 Figure 15 Can be opposite edge Figure 2 Schematic diagram of the subsequent preparation process of the cross section of BB', Figure 13 、 Figure 16 Can be opposite edge Figure 2 Schematic diagram of the subsequent preparation process of the cross section CC'.

[0130] In some embodiments, the third mask layer, the fifth mask layer, and the seventh mask layer are made of the same material. The fourth mask layer, the sixth mask layer, and the eighth mask layer are made of the same material. The third mask layer, the fifth mask layer, and the seventh mask layer are made of materials different from the fourth mask layer, the sixth mask layer, and the eighth mask layer. The third mask layer, the fifth mask layer, and the seventh mask layer are made of materials different from the first mask layer and the second mask layer.

[0131] In some embodiments, the materials of the third mask layer, the fifth mask layer, and the seventh mask layer include bottom anti-reflection coating (BARC);

[0132] The material of the fourth mask layer, the sixth mask layer, and the eighth mask layer includes silicon oxynitride (SiON).

[0133] It should be noted that the BARC layer can be developed, which facilitates the removal of the third mask layer, the fifth mask layer, and the seventh mask layer.

[0134] In some embodiments, the first covering layer, the second covering layer, the third covering layer, and the fourth covering layer are made of the same material.

[0135] In some embodiments, the materials of the first capping layer, the second capping layer, the third capping layer, and the fourth capping layer include silicon dioxide (SiO 2 ).

[0136] In some embodiments, the substrate provided in the embodiments of the present application is a semiconductor substrate. In specific implementations, the semiconductor substrate includes, but is not limited to, silicon (Si), germanium (Ge), SiGe and other commonly used substrates in the semiconductor field.

[0137] In some embodiments, the material of the first dielectric layer includes silicon oxide.

[0138] It should be noted that, in a specific implementation, the method for fabricating a semiconductor device provided in an embodiment of the present application can be utilized. After forming the first and second mask patterns, the method further includes transferring the first and second mask patterns to a substrate, such that the areas corresponding to the first and second mask patterns are semiconductor active areas, and the areas on the substrate outside the first and second mask patterns are conductive areas, i.e., source and drain contact areas. After transferring the first and second mask patterns to the substrate, the first mask layer is removed. The subsequent method for fabricating a semiconductor device further includes steps such as forming gates, sources and drains, capacitors, word lines, and bit lines.

[0139] An embodiment of the present application provides a semiconductor device, which is manufactured using the method for manufacturing a semiconductor device provided in an embodiment of the present application.

[0140] In a specific implementation, the semiconductor device includes: a substrate, a first dielectric layer, a gate, a source and a drain, a capacitor, a word line, a bit line, etc. The pattern of the conductive active area of ​​the substrate is transferred using the first mask pattern and the second mask pattern obtained by the method for preparing the semiconductor device provided in the embodiment of the application.

[0141] In some embodiments, the semiconductor device provided by the embodiments of the present application is applied to dynamic random access memory (DRAM).

[0142] In summary, the semiconductor device and the preparation method thereof provided in the embodiments of the present application obtain a complete mask pattern through at least two graphical processes including exposure, that is, the mask pattern in the peripheral area is split, and the complex mask pattern is split into several simple patterns for exposure in batches, thereby reducing the optical proximity effect, avoiding the appearance of rounded corners in the mask pattern in the peripheral area, and improving the morphology of the mask pattern in the peripheral area, thereby improving the production yield of the mask pattern in the peripheral area, and further reducing the leakage current of the semiconductor device.

[0143] Obviously, those skilled in the art may make various changes and modifications to this application without departing from the spirit and scope of this application. Thus, if these modifications and variations of this application fall within the scope of the claims of this application and their equivalents, this application is intended to include these modifications and variations.

Claims

1. A method for preparing a semiconductor device, characterized in that: The method comprises: Providing a substrate and forming a first dielectric layer on one side of the substrate; the substrate includes an array area and a peripheral area outside the array area; forming an initial mask pattern on the first dielectric layer; Applying at least two patterning processes to the initial mask pattern to form a first mask pattern in the array region and a second mask pattern in the peripheral region; wherein each patterning process exposes the array region and the peripheral region; The initial mask pattern is subjected to at least two patterning processes to form a first mask pattern in the array area and a second mask pattern in the peripheral area, specifically comprising: Patterning the initial mask pattern using a first patterning process to form a first sub-mask pattern in the array region and a second sub-mask pattern in the peripheral region, wherein the first sub-mask pattern has a first height and the second sub-mask pattern has a second height; The first sub-mask pattern and the second sub-mask pattern are patterned using a second patterning process to form the first mask pattern having the first height in the array area, and at the same time form the second mask pattern in the peripheral area, wherein the second mask pattern includes a stepped structure having a first plane and a second plane, the first plane has the second height, the second plane has a third height, and the third height is less than the second height.

2. The method according to claim 1, characterized in that Forming an initial mask pattern on the first dielectric layer specifically includes: forming a first mask layer on the first dielectric layer; removing the first mask layer in the array area by a patterning process; forming a second mask layer covering the array area and the peripheral area; A patterning process is adopted to form an initial pattern of the array region on the second mask layer in the array region and the first mask layer and the second mask layer in the peripheral region are retained to obtain an initial mask pattern.

3. The method according to claim 2, characterized in that The thickness H1 of the second mask layer and the total thickness H2 of the first mask layer and the second mask layer in the peripheral area satisfy: H1 / H2 is greater than or equal to 1 / 4 and less than or equal to 3 / 4.

4. The method according to claim 3, characterized in that The thickness of the second mask layer is equal to the first height; The total thickness of the first mask layer and the second mask layer is equal to the second height.

5. The method according to claim 2, characterized in that The material of the first mask layer is the same as that of the second mask layer.

6. The method according to claim 5, characterized in that The material of the first mask layer and the material of the second mask layer include polyethylene.

7. The method according to claim 1, characterized in that The sum of the third height H4 and the first height H5 is equal to the second height H3.

8. The method according to claim 7, characterized in that The first height H5 and the second height H3 satisfy: H5 / H3 is greater than or equal to 1 / 4 and less than or equal to 3 / 4.

9. The method according to any one of claims 1 to 8, characterized in that The initial mask pattern of the array area includes a plurality of first patterns spaced apart along a first direction, the first patterns being continuous patterns in a second direction; the first direction and the second direction intersect; The initial mask pattern of the peripheral region includes a second pattern that is continuous in the first direction and the second direction.

10. The method according to claim 9, characterized in that Patterning the initial mask pattern using a first patterning process to form a first sub-mask pattern in the array region and simultaneously forming a second sub-mask pattern in the peripheral region includes: performing patterning on the initial mask pattern of the array area in the second direction to form the first sub-mask patterns arranged at first intervals in the second direction; The initial mask pattern in the peripheral area is patterned in the first direction or the second direction, and a portion of the initial mask pattern is removed in a direction perpendicular to the substrate to form a second sub-mask pattern with a height difference in the peripheral area, and the second sub-mask pattern does not expose the first dielectric layer in the peripheral area; wherein the second sub-mask pattern with a height difference has the first plane and the second plane.

11. The method according to claim 10, characterized in that The initial mask pattern is patterned using a second patterning process to form a first sub-mask pattern in the array area and a second sub-mask pattern in the peripheral area, specifically comprising: performing patterning on the first sub-mask patterns in the array area in the second direction to form the first mask patterns arranged at first intervals in the second direction; The initial mask pattern in the peripheral area is patterned in the first direction or the second direction, and a portion of the second sub-mask pattern is removed in a direction perpendicular to the substrate to form the second mask pattern in the peripheral area, and the second mask pattern exposes a portion of the first dielectric layer in the peripheral area.

12. The method according to claim 1, characterized in that The first patterning process specifically includes: forming a third mask layer, a fourth mask layer and a photoresist in sequence on the initial mask pattern; Applying an exposure and development process to the photoresist to form a first photoresist pattern; forming a first covering layer on the first photoresist pattern, wherein the first covering layer covers the first photoresist pattern, sidewalls of the first photoresist pattern, and the fourth mask layer not covered by the first photoresist pattern, to form a first opening; Using a dry etching process, the first covering layer, the fourth mask layer, the third mask layer, and the initial mask pattern in the first opening area are removed to form a first sub-mask pattern in the array area and a second sub-mask pattern in the peripheral area; removing the remaining first covering layer, the first photoresist pattern, the fourth mask layer, and the third mask layer; The second patterning process specifically includes: sequentially forming a fifth mask layer, a sixth mask layer, and a photoresist on the first sub-mask pattern and the second sub-mask pattern; Applying an exposure and development process to the photoresist to form a second photoresist pattern; forming a second covering layer on the second photoresist pattern, wherein the second covering layer covers the second photoresist pattern, sidewalls of the second photoresist pattern, and the sixth mask layer not covered by the photoresist pattern, to form a second opening; Using a dry etching process, the second covering layer, the sixth mask layer, the fifth mask layer, and the first sub-mask pattern or the second sub-mask pattern in the second opening area are removed, forming a first mask pattern in the array area and a second mask pattern in the peripheral area; The remaining second covering layer, the second photoresist pattern, the sixth mask layer, and the fifth mask layer are removed.

13. The method according to claim 12, characterized in that The materials of the third mask layer and the fifth mask layer include bottom anti-reflective coating; The material of the fourth mask layer and the sixth mask layer includes silicon oxynitride; The first covering layer and the second covering layer are made of silicon dioxide.

14. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to any one of claims 1 to 13.

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