An enhanced gallium oxide-based power transistor and a method of manufacturing the same

Abstract

The application discloses an enhanced gallium oxide-based power transistor and a manufacturing method thereof, and the method comprises the following steps: providing a Fe-doped beta-Ga2O3 substrate; sequentially growing a beta-Ga2O3 UID layer, a beta-Ga2O3 channel layer and a beta-Ga2O3 ohmic contact layer on the surface of the substrate, wherein the doping concentration of the beta-Ga2O3 channel layer is lower than the doping concentration of the beta-Ga2O3 ohmic contact layer; etching the beta-Ga2O3 ohmic contact layer outside the ohmic region, and then forming a source electrode and a drain electrode after depositing metal on the ohmic region on the upper surface of the beta-Ga2O3 ohmic contact layer; spin-coating a boron (B)-doped SOG dielectric layer on the upper surface of the beta-Ga2O3 channel layer, and then manufacturing a gate electrode after depositing metal on the gate region on the upper surface of the SOG dielectric layer. According to the application, the B-doped SOG dielectric layer is spin-coated on the gate region on the upper surface of the beta-Ga2O3 channel layer as a P-type layer, so that the channel electrons under the gate can be effectively depleted, the threshold voltage of the transistor is positively shifted, and then the enhanced device is formed.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and particularly relates to an enhancement-mode gallium oxide-based power transistor and a manufacturing method thereof. BACKGROUND

[0002] Since the beta-Ga2O3 material has an ultra-wide band gap and a high breakdown field strength, the power device made of the beta-Ga2O3 has the characteristics of high withstand voltage and large power, and has the potential for application in the field of power electronics. In recent years, the beta-Ga2O3 crystal material and the power device have become a research hotspot in the field. However, since the beta-Ga2O3 bulk material has a low mobility, a relatively thick channel layer is usually needed to obtain a large current output, and at the same time, the threshold voltage of the device is relatively negative, usually more than -20V, which seriously affects the application of the gallium oxide power transistor in the field of power electronics.

[0003] Therefore, how to design and develop the gallium oxide power transistor with a positive threshold voltage (i.e., an enhancement-mode) has become a problem to be solved by the technical personnel in the field. SUMMARY

[0004] In order to solve the above problems existing in the prior art, the application provides an enhancement-mode gallium oxide-based power transistor and a manufacturing method thereof. The technical problem to be solved by the application is realized by the following technical scheme:

[0005] In a first aspect, the application provides a manufacturing method of an enhancement-mode gallium oxide-based power transistor, comprising:

[0006] providing a beta-Ga2O3 substrate doped with Fe;

[0007] growing a beta-Ga2O3 UID layer, a beta-Ga2O3 channel layer and a beta-Ga2O3 ohmic contact layer on one side surface of the substrate in sequence, the doping concentration of the beta-Ga2O3 channel layer being lower than the doping concentration of the beta-Ga2O3 ohmic contact layer;

[0008] etching the beta-Ga2O3 ohmic contact layer outside the ohmic region, and after depositing metal on the ohmic region on the side of the beta-Ga2O3 ohmic contact layer away from the substrate, forming a source electrode and a drain electrode;

[0009] spinning a boron (B) doped SOG dielectric layer on the side surface of the beta-Ga2O3 channel layer away from the substrate, and after depositing metal on the gate region on the side of the SOG dielectric layer away from the substrate, manufacturing and forming a gate electrode.

[0010] In one embodiment of the present application, after the β-Ga2O3 ohmic contact layer outside the ohmic region is etched and the metal is deposited on the ohmic region on the side of the β-Ga2O3 ohmic contact layer away from the substrate, the step of forming the source electrode and the drain electrode comprises:

[0011] etching the β-Ga2O3 ohmic contact layer outside the ohmic region;

[0012] After the Ti / Au metal stack is evaporated on the surface of the side of the β-Ga2O3 ohmic contact layer away from the substrate, rapid thermal annealing is performed to alloy the Ti / Au metal, thereby forming the source electrode and the drain electrode.

[0013] In one embodiment of the present application, the etching depth of the β-Ga2O3 ohmic contact layer in the direction perpendicular to the plane where the substrate is located is at least equal to the thickness of the β-Ga2O3 ohmic contact layer.

[0014] In one embodiment of the present application, the step of forming the gate electrode after the B-doped SOG dielectric layer is spin-coated on the surface of the side of the β-Ga2O3 channel layer away from the substrate and the metal is deposited on the gate region on the side of the SOG dielectric layer away from the substrate comprises:

[0015] spinning the B-doped SOG dielectric layer on the surface of the side of the β-Ga2O3 channel layer away from the substrate and heating to dry it;

[0016] etching the SOG dielectric layer outside the gate region;

[0017] evaporating the Ni / Au metal stack on the gate region on the surface of the side of the SOG dielectric layer away from the substrate to form the gate electrode.

[0018] In one embodiment of the present application, after the step of evaporating the Ni / Au metal stack on the gate region on the surface of the side of the SOG dielectric layer away from the substrate to form the gate electrode, the method further comprises:

[0019] depositing the interconnection metal on the surface of the side of the gate, the source and the drain away from the substrate, and leading out the source, the gate and the drain to the preset pad.

[0020] In the second aspect, the present application provides an enhanced gallium oxide-based power transistor, which is prepared by using the manufacturing method of the enhanced gallium oxide-based power transistor of the first aspect.

[0021] Compared with the prior art, the present application has the following beneficial effects:

[0022] This invention provides an enhancement-mode gallium oxide-based power transistor and its fabrication method. By spin-coating a B-doped SOG dielectric layer as a P-type layer on the gate region of the upper surface of the β-Ga2O3 channel layer, the channel electrons below the gate can be effectively depleted, causing the threshold voltage of the transistor to shift positively, thereby forming an enhancement-mode device.

[0023] Furthermore, in the aforementioned power transistor, the doping concentration of the β-Ga2O3 ohmic contact layer is higher than that of the β-Ga2O3 channel layer. In other words, the present invention uses a heavily doped layer to form the ohmic contact, which is simpler and more controllable than the ohmic region ion implantation process in the prior art.

[0024] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0025] Figure 1 This is a flowchart of a method for fabricating an enhanced gallium oxide-based power transistor according to an embodiment of the present invention;

[0026] Figure 2 This is a schematic diagram of a method for fabricating an enhanced gallium oxide-based power transistor according to an embodiment of the present invention;

[0027] Figure 3 This is another schematic diagram of the fabrication method of the enhanced gallium oxide-based power transistor provided in the embodiment of the present invention;

[0028] Figure 4 This is another schematic diagram of the fabrication method of the enhanced gallium oxide-based power transistor provided in the embodiment of the present invention;

[0029] Figure 5 This is another schematic diagram of the fabrication method of the enhanced gallium oxide-based power transistor provided in the embodiment of the present invention;

[0030] Figure 6 This is another schematic diagram of the fabrication method of the enhanced gallium oxide-based power transistor provided in the embodiment of the present invention;

[0031] Figure 7 This is another schematic diagram of the fabrication method of the enhanced gallium oxide-based power transistor provided in the embodiments of the present invention. Detailed Implementation

[0032] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0033] Figure 1 This is a flowchart illustrating a method for fabricating an enhanced gallium oxide-based power transistor according to an embodiment of the present invention. Please refer to [link / reference]. Figure 1The embodiment of the present application provides a manufacturing method of an enhanced gallium oxide-based power transistor, comprising the following steps:

[0034] S1, providing a Fe-doped beta-Ga2O3 substrate;

[0035] S2, sequentially growing a beta-Ga2O3 UID layer, a beta-Ga2O3 channel layer and a beta-Ga2O3 ohmic contact layer on one side surface of the substrate, wherein the doping concentration of the beta-Ga2O3 channel layer is lower than the doping concentration of the beta-Ga2O3 ohmic contact layer;

[0036] S3, etching the beta-Ga2O3 ohmic contact layer outside the ohmic region, and then forming a source electrode and a drain electrode after depositing metal on the ohmic region away from the substrate side of the beta-Ga2O3 ohmic contact layer;

[0037] S4, spin-coating a B-doped SOG dielectric layer on the side surface of the beta-Ga2O3 channel layer away from the substrate, and then forming a gate electrode after depositing metal on the gate region away from the substrate side of the SOG dielectric layer.

[0038] Specifically, first, a beta-Ga2O3 UID layer is grown on one side surface of the Fe-doped beta-Ga2O3 substrate (a <010>, <-201> or <001> crystal direction) by using an epitaxial device, then a lightly-doped beta-Ga2O3 channel layer is grown on the side surface of the beta-Ga2O3 UID layer away from the substrate, and a heavily-doped beta-Ga2O3 ohmic contact layer is grown on the side surface of the beta-Ga2O3 channel layer away from the substrate. In step S3, the beta-Ga2O3 ohmic contact layer outside the ohmic region is etched, a Ti / Au metal layer is evaporated on the side surface of the beta-Ga2O3 ohmic contact layer away from the substrate, and rapid thermal annealing treatment is performed on the Ti / Au metal layer to make the Ti metal and the Au metal alloy, so as to form the source electrode and the drain electrode.

[0039] It should be noted that in the direction perpendicular to the plane where the substrate is located, the etching depth of the beta-Ga2O3 ohmic contact layer is at least equal to the thickness of the beta-Ga2O3 ohmic contact layer; that is to say, in the direction perpendicular to the plane where the substrate is located, the beta-Ga2O3 ohmic contact layer can be etched exactly, or a part of the beta-Ga2O3 channel layer can be etched at the same time when the beta-Ga2O3 ohmic contact layer is etched.

[0040] In step S4, after spin-coating a boron (B) doped SOG medium layer on the side surface of the β-Ga2O3 channel layer away from the substrate, heating the wafer to dry the SOG medium layer, removing the SOG medium layer outside the gate region, and evaporating Ni / Au metal on the remaining SOG medium layer, the above-mentioned enhancement-mode gallium oxide-based power transistor is formed. It should be understood that the B-doped SOG medium layer has good P-type semiconductor properties, so it can deplete the carriers in the channel under the gate, so that the threshold voltage of the device is positively shifted, and finally an enhancement-mode device is realized.

[0041] Optionally, after the gate is completed, an interconnection metal is further deposited on the source, drain and gate, and the source, drain and gate are led out to a preset pad.

[0042] Embodiment one: manufacturing a gallium oxide-based power transistor with a 200 nm channel layer

[0043] S1, providing a Fe-doped β-Ga2O3 substrate.

[0044] S2, sequentially growing a β-Ga2O3 UID layer, a β-Ga2O3 channel layer and a β-Ga2O3 ohmic contact layer on one side surface of the substrate, the doping concentration of the β-Ga2O3 channel layer being lower than the doping concentration of the β-Ga2O3 ohmic contact layer:

[0045] S201, growing a β-Ga2O3 UID layer with a thickness of 100 nm and a carrier concentration of 1×10 14 cm -3 ;

[0046] S202, growing a β-Ga2O3 channel layer with a thickness of 200 nm and a doping concentration of 1×10 17 cm -3 ;

[0047] S203, growing a β-Ga2O3 ohmic contact layer with a thickness of 20 nm and a doping concentration of 5×10 18 cm -3 .

[0048] S3, etching the β-Ga2O3 ohmic contact layer outside the ohmic region, and after depositing a metal on the ohmic region of the β-Ga2O3 ohmic contact layer away from the substrate, forming a source electrode and a drain electrode:

[0049] S301, etching the β-Ga2O3 ohmic contact layer outside the ohmic region to a depth of 20 nm;

[0050] S302, evaporate Ti / Au metal stack on the side surface of the β-Ga2O3 ohmic contact layer away from the substrate, the thickness of the Ti / Au metal stack is 20 / 200 nm;

[0051] S303, rapid thermal annealing, alloy the Ti / Au metal stack, and complete the fabrication of the source and drain electrodes.

[0052] S4, spin-coat a B-doped SOG dielectric layer on the side surface of the β-Ga2O3 channel layer away from the substrate, and after depositing a metal on the gate region of the SOG dielectric layer away from the substrate, fabricate and form a gate electrode:

[0053] S401, spin-coat a B-doped SOG dielectric layer on the side surface of the β-Ga2O3 channel layer away from the substrate, the thickness of the SOG dielectric layer is 100 nm, and the doping concentration is 1×10 17 cm -3 ;

[0054] S402, heat the substrate to dry it;

[0055] S403, etch the SOG dielectric layer except for the gate region, the etching depth is 100 nm;

[0056] S404, evaporate a Ni / Au metal stack on the SOG dielectric layer to form a gate electrode, the thickness of the Ni / Au metal stack is 45 / 400 nm;

[0057] S405, deposit an interconnection metal and lead out an electrode.

[0058] Example Two: Fabrication of a Gallium Oxide-based Power Transistor with a 400 nm Channel Layer

[0059] S1, provide a Fe-doped β-Ga2O3 substrate.

[0060] S2, grow a β-Ga2O3 UID layer, a β-Ga2O3 channel layer, and a β-Ga2O3 ohmic contact layer in sequence on the side surface of the substrate, the doping concentration of the β-Ga2O3 channel layer is lower than that of the β-Ga2O3 ohmic contact layer:

[0061] S201, grow a β-Ga2O3 UID layer on the side surface of the Fe-doped β-Ga2O3 substrate, the thickness of the β-Ga2O3 UID layer is 300 nm, and the carrier concentration is 1×10 15 cm -3 ;

[0062] S202, grow a β-Ga2O3 channel layer on the side surface of the β-Ga2O3 UID layer away from the substrate, the thickness of the β-Ga2O3 channel layer is 400 nm, and the doping concentration is 1×10 18 cm -3 ;

[0063] S203, growing a β-Ga2O3 ohmic contact layer on the side surface of the β-Ga2O3 channel layer away from the substrate, with a thickness of 60 nm and a doping concentration of 1×10 19 cm -3 .

[0064] S3, etching the β-Ga2O3 ohmic contact layer outside the ohmic region, and after depositing metal on the ohmic region on the side of the β-Ga2O3 ohmic contact layer away from the substrate, forming a source electrode and a drain electrode:

[0065] S301, etching the β-Ga2O3 ohmic contact layer outside the ohmic region, with an etching depth of 60 nm;

[0066] S302, evaporating a Ti / Au metal stack on the side surface of the β-Ga2O3 ohmic contact layer away from the substrate, with a thickness of 20 / 200 nm;

[0067] S303, rapid thermal annealing, alloying the Ti / Au metal stack, and completing the fabrication of the source and drain electrodes.

[0068] S4, spin-coating a B-doped SOG dielectric layer on the side surface of the β-Ga2O3 channel layer away from the substrate, and after depositing metal on the gate region on the side of the SOG dielectric layer away from the substrate, fabricating and forming a gate electrode:

[0069] S401, spin-coating a B-doped SOG dielectric layer on the side surface of the β-Ga2O3 channel layer away from the substrate, with a thickness of 300 nm and a doping concentration of 1×10 18 cm -3 ;

[0070] S402, heating the substrate to dry it;

[0071] S403, etching the SOG dielectric layer outside the gate region, with an etching depth of 300 nm;

[0072] S404, evaporating a Ni / Au metal stack above the SOG dielectric layer to form a gate electrode, with a thickness of 45 / 400 nm;

[0073] S405, depositing an interconnection metal and leading out an electrode.

[0074] Example Three: Gallium Oxide Power Transistor with a 600 nm Channel Layer

[0075] S1, providing a Fe-doped β-Ga2O3 substrate.

[0076] S2, growing a β-Ga2O3 UID layer, a β-Ga2O3 channel layer and a β-Ga2O3 ohmic contact layer on a side surface of the substrate in sequence, the doping concentration of the β-Ga2O3 channel layer is lower than the doping concentration of the β-Ga2O3 ohmic contact layer:

[0077] S201, growing a β-Ga2O3 UID layer on a side surface of the Fe-doped β-Ga2O3 substrate, the thickness of the β-Ga2O3 UID layer is 500 nm, and the carrier concentration is 1×10 16 cm -3 ;

[0078] S202, growing a β-Ga2O3 channel layer on a side surface of the β-Ga2O3 UID layer away from the substrate, the thickness of the β-Ga2O3 channel layer is 600 nm, and the doping concentration is 5×10 18 cm -3 ;

[0079] S203, growing a β-Ga2O3 ohmic contact layer on a side surface of the β-Ga2O3 channel layer away from the substrate, the thickness of the β-Ga2O3 ohmic contact layer is 100 nm, and the doping concentration is 1×10 19 cm -3 .

[0080] S3, etching the β-Ga2O3 ohmic contact layer outside the ohmic region, and after depositing a metal on the ohmic region of the β-Ga2O3 ohmic contact layer away from the substrate, forming a source electrode and a drain electrode:

[0081] S301, etching the β-Ga2O3 ohmic contact layer outside the ohmic region, and after depositing a metal on the ohmic region of the β-Ga2O3 ohmic contact layer away from the substrate, forming a source electrode and a drain electrode:

[0082] S302, evaporating a Ti / Au metal stack on a side surface of the β-Ga2O3 ohmic contact layer away from the substrate, the thickness of the Ti / Au metal stack is 20 / 200 nm;

[0083] S303, rapid thermal annealing, alloying the Ti / Au metal stack, and completing the fabrication of the source and drain electrodes.

[0084] S4, spin-coating a B-doped SOG dielectric layer on a side surface of the β-Ga2O3 channel layer away from the substrate, and after depositing a metal on the gate region of the SOG dielectric layer away from the substrate, fabricating a gate electrode:

[0085] S401, spin-coating a B-doped SOG dielectric layer on a side surface of the β-Ga2O3 channel layer away from the substrate, the thickness of the SOG dielectric layer is 500 nm, and the doping concentration is 1×10 19 cm -3 ;

[0086] S402, heating the substrate to dry it;

[0087] S403, etching the SOG medium layer outside the gate region, and the etching depth is 100nm;

[0088] S404, evaporating Ni / Au metal layer above the SOG medium layer to form a gate, and the thickness of the Ni / Au metal layer is 45 / 400nm;

[0089] S405, depositing interconnection metal and leading electrode.

[0090] The embodiment of the present application also provides an enhanced gallium oxide-based power transistor, which is prepared by using the manufacturing method of the enhanced gallium oxide-based power transistor.

[0091] It can be known from the above embodiments that the present application has the following beneficial effects:

[0092] The present application provides an enhanced gallium oxide-based power transistor and a manufacturing method thereof, wherein the B-doped SOG medium layer is spin-coated on the gate region on the surface of the beta-Ga2O3 channel layer as a P-type layer, which can effectively deplete the channel electrons below the gate, so that the threshold voltage of the transistor is positively shifted, and then the enhanced device is formed.

[0093] In addition, in the power transistor, the doping concentration of the beta-Ga2O3 ohmic contact layer is higher than the doping concentration of the beta-Ga2O3 channel layer, that is, the present application adopts the heavily doped layer to form the ohmic contact, and compared with the ion implantation process of the ohmic region in the prior art, the process is simpler and more controllable.

[0094] In the description of the present application, it should be understood that the orientations or positional relationships indicated by the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "upper", "lower", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", "clockwise", "counterclockwise" and the like are based on the orientations or positional relationships shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and therefore cannot be understood as indicating or implying that the devices or elements indicated must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application.

[0095] In addition, the terms "first" and "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined with "first" and "second" can explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise specifically limited.

[0096] In the present application, unless specifically defined otherwise and limited, the terms "mount", "connect", "connection", "contact", and the like are to be construed in their broadest possible sense, such as to include fixed connections, detachable connections, or integral connections; mechanical connections, electrical connections, or connections made directly or through an intermediary medium; or the internal communication between two elements or the interaction between two elements. Those skilled in the art can understand the specific meaning of the above terms in the present application according to the specific circumstances.

[0097] In the present application, unless specifically defined otherwise and limited, the first feature "on" or "under" the second feature can include that the first and second features are in direct contact, or that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, the first feature "on", "above", and "over" the second feature includes that the first feature is directly above and obliquely above the second feature, or only means that the first feature is higher in horizontal height than the second feature. The first feature "under", "below", and "under" the second feature includes that the first feature is directly below and obliquely below the second feature, or only means that the first feature is lower in horizontal height than the second feature.

[0098] In the description of the present application, the description of the terms "one embodiment", "some embodiments", "an example", "a specific example", or "some examples" and the like means that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In the present application, the illustrative description of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described can be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art can combine and integrate different embodiments or examples described in the present application.

[0099] Although the present application is described herein in conjunction with various embodiments, those skilled in the art, with the benefit of the drawings, the disclosure, and the appended claims, can understand and appreciate other variations of the disclosed embodiments. Certain measures are described in mutually different dependent claims, but this does not mean that these measures cannot be combined to produce good results.

[0100] The above is a further detailed description of the present application in conjunction with specific preferred embodiments, and cannot be considered as limiting the specific implementation of the present application to these descriptions. For those skilled in the art, without departing from the concept of the present application, a number of simple deductions or substitutions can be made, which should be considered as falling within the scope of protection of the present application.

Claims

1. A method for fabricating an enhanced gallium oxide-based power transistor, comprising: The application relates to a method for manufacturing a Ga2O3-based field effect transistor (FET) and a Ga2O3-based FET manufactured by the method. The method comprises the following steps: providing an Fe-doped beta-Ga2O3 substrate; sequentially growing a beta-Ga2O3 UID layer, a beta-Ga2O3 channel layer and a beta-Ga2O3 ohmic contact layer on one side surface of the substrate, wherein the doping concentration of the beta-Ga2O3 channel layer is lower than that of the beta-Ga2O3 ohmic contact layer; etching the beta-Ga2O3 ohmic contact layer outside the ohmic region, and then forming source and drain electrodes by depositing metal on the ohmic region of the beta-Ga2O3 ohmic contact layer away from the substrate; spinning a B-doped SOG medium layer on the side surface of the beta-Ga2O3 channel layer away from the substrate, and then forming a gate electrode by depositing metal on the gate region of the SOG medium layer away from the substrate; 2. The method of fabricating an enhanced gallium oxide-based power transistor according to claim 1, wherein the B-doped SOG medium layer serves as a P-type layer. The step of etching the beta-Ga2O3 ohmic contact layer outside the ohmic region, and then forming source and drain electrodes by depositing metal on the ohmic region of the beta-Ga2O3 ohmic contact layer away from the substrate comprises the following steps: etching the beta-Ga2O3 ohmic contact layer outside the ohmic region; 3. The method of fabricating an enhanced gallium oxide-based power transistor according to claim 2, wherein after evaporating a Ti / Au metal stack on the side surface of the beta-Ga2O3 ohmic contact layer away from the substrate, performing rapid thermal annealing to alloy the Ti / Au metal, thereby forming the source and drain electrodes.

4. The method of fabricating an enhanced gallium oxide-based power transistor according to claim 1, wherein In the direction perpendicular to the plane where the substrate is located, the etching depth of the beta-Ga2O3 ohmic contact layer is at least equal to the thickness of the beta-Ga2O3 ohmic contact layer. The step of spinning a B-doped SOG medium layer on the side surface of the beta-Ga2O3 channel layer away from the substrate, and then forming a gate electrode by depositing metal on the gate region of the SOG medium layer away from the substrate comprises the following steps: spinning a B-doped SOG medium layer on the side surface of the beta-Ga2O3 channel layer away from the substrate, and then heating to dry the B-doped SOG medium layer; etching the SOG medium layer outside the gate region; 5. The method of fabricating an enhanced gallium oxide-based power transistor according to claim 4, wherein evaporating a Ni / Au metal stack on the gate region of the SOG medium layer away from the substrate to form the gate electrode. After the step of evaporating a Ni / Au metal stack on the gate region of the SOG medium layer away from the substrate to form the gate electrode, the method further comprises the following steps: depositing an interconnection metal on the side surface of the gate, the source and drain electrodes away from the substrate, and leading out the source electrode, the gate and the drain electrode to a preset pad.

6. An enhanced gallium oxide-based power transistor, characterized by, A method of fabricating an enhanced gallium oxide-based power transistor as claimed in claim 1 5. The method of claim 1.

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