A method for manufacturing a semiconductor device and a semiconductor device

Abstract

The present disclosure provides a semiconductor device manufacturing method and a semiconductor device. The semiconductor device manufacturing method comprises: providing a substrate with a trench, the trench extending along the thickness direction of the substrate from the first surface of the substrate; sequentially forming a first auxiliary layer and a first conductive layer in the trench, the first conductive layer covering the first auxiliary layer; thinning the substrate at the second surface of the substrate to expose the first auxiliary layer; removing the first auxiliary layer to form a first opening; forming a second dielectric layer on the second surface of the substrate; patterning the second dielectric layer to form a second opening in the second dielectric layer, the second opening exposing the first opening; and depositing a second initial conductive layer, the second initial conductive layer filling the first opening and the second opening. The method in the present disclosure can effectively avoid the material of the first auxiliary layer contaminating the surface or gap of the substrate during the thinning process of the substrate, thereby improving the yield.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit manufacturing technology, and in particular to a method for manufacturing a semiconductor device and a semiconductor device. Background Technology

[0002] Through Silicon Vias (TSV) technology enables interconnections between chips with the shortest distance and smallest spacing, resulting in better electrical performance.

[0003] However, in related technologies, the fabrication of TSVs typically requires grinding until the copper layer is exposed. This process necessitates grinding both silicon and copper simultaneously. Silicon is brittle and prone to cracking. Furthermore, under high temperature and an applied electric field, copper easily diffuses within the semiconductor silicon wafer, potentially causing copper contamination of the silicon surface or cracks, resulting in low yield. Summary of the Invention

[0004] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0005] This disclosure provides a method for fabricating a semiconductor device and a semiconductor device.

[0006] According to a first aspect of this disclosure, a method for fabricating a semiconductor device is proposed, comprising: providing a substrate having a trench, the trench extending from a first surface of the substrate along the thickness direction of the substrate; sequentially forming a first auxiliary layer and a first conductive layer within the trench, the first conductive layer covering the first auxiliary layer; thinning the substrate on a second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are disposed opposite to each other; removing the first auxiliary layer to form a first opening; forming a second dielectric layer on the second surface of the substrate; patterning the second dielectric layer to form a second opening in the second dielectric layer, the second opening exposing the first opening; and depositing a second initial conductive layer to fill the first opening and the second opening.

[0007] In some embodiments, after depositing the second initial conductive layer, the method further includes: removing the second dielectric layer and the second initial conductive layer located in the second opening, and retaining the second initial conductive layer located in the first opening as the second conductive layer.

[0008] In other embodiments, after depositing the second initial conductive layer, the method further includes: removing the second dielectric layer and retaining the second initial conductive layer located in the second opening, wherein the second initial conductive layer serves as the second conductive layer.

[0009] The coefficient of thermal expansion of the second conductive layer is smaller than that of the first conductive layer.

[0010] The material of the first conductive layer may be the same as or different from the material of the second conductive layer.

[0011] In some embodiments, the width of the projected profile of the second opening on the substrate is greater than the width of the projected profile of the first opening on the substrate. Before depositing the second initial conductive layer, the method further includes: forming a second dielectric layer, the second dielectric layer at least covering the inner wall of the second opening; and forming a second barrier layer, the second barrier layer covering the second dielectric layer.

[0012] In some embodiments, after forming the second conductive layer, the method further includes annealing the second conductive layer.

[0013] In some embodiments, before sequentially forming a first auxiliary layer and a first conductive layer in the trench, the method further includes: forming a first dielectric layer that covers the inner wall of the trench; and forming a first barrier layer that covers the first dielectric layer.

[0014] In some embodiments, prior to providing the substrate with trenches, the method further includes: providing a substrate; forming a first dielectric layer on the surface of the substrate to form the substrate; patterning the first dielectric layer to form the trenches in the substrate, the trenches penetrating the first dielectric layer, and the exposed surface of the first dielectric layer being the first surface.

[0015] Under the same etching conditions, the etching rate of the first auxiliary layer is higher than that of the substrate.

[0016] The material of the first auxiliary layer has less ductility than the material of the first conductive layer.

[0017] The second aspect of this disclosure provides a semiconductor device, comprising: a substrate having a first surface and a second surface disposed opposite to each other; at least one through-hole penetrating the substrate along its thickness direction; a first conductive layer and a second conductive layer filling the through-hole and completely filling the through-hole, wherein the first conductive layer and the second conductive layer in the same through-hole are connected; and the top surface of the first conductive layer is flush with the first surface of the substrate.

[0018] The semiconductor device further includes: a dielectric layer covering the inner wall of the via; a barrier layer covering the inner wall of the dielectric layer; and the first conductive layer and the second conductive layer located inside the barrier layer along the radial direction of the via.

[0019] The top surface of the second conductive layer is flush with the second surface of the substrate.

[0020] The second conductive layer includes a first part and a second part, wherein the top surface of the first part is flush with the second surface of the substrate; the second part is located on the second surface, and the surface of the second part connected to the first part covers part of the second surface.

[0021] The first part and the second part are connected as one unit.

[0022] The embodiments disclosed herein employ the above technical solutions and have the following advantages: The method in this disclosure can effectively avoid material contamination of the substrate surface or gaps by the material of the first auxiliary layer during the substrate thinning process, thereby improving the yield. Simultaneously, using the semiconductor device fabrication method in this disclosure to process semiconductor devices can reduce processing steps and improve processing efficiency.

[0023] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0024] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 This is a flowchart illustrating a method for fabricating a semiconductor device according to an exemplary embodiment;

[0026] Figure 2 This is a flowchart illustrating a method for fabricating a semiconductor device according to an exemplary embodiment;

[0027] Figure 3 This is a flowchart illustrating a method for fabricating a semiconductor device according to an exemplary embodiment;

[0028] Figure 4 This is a flowchart illustrating a method for fabricating a semiconductor device according to an exemplary embodiment;

[0029] Figure 5 This is a flowchart illustrating a method for fabricating a semiconductor device according to an exemplary embodiment;

[0030] Figure 6 This is a flowchart illustrating a method for fabricating a semiconductor device according to an exemplary embodiment;

[0031] Figures 7 to 25A schematic diagram of the structures involved in each step of the semiconductor device fabrication process;

[0032] Figure 26 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment;

[0033] Figure 27 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment;

[0034] Figure 28 This is a schematic diagram of the structure of a semiconductor device according to an exemplary embodiment. Detailed Implementation

[0035] In the following description, only certain exemplary embodiments are briefly described. As those skilled in the art will recognize, the described embodiments can be modified in various ways without departing from the spirit or scope of this disclosure. Therefore, the drawings and description are considered to be exemplary in nature and not restrictive.

[0036] Currently, through-silicon via (TSV) technology can achieve the shortest distance and smallest spacing between chips to achieve better electrical performance.

[0037] However, in related technologies, the fabrication of TSVs typically requires grinding until the copper layer is exposed. This process necessitates grinding both silicon and copper simultaneously. Silicon is brittle and prone to cracking. Furthermore, under high temperature and an applied electric field, copper easily diffuses within the semiconductor silicon wafer, potentially causing copper contamination of the silicon surface or cracks, resulting in low yield.

[0038] In view of this, the present disclosure provides a method for manufacturing a semiconductor device that can reduce processing steps and improve the yield of semiconductor devices.

[0039] refer to Figure 1 As shown, the method for fabricating a semiconductor device provided in this embodiment includes:

[0040] S101: Provide a substrate with grooves, the grooves extending from a first surface of the substrate along the thickness direction of the substrate;

[0041] S102: A first auxiliary layer and a first conductive layer are formed sequentially in the trench, with the first conductive layer covering the first auxiliary layer;

[0042] S103: Thin the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are disposed opposite to each other;

[0043] S104: Remove the first auxiliary layer to form the first opening;

[0044] S105: A second dielectric layer is formed on the second surface of the substrate;

[0045] S106: Graphicalize the second dielectric layer, form a second opening in the second dielectric layer, and expose the first opening;

[0046] S107: Deposit a second initial conductive layer, the second initial conductive layer filling the first opening and the second opening.

[0047] In step 101, as Figure 9 As shown, the groove 13 on the substrate 10 is a non-through groove formed on the first surface 14 of the substrate 10, that is, the bottom surface of the groove 13 is a certain distance away from the second surface 15 of the substrate 10. The groove 13 extends from the first surface 14 of the substrate 10 along the thickness direction of the substrate 10, so that the bottom surface of the groove 13 is close to the second surface 15 of the substrate 10, and the first surface 14 and the second surface 15 are arranged opposite to each other.

[0048] The number of grooves 13 on the base 10 is not specifically limited; it can be one, two, or more. Taking a plane parallel to the base 10 as a cross-section, the cross-sectional shape of the groove 13 includes, but is not limited to, a circle, a rectangle, or a rhombus.

[0049] Various active devices (e.g., transistors, diodes, etc.) can be disposed on the first surface 14 of the substrate 10, and various electrical interconnection structures can be formed between the active devices.

[0050] In step 102, as Figure 12 and Figure 13 As shown, a first auxiliary layer 20 is first deposited within the trench 13, covering the bottom surface of the trench 13, and the first auxiliary layer 20 has a certain thickness. Then, a first conductive layer 30 is deposited on top of the first auxiliary layer 20, covering the first auxiliary layer 20. That is, the first auxiliary layer 20 is located at the bottom of the trench 13, and is positioned relative to the first conductive layer 30 on the side closer to the second surface 15. The first conductive layer 30 can be made of a material with good electrical conductivity, such as silver, copper, or aluminum.

[0051] In this embodiment, the first auxiliary layer 20 and the first conductive layer 30 can be directly contacted and connected to the sidewall of the trench 13, that is, no other structures are provided between the first auxiliary layer 20 and the sidewall of the trench 13, or between the first conductive layer 30 and the sidewall of the trench 13. Of course, it is understood that in other embodiments, other structures, such as a barrier layer, may be provided between the first auxiliary layer 20 and the sidewall of the trench 13, or between the first conductive layer 30 and the sidewall of the trench 13.

[0052] In this embodiment, when the substrate 10 has two or more trenches 13, the depths of the different trenches 13 may vary. However, the distance between the contact surface of the first conductive layer 30 and the first auxiliary layer 20 in any one trench 13 and the first surface 14 of the substrate 10 is less than the depth of any other trench 13, so as to avoid grinding the first conductive layer 30 when performing step S103, that is, when thinning the substrate 10 on the second surface 15 of the substrate 10.

[0053] In step 103, as Figure 14 As shown, the second surface 15 of the substrate 10 can be ground to thin the substrate 10 until the first auxiliary layer 20 is exposed. The top surface of the first auxiliary layer 20 is flush with the second surface 15, and the surface of the first conductive layer 30 is flush with the first surface 14. The trench 13 forms openings on both the first surface 14 and the second surface 15, creating through-holes that penetrate the first and second surfaces of the substrate 10. During the grinding process to thin the substrate 10, the substrate 10 material near the second surface 15 and part of the first auxiliary layer 20 are simultaneously ground away, avoiding grinding the first conductive layer 30. When the material of the first auxiliary layer 20 is a non-metallic material (such as silicon dioxide or silicon nitride), on the one hand, there is no situation where metallic materials contaminate the second surface of the substrate 10; on the other hand, the ductility of non-metallic materials is weaker than that of metallic materials, and the ductility of the first auxiliary layer 20 is closer to that of the substrate 10 material. When the substrate 10 material and part of the first auxiliary layer 20 are ground away simultaneously, the deformation of the first auxiliary layer 20 in the radial direction is very small, resulting in less compression of the substrate 10 by the first auxiliary layer 20 in the radial direction, reducing the probability of cracks forming on the second surface 15 of the substrate 10, thereby improving the yield of TSV fabrication. To minimize the contamination of the second surface 15 by metallic substances and the cracks on the second surface 15, the material of the first auxiliary layer 20 includes, but is not limited to, non-metallic materials such as silicon dioxide or silicon nitride.

[0054] In addition, the material of the first auxiliary layer 20 in this embodiment can be a non-metallic material or a metallic material with low ductility, which can reduce the probability of metal contamination of the second surface 15 or cracks on the second surface 15.

[0055] In step 104, refer to Figure 12 , Figure 14 and Figure 15 The first auxiliary layer 20 can be removed by etching, so that a first opening 131 is formed at one end of the trench 13 facing the second surface 15, exposing the first conductive layer 30 in the trench 13.

[0056] The etching process can include wet etching, dry etching, deep reactive ion etching, laser etching, etc.

[0057] In steps 105, 106, and S107, as follows Figure 16 , Figure 18 and Figure 19 As shown, and refer to Figure 15 Please see. Figure 16 A second dielectric layer 16 is formed on the second surface 15 of the substrate 10, wherein the material of the second dielectric layer 16 may be silicon dioxide, and the second dielectric layer 16 covers the second surface 15 of the substrate 10 and the first opening 131. See also Figure 18 The second dielectric layer 16 is patterned such that a second opening 161 is formed on the second dielectric layer 16, which exposes the first opening 131. (Refer to...) Figure 19 Finally, a second initial conductive layer 40 is deposited, filling the first opening 131 and the second opening 161. The first conductive layer 30 and the second initial conductive layer 40 are connected as a whole to form a through-silicon via (TSV) for conduction on the substrate 10. This enables multiple semiconductor devices (e.g., chips) to be stacked in a vertical plane, saving space. The material of the second initial conductive layer 40 includes, but is not limited to, silver, copper, and aluminum. The materials of the second initial conductive layer 40 and the first conductive layer 30 can be the same or different.

[0058] like Figure 17 As shown, when patterning the second dielectric layer 16, a mask layer 17 is first formed on the second dielectric layer 16. Geometric patterns are then etched onto the mask layer 17 using exposure and development. Finally, the pattern on the mask layer 17 is transferred to the second dielectric layer 16 through an etching process, thereby forming the second opening 161. The material of the second initial conductive layer 40 is preferably a material with good conductivity, such as silver, copper, or aluminum. The purpose of forming the second dielectric layer 16 on the second surface 15 is to ensure that, during the deposition of the second initial conductive layer 40, it is formed on the surface of the second dielectric layer 16 and within the first opening 131 and the second opening 161, thus preventing metal material from contaminating the second surface 15 of the substrate 10 and any cracks on the second surface 15.

[0059] refer to Figure 2 As shown, in one exemplary embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes:

[0060] S201: Provide a substrate with grooves, the grooves extending from a first surface of the substrate along the thickness direction of the substrate;

[0061] S202: A first auxiliary layer and a first conductive layer are sequentially formed in the trench, with the first conductive layer covering the first auxiliary layer;

[0062] S203: Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are disposed opposite to each other;

[0063] S204: Remove the first auxiliary layer to form the first opening;

[0064] S205: A second dielectric layer is formed on the second surface of the substrate;

[0065] S206: Graphicalize the second dielectric layer, form a second opening in the second dielectric layer, and expose the first opening;

[0066] S207: Deposit a second initial conductive layer, the second initial conductive layer filling the first opening and the second opening;

[0067] S208: Remove the second dielectric layer and the second initial conductive layer located in the second opening, and retain the second initial conductive layer located in the first opening as the second conductive layer.

[0068] In this embodiment, steps S201 to S207 are implemented in the same way as in the above embodiment, and will not be described again here. In step S208 of this embodiment, as follows: Figure 20 As shown, refer to Figure 18 and Figure 19 As shown, the second dielectric layer 16 and the second initial conductive layer 40 located in the second opening 161 are removed, and the second initial conductive layer 40 located in the first opening 131 is retained as the second conductive layer 41, making the surface of the second conductive layer 41 flush with the second surface 15. At this time, the first conductive layer 30 and the second conductive layer 41 form a connected whole, and both the first conductive layer 30 and the second conductive layer 41 are made of materials with good conductivity, such as silver, copper, aluminum, etc., so that the first conductive layer 30 and the second conductive layer 41 form a conductive silicon via structure of the semiconductor device, and the first conductive layer 30 and the second conductive layer 41 serve as the electrical connection structure between each two adjacent semiconductor devices when multiple semiconductor devices are stacked in the vertical plane direction.

[0069] In this embodiment, the top surface of the second conductive layer 41 is flush with the second surface 15. Devices connected to the second conductive layer 41 can be directly disposed on the substrate 10 and contacted and connected to the second conductive layer 41.

[0070] refer to Figure 3 As shown, in one exemplary embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes:

[0071] S301: Provide a substrate with grooves, the grooves extending from a first surface of the substrate along the thickness direction of the substrate;

[0072] S302: A first auxiliary layer and a first conductive layer are sequentially formed in the trench, with the first conductive layer covering the first auxiliary layer;

[0073] S303: Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are disposed opposite to each other;

[0074] S304: Remove the first auxiliary layer to form the first opening;

[0075] S305: A second dielectric layer is formed on the second surface of the substrate;

[0076] S306: Graphicalize the second dielectric layer, form a second opening in the second dielectric layer, and expose the first opening;

[0077] S307: Deposit a second initial conductive layer, the second initial conductive layer filling the first opening and the second opening;

[0078] S308: Remove the second dielectric layer and retain the second initial conductive layer located in the second opening, which serves as the second conductive layer.

[0079] In this embodiment, steps S301 to S307 are implemented in the same way as in the above embodiments, and will not be repeated here. In step S308, as... Figure 25 As shown, refer to Figure 24 The second dielectric layer 16 is removed, leaving the second initial conductive layer 40 located in the second opening 161. The second initial conductive layer 40 serves as the second conductive layer 41, and the protrusion of the second conductive layer 41 onto the second surface 15 forms a raised structure. The first conductive layer 30 and the second conductive layer 41 form a connected whole, and both the first conductive layer 30 and the second conductive layer 41 are made of materials with good conductivity, such as silver, copper, and aluminum. Thus, the first conductive layer 30 and the second conductive layer 41 form a conductive silicon via structure for the semiconductor device. The first conductive layer 30 and the second conductive layer 41 enable electrical connection between each two adjacent semiconductor devices when multiple semiconductor devices are stacked in the vertical plane direction. The raised structure formed on the second surface 15 by the second conductive layer 41 facilitates the formation of electrical connection between two adjacent semiconductor devices.

[0080] In this embodiment, the materials of the first conductive layer 30 and the second conductive layer 41 can be the same or different. In other possible embodiments, the coefficient of thermal expansion of the second conductive layer 41 is less than that of the first conductive layer 30, so as to reduce the stress borne by the substrate 10 during heat treatment.

[0081] In this embodiment, the second conductive layer 41 is a protruding structure protruding from the second surface 15. The projection of the second conductive layer 41 on the substrate 10 covers the first conductive layer 30, and the projection outline of the second conductive layer 41 on the substrate 10 is larger than the projection outline of the first conductive layer 30.

[0082] In one exemplary embodiment, reference is made to Figure 4 As shown, a method for fabricating a semiconductor device is provided. The method for fabricating a semiconductor device in this embodiment includes:

[0083] S401: Provide a substrate with grooves, the grooves extending from a first surface of the substrate along the thickness direction of the substrate;

[0084] S402: A first auxiliary layer and a first conductive layer are sequentially formed in the trench, with the first conductive layer covering the first auxiliary layer;

[0085] S403: Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are disposed opposite to each other;

[0086] S404: Remove the first auxiliary layer to form the first opening;

[0087] S405: A second dielectric layer is formed on the second surface of the substrate;

[0088] S406: Graphicalize the second dielectric layer, form a second opening in the second dielectric layer, and expose the first opening;

[0089] S407: Form a second dielectric layer, the second dielectric layer at least covering the inner wall of the second opening and the second surface located within the second opening;

[0090] S408: Form a second barrier layer, which covers the second dielectric layer;

[0091] S409: Deposit a second initial conductive layer, the second initial conductive layer filling the first opening and the second opening;

[0092] S410: Remove the second dielectric layer and retain the second initial conductive layer located in the second opening, which serves as the second conductive layer.

[0093] In this embodiment, steps S401 to S406, as well as S409 and S410, are implemented in the same way as in the above embodiments, and will not be repeated here. In steps S407 and S408, as... Figure 22 and Figure 23 As shown, for reference Figure 25A second dielectric layer 52 and a second barrier layer 62 are deposited within the second opening 161 using a deposition process. The second dielectric layer 52 at least covers the inner wall of the second opening 161 and a portion of the second surface 15 located within the second opening 161. Then, a second barrier layer 62 is deposited to form the second dielectric layer 52, thereby isolating the second conductive layer 41 from the substrate 10 and preventing the charge in the second conductive layer 41 from affecting the substrate 10 during the operation of the semiconductor device.

[0094] In this embodiment, after the second conductive layer 41 is formed, if the material of the second conductive layer 41 is copper, the second conductive layer 41 is annealed to eliminate the stress in the second conductive layer 41.

[0095] In one exemplary embodiment, reference is made to Figure 5 As shown, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device in this embodiment includes:

[0096] S501: Provide a substrate with grooves, the grooves extending from a first surface of the substrate along the thickness direction of the substrate;

[0097] S502: Forming a first dielectric layer, the first dielectric layer covers the inner wall of the trench;

[0098] S503: A first barrier layer is formed, and the first barrier layer covers the first dielectric layer;

[0099] S504: A first auxiliary layer and a first conductive layer are sequentially formed in the trench, with the first conductive layer covering the first auxiliary layer;

[0100] S505: Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are disposed opposite to each other;

[0101] S506: Remove the first auxiliary layer to form the first opening;

[0102] S507: A second dielectric layer is formed on the second surface of the substrate;

[0103] S508: Graphicalize the second dielectric layer, form a second opening in the second dielectric layer, and expose the first opening;

[0104] S509: Deposit a second initial conductive layer, the second initial conductive layer filling the first opening and the second opening.

[0105] In this embodiment, steps S501 and S504 to S509 are implemented in the same way as in the above embodiments, and will not be described again here. In steps S502 and S503, as follows: Figure 10 and Figure 11As shown, a first dielectric layer 51 and a first barrier layer 61 are formed on the sidewall of trench 13 by a deposition process. The first dielectric layer 51 covers the inner wall of trench 13, and the first barrier layer 61 covers the first dielectric layer 51, so that the first conductive layer 30, the first auxiliary layer 20 and the inner wall of trench 13 are isolated by the first dielectric layer 51 and the first barrier layer 61. The material of the first dielectric layer 51 is silicon nitride, and the material of the first barrier layer 61 is titanium nitride.

[0106] Additionally, it should be noted that, referring to Figure 12 , Figure 13 As shown, in this embodiment, the first conductive layer 30 and the first auxiliary layer 20 are not directly connected to the inner sidewall of the trench 13. A first dielectric layer 51 and a first barrier layer 61 are provided between the two and the sidewall of the trench 13. The sidewalls of the first conductive layer 30 and the first auxiliary layer 20 are in contact with the first barrier layer 61.

[0107] In this embodiment, by setting a first dielectric layer 51 and a first barrier layer 61, on the one hand, the first dielectric layer 51 serves as an insulator to prevent interference between the first conductive layer 30, the second conductive layer 41 and the active devices on the substrate 10; on the other hand, the first barrier layer 61 can provide a buffer barrier for the substrate 10 during polishing, reducing the probability of cracks in the silicon layer and preventing copper contamination to the surface or cracks of the adjacent silicon layer, thereby further improving the yield of TSV fabrication.

[0108] refer to Figure 6 As shown, in one exemplary embodiment, a method for fabricating a semiconductor device is provided. The method for fabricating the semiconductor device includes:

[0109] S601: Provides a substrate;

[0110] S602: A first dielectric layer is formed on the surface of the substrate to form a substrate;

[0111] S603: A first dielectric layer is patterned, and a trench is formed in the substrate. The trench penetrates the first dielectric layer, and the exposed surface of the first dielectric layer is the first surface.

[0112] S604: Provides a substrate with grooves, the grooves extending from a first surface of the substrate along the thickness direction of the substrate;

[0113] S605: A first auxiliary layer and a first conductive layer are sequentially formed in the trench, with the first conductive layer covering the first auxiliary layer;

[0114] S606: Thinning the substrate on the second surface of the substrate to expose the first auxiliary layer, wherein the first surface and the second surface are disposed opposite to each other;

[0115] S607: Remove the first auxiliary layer to form the first opening;

[0116] S608: A second dielectric layer is formed on the second surface of the substrate;

[0117] S609: A second dielectric layer is graphically defined, and a second opening is formed in the second dielectric layer, the second opening exposing the first opening;

[0118] S610: Deposit a second initial conductive layer, the second initial conductive layer filling the first opening and the second opening.

[0119] Steps S604 to S5610 are implemented in the same way as in the above embodiments, and will not be repeated here. Figure 7 and Figure 8 As shown, and refer to Figure 9 In steps S601, S602, and S603, a substrate 11 is first provided. The substrate 11 can be made of silicon. A first dielectric layer 12 is formed on the surface of the substrate 11. The substrate 11 and the first dielectric layer 12 together constitute the substrate 10. The first dielectric layer 12 is patterned, and trenches 13 are formed in the substrate 10 through an etching process. The surface of the first dielectric layer 12 away from the substrate 11 is the first surface 14, and the surface of the substrate 11 away from the first dielectric layer 12 is the second surface 15.

[0120] like Figure 8 As shown, when patterning the first dielectric layer 12, a mask layer 17 is first formed on the first dielectric layer 12. Geometric patterns are formed on the mask layer 17 using exposure and development. Then, the pattern on the mask layer 17 is transferred to the substrate 10 through an etching process, thereby forming the trench 13. It should be noted that the materials of the first dielectric layer 12 and the second dielectric layer 16 are different.

[0121] In this embodiment, under the same etching conditions, the material of the first auxiliary layer 20 is silicon dioxide, silicon nitride, or a metal with low ductility, and the material of the substrate 10 is silicon. Therefore, the etching rate of the first auxiliary layer 20 is higher than that of the substrate 10, so that when the first auxiliary layer 20 is removed by etching process in step S104, the etching rate of the first auxiliary layer 20 is faster than that of the substrate 10, so as to ensure that the amount of etching on the substrate 10 is minimized when the first auxiliary layer 20 is removed.

[0122] The first auxiliary layer 20 has a high selectivity to the substrate 10, that is, the etching rate of the first auxiliary layer 20 is higher than the etching rate of the substrate 10. For example, the ratio of the etching rate of the first auxiliary layer 20 to the etching rate of the substrate 10 is 100 or 80, etc.

[0123] High selectivity: Selectivity refers to how much faster one material is etched compared to another under the same etching conditions. It is defined as the ratio of the etching rate of the material being etched to the etching rate of the other material. High selectivity means that only the layer of material to be etched is removed. A high-selectivity etching process does not etch the underlying layer (it stops etching at the appropriate depth) and the protective photoresist is also not etched.

[0124] In addition, in this embodiment, the ductility of the material of the first auxiliary layer 20 is less than that of the material of the first conductive layer 30. For example, the material of the first auxiliary layer 20 is silicon dioxide, silicon nitride, or a metal material with low ductility. In this case, when performing step S103, the substrate 10 material near the second surface 15 and part of the first auxiliary layer 20 are ground off simultaneously. Since the material of the first auxiliary layer 20 is silicon dioxide or silicon nitride, which have ductility close to that of silicon, the probability of cracks appearing on the second surface 15 of the substrate 10 is reduced, and there is no situation where metal contaminates the second surface 15 of the substrate 10 or the cracks. If the first auxiliary layer 20 is made of a metal with ductility less than that of the first conductive layer 30, the probability of the metal contained in the first auxiliary layer 20 entering the silicon layer surface or cracks and causing contamination is also reduced to a certain extent.

[0125] The semiconductor device fabrication method disclosed herein involves sequentially depositing a first auxiliary layer and a first conductive layer in a trench. During the process of thinning the substrate through a grinding process to form a through-hole penetrating both sides of the substrate, the second surface of the substrate and the first auxiliary layer in the trench are ground simultaneously without grinding the first conductive layer. Therefore, the metal (e.g., copper) in the first conductive layer will not contaminate the second surface or cracks of the substrate. At the same time, the material of the first auxiliary layer is silicon dioxide or silicon nitride, which has a ductility close to that of silicon. This reduces the probability of cracks appearing on the second surface of the substrate and eliminates the possibility of metal contamination of the second surface or cracks. This can further improve the yield of TSV fabrication.

[0126] The second aspect of this disclosure provides a semiconductor device, according to an exemplary embodiment, such as... Figure 26 and Figure 27 , refer to Figure 28The semiconductor device includes a substrate 10, which has a first surface 14 and a second surface 15, which are disposed opposite to each other. At least one via 18 is formed on the substrate 10, penetrating the substrate 10 along its thickness direction. The semiconductor device also includes a first conductive layer 30 and a second conductive layer 41, both filling and completely filling the via 18. The first conductive layer 30 and the second conductive layer 41 in the same via 18 are connected, wherein the top surface of the first conductive layer 30 is flush with the first surface 14 of the substrate 10, and the top surface of the second conductive layer 41 is flush with the second surface 15 of the substrate 10. In this embodiment, the first conductive layer 30 and the second conductive layer 41 form a TSV structure of the semiconductor device, achieving the shortest distance and smallest spacing between chips for better electrical performance.

[0127] In one exemplary embodiment, reference is made to Figure 26 , Figure 28 As shown, the semiconductor device also includes a dielectric layer 50 covering the inner wall of the via 18, the via 18, and a barrier layer 60 covering the inner wall of the dielectric layer 50. When the cross-section of the via 18 is circular, the first conductive layer 30 and the second conductive layer 41 are located inside the barrier layer 60 along the radial direction of the via 18. The dielectric layer 50 and the barrier layer 60 isolate the first conductive layer 30 and the second conductive layer 41 from the substrate 10, preventing the charges in the first conductive layer 30 and the second conductive layer 41 from interfering with the active devices on the substrate 10.

[0128] In this embodiment, as Figure 25 As shown, the second conductive layer 41 includes a first portion 411 and a second portion 412. The top surface of the first portion 411 is flush with the second surface 15 of the substrate 10. The second portion 412 is located on the second surface 15, and the surface of the second portion 412 connected to the first portion 411 covers a portion of the second surface 15, so that the second portion 412 of the second conductive layer 41 protrudes from the second surface 15 of the substrate 10 to form a protruding structure for electrical connection between different semiconductor devices. The first portion 411 and the second portion 412 are integrally connected.

[0129] The terms "first" and "second" used in this document are for descriptive purposes only and should not be construed as indicating relative importance or implying the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more.

[0130] Obviously, those skilled in the art can make various modifications and variations to this application without departing from the spirit and scope of this application. Therefore, if such modifications and variations fall within the scope of the claims of this application and their equivalents, this application also intends to include such modifications and variations.

Claims

1. A method for fabricating a semiconductor device, characterized in that, include: A substrate with grooves is provided, the grooves extending from a first surface of the substrate along the thickness direction of the substrate; A first dielectric layer is formed within the trench, the first dielectric layer covering only the sidewalls of the trench; A first barrier layer is formed, which only covers the sidewalls of the first dielectric layer, and the first barrier layer is titanium nitride. A first auxiliary layer and a first conductive layer are sequentially formed in the trench. The first conductive layer covers the first auxiliary layer. The first auxiliary layer and the first conductive layer cover the sidewall of the first barrier layer. The first auxiliary layer covers the bottom of the trench. The substrate is thinned by grinding on its second surface until the first auxiliary layer is exposed, wherein the first surface and the second surface are disposed opposite to each other; Remove the first auxiliary layer to form the first opening; A second dielectric layer is formed on the second surface of the substrate; The second dielectric layer is graphically represented, and a second opening is formed in the second dielectric layer, the second opening exposing the first opening; A second initial conductive layer is deposited, which fills the first opening and the second opening.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, After depositing the second initial conductive layer, the process further includes: Remove the second dielectric layer and the second initial conductive layer located in the second opening, and retain the second initial conductive layer located in the first opening as the second conductive layer.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, After depositing the second initial conductive layer, the process further includes: Remove the second dielectric layer and retain the second initial conductive layer located in the second opening, which serves as the second conductive layer.

4. The method for fabricating a semiconductor device according to claim 3, characterized in that, The coefficient of thermal expansion of the second conductive layer is less than that of the first conductive layer.

5. The method for fabricating a semiconductor device according to claim 3, characterized in that, The material of the first conductive layer may be the same as or different from the material of the second conductive layer.

6. The method for fabricating a semiconductor device according to claim 3, characterized in that, The width of the projected profile of the second opening on the substrate is greater than the width of the projected profile of the first opening on the substrate. Before depositing the second initial conductive layer, the method further includes: A second dielectric layer is formed, the second dielectric layer at least covering the inner wall of the second opening and the second surface located within the second opening; A second barrier layer is formed, which covers the second dielectric layer.

7. The method for fabricating a semiconductor device according to any one of claims 2 to 6, characterized in that, After forming the second conductive layer, the method further includes: The second conductive layer is then annealed.

8. The method for fabricating a semiconductor device according to claim 1, characterized in that, Before providing the trenched substrate, the method further includes: Provide substrate; A first dielectric layer is formed on the surface of the substrate to form the substrate; The first dielectric layer is patterned, and the trench is formed in the substrate, the trench penetrating the first dielectric layer, the exposed surface of the first dielectric layer being the first surface.

9. The method for fabricating a semiconductor device according to claim 1, characterized in that, Under the same etching conditions, the etching rate of the first auxiliary layer is higher than that of the substrate.

10. The method for fabricating a semiconductor device according to claim 1, characterized in that, The material of the first auxiliary layer has less ductility than the material of the first conductive layer.

11. A semiconductor device formed by the manufacturing method according to any one of claims 1-10, characterized in that, include: A substrate having a first surface and a second surface, the first surface and the second surface being disposed opposite to each other; At least one through hole penetrates the substrate along its thickness direction; A first dielectric layer and a first barrier layer, wherein the first dielectric layer only covers the sidewall of the via, and the first barrier layer only covers the sidewall of the first dielectric layer, and the first barrier layer is titanium nitride; A first conductive layer and a second conductive layer are filled in the through hole and completely fill the through hole, and the first conductive layer and the second conductive layer in the same through hole are connected; The top surface of the first conductive layer is flush with the first surface of the substrate.

12. The semiconductor device according to claim 11, characterized in that, The top surface of the second conductive layer is flush with the second surface of the substrate.

13. The semiconductor device according to claim 11, characterized in that, The second conductive layer includes a first portion and a second portion, wherein the top surface of the first portion is flush with the second surface of the substrate; The second portion is located on the second surface, and the surface of the second portion connected to the first portion covers a portion of the second surface.

14. The semiconductor device according to claim 13, characterized in that, The first part and the second part are connected as one unit.

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