Method of manufacturing a semiconductor structure
By employing anisotropic etching and trimming steps in semiconductor structure fabrication, the problem of controlling the opening morphology in traditional wet etching processes is solved, thereby improving the coverage of metal deposition and the reliability of semiconductor structures.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANGHAI DINGTAI JIANGXIN TECH CO LTD
- Filing Date
- 2022-09-30
- Publication Date
- 2026-07-03
AI Technical Summary
Traditional wet etching processes have difficulty in accurately controlling the opening morphology and angle, resulting in poor reliability of semiconductor structures.
Anisotropic etching and trimming steps are employed, and openings in vertical or specific directions are gradually formed through dry etching and photoresist trimming. The amount of etching and trimming is controlled to regulate the opening edge angle and morphology.
This improves the step coverage of metal deposition and enhances the reliability of semiconductor structures.
Smart Images
Figure CN115565944B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating a semiconductor structure. Background Technology
[0002] In semiconductor structures, passivation dielectric layers are typically used to provide stress buffering to protect the device and metal interconnect structure from damage and corrosion caused by subsequent processes such as cutting, cleaning, and packaging.
[0003] In traditional techniques, a combined wet and dry etching process is typically used to etch the dielectric layer to form openings, facilitating subsequent metal deposition in the front-side metallization process to ultimately form a semiconductor structure. However, this traditional technique has certain limitations. Because the wet etching used in traditional techniques is isotropic, it is difficult to accurately control the morphology and angle of the formed openings. This can lead to the formation of slopes or bowl-shaped morphologies on the edges of the openings, affecting the step coverage of metal deposition in the subsequent front-side metallization process, and consequently resulting in a semiconductor structure with poor reliability. Summary of the Invention
[0004] Therefore, it is necessary to provide a method for fabricating semiconductor structures to address the problem of poor reliability in existing technologies.
[0005] To achieve the above objectives, the present invention provides a method for preparing a semiconductor structure, comprising:
[0006] Formation of a passivation dielectric layer;
[0007] A patterned photoresist layer is formed on the upper surface of the passivation dielectric layer, and the patterned photoresist layer has an opening pattern;
[0008] The etching and trimming steps include: anisotropic etching of the passivation dielectric layer based on the patterned photoresist layer; and trimming of the patterned photoresist layer to increase the size of the opening pattern.
[0009] The etching and trimming steps are repeated several times to form a first opening within the passivation dielectric layer.
[0010] In one embodiment, a dry etching process is used to anisotropically etch the passivation dielectric layer based on a patterned photoresist layer, and the etching gas used to etch the passivation dielectric layer includes a fluorine-based gas.
[0011] In one embodiment, a resist stripper is used to trim the patterned photoresist layer based on a photoresist trimming gas; the photoresist trimming gas includes at least one of oxygen, nitrogen, carbon monoxide, carbon dioxide, and hydrogen.
[0012] In one embodiment, the passivation dielectric layer includes a first passivation dielectric layer and a second passivation dielectric layer, and forming the passivation dielectric layer includes:
[0013] Forming the first passivation dielectric layer;
[0014] A second passivation medium layer is formed on the upper surface of the first passivation medium layer.
[0015] In one embodiment, the etching and trimming steps include:
[0016] The second passivation dielectric layer is anisotropically etched based on the patterned photoresist layer;
[0017] The patterned photoresist layer is trimmed to increase the size of the opening pattern.
[0018] In one embodiment, repeating the etching and trimming steps several times to form a first opening within the passivation dielectric layer includes:
[0019] Repeat the etching and trimming steps several times until the first opening exposes the first passivation dielectric layer.
[0020] In one embodiment, after repeating the etching and trimming steps several times to form a first opening within the passivation dielectric layer, the method further includes:
[0021] The first passivation dielectric layer is etched to form a second opening within the first passivation dielectric layer, the second opening being connected to the first opening.
[0022] In one embodiment, after etching the first passivation dielectric layer to form a second opening within the first passivation dielectric layer, the method further includes:
[0023] Remove the patterned photoresist layer.
[0024] In one embodiment, the first passivation dielectric layer is etched using a dry etching process, and the etching gas used to etch the first passivation dielectric layer includes a fluorine-based gas.
[0025] In one embodiment, the method further includes, prior to forming the passivation dielectric layer:
[0026] A metal layer is formed; the passivation dielectric layer is located on the upper surface of the metal layer or covers the metal layer.
[0027] The above-described semiconductor structure fabrication method involves forming a passivation dielectric layer; forming a patterned photoresist layer on the upper surface of the passivation dielectric layer, the patterned photoresist layer having an opening pattern; and performing etching and trimming steps, including: anisotropic etching of the passivation dielectric layer based on the patterned photoresist layer; trimming the patterned photoresist layer to increase the size of the opening pattern; and repeating the etching and trimming steps several times to form a first opening within the passivation dielectric layer. Since the etching and trimming amounts in each etching and trimming step can be controlled as needed, the angle and morphology of the first opening's edges can be accurately adjusted, thereby overcoming the limitations of traditional wet etching processes. This allows for increased step coverage of metal deposition in subsequent processes, thus improving the reliability of the formed semiconductor structure. Attached Figure Description
[0028] To more clearly illustrate the technical solutions in the embodiments of this application or the conventional technology, the drawings used in the description of the embodiments or the conventional technology will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0029] Figure 1 This is a schematic flowchart of a method for fabricating a semiconductor structure provided in one embodiment;
[0030] Figure 2 This is a schematic cross-sectional view of the structure obtained in step S102 of the semiconductor structure fabrication method provided in one embodiment;
[0031] Figure 3 This is a schematic cross-sectional view of the structure obtained after the etching step in step S103 of the semiconductor structure fabrication method provided in one embodiment.
[0032] Figure 4 This is a schematic cross-sectional view of the structure obtained after the trimming step in step S103 of the semiconductor structure fabrication method provided in one embodiment.
[0033] Figure 5 This is a schematic cross-sectional view of the structure obtained after the second etching step in step S104 of the semiconductor structure fabrication method provided in one embodiment.
[0034] Figure 6 This is a schematic cross-sectional view of the structure obtained after the second trimming step in step S104 of the semiconductor structure fabrication method provided in one embodiment.
[0035] Figure 7This is a schematic cross-sectional view of the structure obtained after repeated etching and trimming steps in step S104 of the semiconductor structure fabrication method provided in one embodiment.
[0036] Figure 8 This is a flowchart illustrating the sub-steps that may be included in step S101 of the semiconductor structure fabrication method provided in one embodiment.
[0037] Figure 9 This is a schematic cross-sectional view of the structure obtained in step S1012 of the semiconductor structure fabrication method provided in one embodiment.
[0038] Figure 10 This is a flowchart illustrating the sub-steps that may be included in step S103 of the semiconductor structure fabrication method provided in one embodiment.
[0039] Figure 11 This is a schematic cross-sectional view of the structure obtained in step S1031 of the semiconductor structure fabrication method provided in one embodiment.
[0040] Figure 12 This is a schematic cross-sectional view of the structure obtained in step S1032 of the semiconductor structure fabrication method provided in one embodiment;
[0041] Figure 13 This is a schematic diagram of the cross-sectional structure of the semiconductor structure obtained by repeating the etching and trimming steps several times until the first opening exposes the first passivation dielectric layer in a semiconductor structure fabrication method provided in one embodiment.
[0042] Figure 14 This is a schematic cross-sectional view of the structure obtained after etching the first passivation dielectric layer to form a second opening in the first passivation dielectric layer in a semiconductor structure fabrication method provided in one embodiment.
[0043] Figure 15 This is a schematic cross-sectional view of the structure obtained after removing the patterned photoresist layer in a semiconductor structure fabrication method provided in one embodiment.
[0044] Figure 16 This is a schematic cross-sectional view of the structure obtained after forming a metal layer in a semiconductor structure fabrication method provided in one embodiment.
[0045] Figure 17 This is a schematic cross-sectional view of a semiconductor structure prepared by the semiconductor structure preparation method provided in any of the above embodiments in one example;
[0046] Explanation of reference numerals in the attached figures: 10-passivation dielectric layer, 101-first passivation dielectric layer, 102-second passivation dielectric layer, 20-patterned photoresist layer, 201-opening pattern, 30-initial opening, 301-first opening, 302-second opening, 40-metal layer. Detailed Implementation
[0047] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings, which illustrate embodiments of the present application. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that the disclosure of this application will be thorough and complete.
[0048] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.
[0049] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, parts, regions, layers, doping types, and / or portions, these elements, parts, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, part, region, layer, doping type, or portion from another element, part, region, layer, doping type, or portion. Therefore, without departing from the teachings of this invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.
[0050] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, the element or feature described as “below,” “under,” or “below” will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. Furthermore, the device may also include other orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptive terms used herein will be interpreted accordingly.
[0051] When used herein, the singular forms of “a,” “an,” and “ / the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, in this specification, the term “and / or” includes any and all combinations of the associated listed items.
[0052] Embodiments of the invention are described herein with reference to cross-sectional views illustrating ideal embodiments (and intermediate structures) of the invention, thus allowing for variations in the illustrated shape due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing techniques. For instance, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of regions of the device and do not limit the scope of the invention.
[0053] Please see Figure 1 The present invention provides a method for preparing a semiconductor structure, comprising the following steps:
[0054] S101: Formation of a passivation dielectric layer;
[0055] S102: A patterned photoresist layer is formed on the upper surface of the passivation dielectric layer, and the patterned photoresist layer has an opening pattern;
[0056] S103: Perform etching and trimming steps, including: anisotropic etching of the passivation dielectric layer based on the patterned photoresist layer; trimming the patterned photoresist layer to increase the size of the opening pattern;
[0057] S104: Repeat the etching and finishing steps several times to form the first opening in the passivation dielectric layer.
[0058] In step S101, please refer to Figure 1 Step S101 and Figure 2 A passivation dielectric layer 10 is formed.
[0059] The passivation dielectric layer 10 may include one or a combination of silicon oxide, silicon oxynitride, silicon oxycarbonate, and silicon oxynitride-carbonate, and this embodiment is not limited thereto.
[0060] In step S102, please refer to Figure 1 Step S102 and Figure 2 A patterned photoresist layer 20 is formed on the upper surface of the passivation dielectric layer 10, and the patterned photoresist layer 20 has an opening pattern 201.
[0061] Optionally, a patterned photoresist layer 20 can be formed on the upper surface of the passivation dielectric layer 10 by first coating a photoresist layer on the upper surface of the passivation dielectric layer 10 and then performing processes such as exposure and development.
[0062] In step S103, please refer to Figure 1 Step S103 and Figure 3 and Figure 4 The etching and trimming steps include: anisotropic etching of the passivation dielectric layer 10 based on the patterned photoresist layer 20; and trimming of the patterned photoresist layer 20 to increase the size of the opening pattern 201.
[0063] Anisotropic etching refers to an etching method that exhibits different etching rates in different etching directions. In the field of semiconductor technology, it is commonly used for vertical downward etching to form vertical openings, or etching in other specific directions to form openings. For example, ... Figure 3 As shown, a vertical initial opening 3 is formed in the passivation dielectric layer 10 by anisotropic etching.
[0064] In step S104, please refer to Figure 1 Step S104 and Figures 3 to 7 The etching and finishing steps are repeated several times to form the first opening 301 in the passivation dielectric layer 10.
[0065] To better understand this solution, the etching and finishing steps were repeated several times. Figure 3This can be considered an example of the structure obtained after the first etching step. Figure 4 This can be considered as an example of the structure obtained after the first trimming step. Of course, the structure obtained after the first etching step can also be other suitable structures, and the structure obtained after the first trimming step can also be other suitable structures. This embodiment does not impose any limitations on this.
[0066] like Figure 3 As shown, after the first etching step, part of the passivation dielectric layer 10 is removed to form an initial opening 30 within the passivation dielectric layer 10. At this time, the initial opening 30 has the same size as the opening pattern 201. Figure 3 As shown, the etching amount in the first etching step can be represented by e1.
[0067] like Figure 4 As shown, after the first trimming step, part of the patterned photoresist layer 20 is removed to increase the size of the opening pattern 201. Figure 4 As shown, after the first trimming step, the trimming amount of the patterned photoresist layer 20 can be represented by t1.
[0068] like Figure 5 As shown, based on the patterned photoresist layer 20 after the first trimming step, a second etching step is performed. After the second etching step, the size of the initial opening 30 is enlarged, and the depth of the initial opening 30 is further increased. Figure 5 As shown, the etching amount in the second etching step can be represented by e2.
[0069] like Figure 6 As shown, a second trimming step is performed on the patterned photoresist layer 20. After the second trimming step, a portion of the patterned photoresist layer 20 is removed again to further increase the size of the opening pattern 201, as shown. Figure 6 As shown, after the second trimming step, the trimming amount of the patterned photoresist layer 20 can be represented by t2.
[0070] like Figure 7 As shown, when the etching and trimming amounts in each etching and trimming step are sufficiently small, after repeating the etching and trimming steps several times, the initial opening 30 is formed as shown. Figure 7 The shape of the first opening 301 is shown. If the etching and trimming steps are repeated N times, the etching amount of the Nth etching step can be represented by eN, and the trimming amount of the Nth trimming step can be represented by tN.
[0071] The etching and trimming steps are performed alternately and cyclically. Optionally, the etching amount in each etching step can be the same (e.g., e1 = e2 = ... = eN), or they can be different (e.g., e1 ≠ e2 ≠ ... ≠ eN), or they can be partially the same (e.g., e1 = e2 ≠ ... ≠ eN). Similarly, the trimming amount in each trimming step can be the same (e.g., t1 = t2 = ... = tN), or they can be different (e.g., t1 ≠ t2 ≠ ... ≠ tN), or they can be partially the same (e.g., t1 = t2 ≠ ... ≠ tN). Specifically, the etching amount in each etching step and the trimming amount in each trimming step can be determined according to different application requirements.
[0072] Furthermore, the cycle time for alternating etching and trimming steps can be the same. In this case, the etching amount in each etching step is the same, and the trimming amount in each trimming step is also the same.
[0073] In addition, to facilitate understanding of this solution, Figure 5 The initial opening 30 shown in the figure has a stepped side morphology. However, in the actual fabrication process, when the cycle time is sufficiently short, the etching and trimming amounts in each etching and trimming step are relatively small. Therefore, the final side morphology of the first opening 301 will be closer to that shown in the figure. Figure 7 The cone shape shown. Of course. Figure 7 The example provided is merely a preferred one; the angles and morphologies of the sides of the first opening 301 are not limited to this. Figure 7 The angles and morphologies shown can be adjusted by changing the cycle time of the alternating etching and trimming steps, as well as the etching and trimming amounts, so that other angles and other morphologies can be formed on the sides of the first opening 301 to meet different needs.
[0074] In this embodiment, a passivation dielectric layer is formed, and a patterned photoresist layer with an opening pattern is formed on the upper surface of the passivation dielectric layer. An etching and trimming step is performed, including: anisotropic etching of the passivation dielectric layer based on the patterned photoresist layer; trimming the patterned photoresist layer to increase the size of the opening pattern; and repeating the etching and trimming step several times to form a first opening within the passivation dielectric layer. Since the etching and trimming amounts in each step can be controlled as needed, the angle and morphology of the first opening's edges can be accurately adjusted, thereby overcoming the limitations of traditional techniques and increasing the step coverage of metal deposition in subsequent processes, thus improving the reliability of the formed semiconductor structure.
[0075] In one embodiment, a dry etching process is used to anisotropically etch the passivation dielectric layer 10 based on the patterned photoresist layer 20, and the etching gas used to etch the passivation dielectric layer 10 includes a fluorine-based gas.
[0076] By adjusting parameters such as the gas ratio of the etching gas, the plasma source power and bias power, and the etching temperature, the etching amount of the etching step can be accurately adjusted, thereby adjusting the angle, size and morphology of the side of the final first opening 301.
[0077] The fluorine-based gas can be one or more of CF4, CHF3, and CH2F2, and this embodiment does not impose any limitations. Inert gases such as argon can also be added to the fluorine-based gas to dilute it.
[0078] In one embodiment, a photoresist stripper is used to trim the patterned photoresist layer 20 based on a photoresist trimming gas; the photoresist trimming gas includes at least one of oxygen, nitrogen, carbon monoxide, carbon dioxide, and hydrogen.
[0079] Please see Figure 8 In one embodiment, the passivation dielectric layer 10 may include a first passivation dielectric layer 101 and a second passivation dielectric layer 102. The above step S101 may include the following steps:
[0080] S1011: Forming the first passivation dielectric layer;
[0081] S1012: A second passivation dielectric layer is formed on the upper surface of the first passivation dielectric layer.
[0082] In step S1011, please refer to Figure 8 Step S1011 and Figure 9 The first passivation dielectric layer 101 is formed.
[0083] In step S1011, please refer to Figure 8 Step S1011 and Figure 9 A second passivation medium layer 102 is formed on the upper surface of the first passivation medium layer 101.
[0084] The first passivation dielectric layer 101 and the second passivation dielectric layer 102 can be made of different materials. For example, the first passivation dielectric layer 101 can be a silicon oxynitride layer, and the second passivation dielectric layer 102 can be a silicon dioxide layer. Of course, the first passivation dielectric layer 101 and the second passivation dielectric layer 102 can also be made of other suitable materials, which are not limited in this embodiment.
[0085] Please see Figure 10 Based on the above embodiments, in one embodiment, step S103 includes:
[0086] S1031: Anisotropic etching of the second passivation dielectric layer based on a patterned photoresist layer;
[0087] S1032: Trim the patterned photoresist layer to increase the size of the opening pattern.
[0088] In step S1031 above, please refer to Figure 10 Step S1031 and Figure 11 Anisotropic etching is performed on the second passivation dielectric layer 102 based on the patterned photoresist layer 20.
[0089] In step S1031 above, please refer to Figure 10 Step S1031 and Figure 12 The patterned photoresist layer 20 is trimmed to increase the size of the opening pattern 201.
[0090] Please combine Figures 3 to 7 as well as Figure 11 and Figure 12 And see Figure 13 Based on the above embodiments, in one embodiment, the above step S104 includes: repeating the etching and trimming steps several times until the first opening 301 exposes the first passivation dielectric layer 101.
[0091] In this embodiment, the steps for forming the first opening 301 and the beneficial effects are similar to those in the above embodiments, and will not be repeated here.
[0092] Please see Figure 14 Based on the above embodiments, in one embodiment, after step S104, the method further includes: etching the first passivation medium layer 101 to form a second opening 302 in the first passivation medium layer 101, the second opening 302 being connected to the first opening 301.
[0093] Optionally, a method similar to that used to form the first opening 301 in the above embodiment can be used to etch the first passivation dielectric layer 101 to form a second opening 302 within the first passivation dielectric layer 101, so that the morphology of the second opening 302 is as follows: Figure 14 The cone shape is shown. For example, a second patterned photoresist layer can be formed on the surface exposed by the first passivation layer, and the first passivation dielectric layer 101 can be repeatedly etched and trimmed based on the second patterned photoresist layer to form a second opening 302 in the first passivation dielectric layer 101. Finally, the second patterned photoresist layer can be removed. The steps for forming the second opening 302 and the beneficial effects are similar to those for forming the first opening 301, and will not be described again here. Of course, the shape of the second opening 302 can also be rectangular, etc., and this embodiment does not limit it.
[0094] In one embodiment, a dry etching process is used to etch the first passivation dielectric layer 101, and the etching gas used to etch the first passivation dielectric layer 101 includes a fluorine-based gas.
[0095] Please see Figure 15 Based on the above embodiments, in one embodiment, after etching the first passivation dielectric layer 101 to form the second opening 302 in the first passivation dielectric layer 101, the method further includes: removing the patterned photoresist layer 20.
[0096] Please see Figure 16 Based on the above embodiments, in one embodiment, before step S101, the method further includes: forming a metal layer 40; and a passivation dielectric layer 10 located on the upper surface of the metal layer 40 or covering the metal layer 40.
[0097] The material of the metal layer 40 may include metals such as copper, gold, titanium, silver, and aluminum, or it may include a multilayer metal composed of the above-mentioned metals, or it may include metal alloys, etc. This embodiment does not impose any limitations.
[0098] Based on the above embodiments, in one embodiment, please refer to... Figures 1 to 16 And see Figure 17 The first passivation dielectric layer 101 is located on the upper surface of the metal layer 40 or covers the metal layer 40, and the second passivation dielectric layer 102 is located on the upper surface of the first passivation dielectric layer 101. The second passivation dielectric layer 102 has a first opening 301 and a second opening 302. The second opening 302 is connected to the first opening 301 and exposes the metal layer 40.
[0099] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.
[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.
[0101] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.
Claims
1. A method of fabricating a semiconductor structure, characterized by, include: A passivation dielectric layer is formed; wherein the passivation dielectric layer includes a first passivation dielectric layer and a second passivation dielectric layer; the first passivation dielectric layer is a silicon oxynitride layer, and the second passivation dielectric layer is a silicon dioxide layer; A patterned photoresist layer is formed on the upper surface of the passivation dielectric layer, and the patterned photoresist layer has an opening pattern; The etching and trimming steps include: anisotropic etching of the passivation dielectric layer based on the patterned photoresist layer; trimming the patterned photoresist layer to increase the size of the opening pattern; wherein, the trimming of the patterned photoresist layer includes trimming the patterned photoresist layer using a photoresist trimming gas with a photoresist stripper. Repeating the etching and trimming steps several times to form a first opening in the passivation dielectric layer includes: repeating the etching and trimming steps several times until the first opening exposes the first passivation dielectric layer. The first passivation dielectric layer is etched to form a second opening within the first passivation dielectric layer, the second opening being connected to the first opening.
2. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The passivation dielectric layer is anisotropically etched using a dry etching process based on a patterned photoresist layer, and the etching gas used to etch the passivation dielectric layer includes a fluorine-based gas.
3. The method of claim 2, wherein the semiconductor structure is prepared by a method comprising: The fluorine-based gas is one or a combination of CF4, CHF3, and CH2F2.
4. The method for preparing a semiconductor structure according to claim 2, characterized in that, The fluorine-based gas contains an inert gas, including argon.
5. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The photoresist trimming gas includes at least one of oxygen, nitrogen, carbon monoxide, carbon dioxide, and hydrogen.
6. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The formation of the passivation dielectric layer includes: Forming the first passivation dielectric layer; A second passivation medium layer is formed on the upper surface of the first passivation medium layer.
7. The method of claim 6, wherein the semiconductor structure is prepared by a method comprising: The etching and finishing steps include: The second passivation dielectric layer is anisotropically etched based on the patterned photoresist layer; The patterned photoresist layer is trimmed to increase the size of the opening pattern.
8. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: After etching the first passivation dielectric layer to form a second opening within the first passivation dielectric layer, the method further includes: Remove the patterned photoresist layer.
9. The method of claim 1, wherein the semiconductor structure is prepared by a method comprising: The first passivation dielectric layer is etched using a dry etching process, and the etching gas used to etch the first passivation dielectric layer includes a fluorine-based gas.
10. The method of producing a semiconductor structure according to any one of claims 1 to 9, wherein The process further includes the following steps prior to forming the passivation dielectric layer: A metal layer is formed; the passivation dielectric layer is located on the upper surface of the metal layer or covers the metal layer.