A method of forming a semiconductor device

Abstract

The embodiment of the present disclosure provides a forming method of a semiconductor device, which comprises: providing a substrate, wherein the substrate comprises a first device region and a second device region; the first device region and the second device region are different in doping type; forming a first gate stack layer covering the first device region and the second device region; the first gate stack layer comprises a first work function metal layer and a first barrier layer which are stacked in sequence in a direction away from the substrate; forming a first mask pattern on the first gate stack layer, wherein the first mask pattern covers at least the first device region and exposes at least the second device region, the first mask pattern has a first size in a direction perpendicular to the substrate, and the area exposed by the first mask pattern has a second size in a direction parallel to the substrate, and the ratio of the minimum value of the second size to the first size is greater than 10; and removing the first gate stack layer on the area exposed by the first mask pattern by using a cycle process of etching and cleaning based on the first mask pattern.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and to, but is not limited to, a method for forming a semiconductor device. Background Technology

[0002] With the continuous development of semiconductor devices, the feature size of transistors in semiconductor devices is constantly shrinking. This shrinking feature size brings greater challenges to transistor performance. Current transistor fabrication technology still has shortcomings, and how to optimize transistor fabrication technology to stabilize transistor performance has become an urgent problem to be solved at this stage. Summary of the Invention

[0003] In view of this, the main objective of this disclosure is to provide a method for forming a semiconductor device.

[0004] To achieve the above objectives, the technical solution disclosed herein is implemented as follows:

[0005] This disclosure provides a method for forming a semiconductor device, the method comprising:

[0006] A substrate is provided, the substrate including a first device region and a second device region; wherein the first device region and the second device region have different doping types;

[0007] A first gate stack layer is formed covering the first device region and the second device region; the first gate stack layer includes a first work function metal layer and a first barrier layer sequentially stacked along a direction away from the substrate.

[0008] A first mask pattern is formed on the first gate stack layer, the first mask pattern at least covers the first device region and at least exposes the second device region, wherein the first mask pattern has a first size in a direction perpendicular to the substrate, the area exposed by the first mask pattern has a second size in a direction parallel to the substrate, and the ratio of the minimum value of the second size to the first size is greater than 10.

[0009] Based on the first mask pattern, an etch-clean cycle process is used to remove the first gate stack layer on the area exposed by the first mask pattern.

[0010] In the above scheme, the step of removing the first gate stack layer on the area exposed by the first mask pattern using an etch-clean cycle process based on the first mask pattern includes:

[0011] An etching operation is performed on the first gate stack layer on the area exposed by the first mask pattern using an etching solution;

[0012] Deionized water was used for the cleaning operation;

[0013] The etching and cleaning operations are performed cyclically until the first gate stack layer and the byproducts generated during the etching of the first gate stack layer are removed.

[0014] In the above scheme, the first size ranges from 50nm to 90nm.

[0015] In the above scheme, the number of times the etching operation and the cleaning operation are performed in a cycle ranges from 2 to 10.

[0016] In the above scheme, the process parameters of the etching operation include:

[0017] The temperature range of the etching operation is 20°C to 80°C, and the time range of a single etching operation is 30 to 200 seconds.

[0018] In the above scheme, the process parameters of the cleaning operation include:

[0019] The time range for a single cleaning operation is 10 to 30 seconds.

[0020] In the above scheme, the etching solution includes a mixture of ammonia and hydrogen peroxide.

[0021] In the above scheme, before the step of forming the first gate stack layer, the following steps are included:

[0022] A gate oxide layer and a high-dielectric material layer are sequentially formed to cover the first device region and the second device region.

[0023] In the above scheme, after removing the first gate stack layer on the area exposed by the first mask pattern based on the first mask pattern, the process includes:

[0024] A second gate stack layer is formed in the region where the first gate stack layer has been removed; the second gate stack layer includes a second work function metal layer and a second barrier layer stacked sequentially away from the substrate, wherein the first work function metal layer is different from the second work function metal layer.

[0025] In the above scheme, the first work function metal layer is an N-type work function metal layer and the second work function metal layer is a P-type work function metal layer; or, the first work function metal layer is a P-type work function metal layer and the second work function metal layer is an N-type work function metal layer.

[0026] In the above scheme, after forming the second gate stack layer, the following steps are included:

[0027] A third barrier layer is formed covering the first gate stack layer and the second gate stack layer;

[0028] A layer of metallic conductive material is formed covering the third barrier layer;

[0029] The metal conductive material layer, the third barrier layer, the first gate stack layer, and the second gate stack layer are etched to form a first gate structure and a second gate structure.

[0030] In the above scheme, after forming the second gate stack layer and before etching the metal conductive material layer, the third barrier layer, the first gate stack layer, and the second gate stack layer, the following method is further included:

[0031] Annealing is performed on the first gate stack layer and the second gate stack layer.

[0032] This disclosure provides a method for forming a semiconductor device. After forming a first gate stack layer on a first device region and a second device region with different doping types, the method controls the ratio of the minimum value of the second dimension to the first dimension of the first mask to be greater than 10. This allows for a reduction in etching depth and an increase in the contact area between the etching solution and deionized water and the first gate stack layer exposed by the first mask pattern during the etch-cleaning cycle process. This improves the etching-cleaning effect, effectively removing the first gate stack layer from the exposed area of ​​the first mask pattern, and thus enhancing the electrical performance of the final transistor device. Furthermore, cyclically performing etching and cleaning operations reduces the time required for each etching and cleaning cycle, preventing damage to the material layer beneath the first gate stack layer from prolonged single etching and cleaning operations, thereby improving product yield. Attached Figure Description

[0033] Figures 1A to 1D A schematic cross-sectional view of an intermediate process of a method for forming a semiconductor device according to an embodiment of the present disclosure;

[0034] Figure 2 This is a flowchart illustrating another method for forming a semiconductor device according to an embodiment of the present disclosure;

[0035] Figures 3A to 3G This is a schematic cross-sectional view illustrating the formation process of a semiconductor device according to an embodiment of the present disclosure. Detailed Implementation

[0036] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.

[0037] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.

[0038] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “below” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0039] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0040] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.

[0041] As the size of metal-oxide-semiconductor field-effect transistors (MOSFETs) continues to shrink, high-k metal gate (HKMG) technology has been widely used in transistor manufacturing processes. For example, HKMG technology is used in peripheral transistors of memory devices to replace traditional gate stack-up (gate oxide and polysilicon gate) technology.

[0042] Transistors are fabricated using high-dielectric-constant metal gate (HKMG) technology. High-dielectric materials, used as insulating materials, typically possess high dielectric constants and relatively large band gaps, exhibiting greater stability compared to silicon. Therefore, high-dielectric insulating layers made from these materials can improve transistor performance. HKMG technology not only significantly reduces gate leakage current but also effectively reduces gate capacitance due to the thinner equivalent oxide thickness (EOT) of the high-dielectric insulating layer. This allows for further miniaturization of the transistor's critical dimensions and significantly improves its driving capability.

[0043] Figures 1A to 1D This is a schematic cross-sectional view of an intermediate process of a method for forming a semiconductor device according to an embodiment of the present disclosure.

[0044] like Figure 1A As shown, the substrate 100 includes a first region 110 and a second region 120. Here, the example of forming a PMOS device on the first region 100 and an NMOS device on the second region 120 will be described. Here, the substrate 100 can be a substrate of a single-element semiconductor material (e.g., a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a composite semiconductor material substrate (e.g., a germanium-silicon (SiGe) substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0045] It should be noted that in integrated circuit manufacturing, numerous active devices (such as PMOS and NMOS devices) are integrated simultaneously on substrate 100. To reduce mutual interference between devices, isolation techniques are required to isolate the active devices from each other. (Reference) Figure 1A An isolation region 130 is present on the substrate 100 to isolate adjacent first regions 110 and second regions 120 from each other.

[0046] Because PMOS and NMOS devices have different threshold voltages, to simultaneously meet the threshold voltage requirements of both PMOS and NMOS devices, a common practice is to first cover the first and second regions with a work function metal layer (e.g., a P-type work function metal layer). Then, the work function metal layer in the second region is removed, leaving it only in the first region. A different type of work function metal layer is then formed in the first region. By using different types of work function metal layers, the work function of the PMOS and NMOS devices can be adjusted separately, thereby enabling the threshold voltages of the PMOS and NMOS devices to meet the design specifications.

[0047] refer to Figure 1A A gate oxide layer 101, a high dielectric material layer 102, a stacked structure 108, a bottom anti-reflection coating (BARC) layer 106, and a photoresist layer 107 are sequentially deposited on a substrate 100.

[0048] In some embodiments, the stacked structure 108 includes a bottom barrier layer 103, a work function metal layer 104, and a top barrier layer 105. Exemplarily, the bottom barrier layer 103 and the top barrier layer 105 are made of titanium nitride (TiN). The work function metal layer 104 in the stacked structure 108 is a P-type work function metal layer, used to adjust the work function value of the gate structure of the PMOS device subsequently formed in the first region 110, thereby enabling control of the threshold voltage of the PMOS device ultimately formed on the first region 110. Since the work functions of PMOS and NMOS devices differ, work function metal layers of different materials are required. Therefore, when forming a NMOS device on the second region 120, the stacked structure 108 located on the second region 120 needs to be removed.

[0049] refer to Figure 1B A patterned photoresist layer 107 is formed to create a mask pattern 109, which covers areas other than the second region 120, such as the first region 110. The mask pattern 109 exposes a bottom anti-reflective layer 106 located on the second region 120.

[0050] refer to Figure 1C The bottom anti-reflective layer 106 is etched based on the mask pattern 109.

[0051] refer to Figure 1D The top barrier layer 105, work function metal layer 104, and bottom barrier layer 103 in the stacked structure 108 on the second region 120 are removed using a wet etching process. Specifically, an etching solvent including an ammonia-hydrogen peroxide mixture, such as SC1 cleaning solution, can be used to remove the top barrier layer 105, work function metal layer 104, and bottom barrier layer 103.

[0052] Both the top barrier layer 105 and the bottom barrier layer 103 are made of titanium nitride. During the removal of the stacked structure 108, the SC1 cleaning solution will produce... Figure 1D The byproduct 110 shown is titanium oxynitride (TiON). Residual byproducts from the wet etching process used to remove the stacked structure 108 can affect the electrical performance of the formed transistor device, hindering product yield improvement.

[0053] Figure 2 This is a schematic flowchart illustrating a method for forming a semiconductor device according to another embodiment of the present disclosure. The present disclosure provides a method for forming a semiconductor device, such as... Figure 2 As shown, the formation method specifically includes the following steps:

[0054] Step S10: Provide a substrate, the substrate including a first device region and a second device region; wherein the first device region and the second device region have different doping types;

[0055] Step S20: Form a first gate stack layer covering the first device region and the second device region; the first gate stack layer includes a first work function metal layer and a first barrier layer sequentially stacked along the direction away from the substrate;

[0056] Step S30: Form a first mask pattern on the first gate stack layer. The first mask pattern at least covers the first device region and at least exposes the second device region. The first mask pattern has a first size in a direction perpendicular to the substrate, and the area exposed by the first mask pattern has a second size in a direction parallel to the substrate. The ratio of the minimum value of the second size to the first size is greater than 10.

[0057] Step S40: Based on the first mask pattern, the first gate stack layer on the area exposed by the first mask pattern is removed using an etch-clean cycle process.

[0058] Figures 3A to 3G This is a schematic cross-sectional view of a method for forming a semiconductor device according to an embodiment of the present disclosure.

[0059] refer to Figure 3A The substrate 301 includes a first device region A1 and a second device region A2; wherein the first device region and the second device region have different doping types. Here, the example is given where the first device region A1 is a P-type device region and the second device region A2 is an N-type device region. For example, a PMOS device can be formed in the first device region A1 and an NMOS device can be formed in the second device region A2.

[0060] To reduce mutual interference between devices, isolation techniques are needed to isolate active devices from each other. (Reference) Figure 3A At least one isolation region 300 exists on the substrate 301 to isolate adjacent first device region A1 and second device region A2 from each other. The isolation region may include a trench isolation region or a field oxide isolation region. In a specific example, the trench isolation region can be formed using a trench isolation process. For example, the isolation region 300 can be formed by photolithography, etching, and filling trenches with a trench dielectric material. The trench dielectric material can be any suitable dielectric material, such as silicon nitride.

[0061] In some implementations, the field oxide isolation region can be formed using a local oxidation of silicon (LOCOS) process.

[0062] refer to Figure 3A A gate oxide layer 302 and a high-dielectric material layer 303 are sequentially formed covering the first device region A1 and the second device region A2. In some embodiments, the gate oxide layer 302 is formed by methods including, but not limited to, in-situ steam generation (ISSG), physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD). Exemplarily, the material of the gate oxide layer 302 includes, but is not limited to, oxides, such as silicon oxide.

[0063] In some embodiments, the deposition process for forming the high dielectric material layer 303 includes, but is not limited to, chemical vapor deposition, physical vapor deposition, atomic layer deposition, metal-organic chemical vapor deposition, evaporation, plasma-assisted chemical vapor deposition, reactive sputtering, chemical solution deposition or other similar deposition processes, or any combination thereof.

[0064] For example, the high-dielectric material layer 303 includes a thin film with a dielectric constant greater than that of the silicon dioxide thin film. The materials of the high-dielectric material layer 303 include, but are not limited to, hafnium oxide (HfO2), hafnium oxynitride (HfON), titanium oxide (TiO2), aluminum oxide (Al2O3), zirconium oxide (ZrO2), hafnium oxynitride silicon (HfSiON), hafnium silicon oxide (HfSiO4), zirconium silicon oxide (ZrSiO2), yttrium oxide (Y2O3), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), hafnium zirconium oxide (HfZrO), strontium titanate (SrTiO3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), hafnium titanium oxide (HfTiO), barium titanate (BaTiO3), rare earth element oxides, rare earth element hydrides, and other materials.

[0065] refer to Figure 3A Step S20 is executed to form a first gate stack layer 309 covering the first device region A1 and the second device region A2. The first gate stack layer 309 includes a first work function metal layer 305 and a first barrier layer 306 sequentially stacked along the direction away from the substrate. In some embodiments, the first gate stack layer 309 further includes a first bottom barrier layer 304.

[0066] In some embodiments, when the first device region A1 is a P-type device region, the first work function metal layer 305 is a P-type work function metal layer used to adjust the work function of the PMOS device, thereby enabling the threshold voltage of the PMOS device to reach the threshold voltage that meets the design specifications. The material of the first work function metal layer 305 includes, but is not limited to, at least one of aluminum oxide (Al2O3), magnesium oxide (MgO), and calcium oxide (CaO). In a preferred embodiment, the material of the first work function metal layer 305 is aluminum oxide (Al2O3).

[0067] In some embodiments, a first bottom barrier layer 304 is used to prevent the high-dielectric material layer 303 and the first work function metal layer 305 from reacting and affecting the work function value of the first work function metal layer 305. The material of the first bottom barrier layer 304 includes, but is not limited to, titanium nitride or tantalum nitride. A first barrier layer 306 is used to block the downward diffusion of metal from the subsequently formed metal conductive material layer, preventing the metal diffusion of the metal conductive material layer from affecting the work function value of the first work function metal layer 305, thereby keeping the threshold voltage of the PMOS device stable. The material of the first barrier layer 306 is titanium nitride.

[0068] refer to Figure 3AStep S30 is executed to form a first mask pattern 308 on the first gate stack layer 309. In some embodiments, to eliminate the standing wave effect, a bottom anti-reflective coating 307 may be added to the bottom of the first mask pattern 308. The first mask pattern 308 at least covers the first device region A1 and at least exposes the second device region A2, wherein the first mask pattern 308 has a first dimension H1 in a direction perpendicular to the substrate, and the exposed area of ​​the first mask pattern 308 has a second dimension in a direction parallel to the substrate, wherein the ratio of the minimum value W1 of the second dimension to the first dimension H1 is greater than 10.

[0069] In some embodiments, the first mask pattern is photoresist (PR), and the size of the first dimension can be controlled by process parameters (e.g., viscosity, rotation speed, temperature, etc.) used to form the photoresist. For example, by controlling the viscosity to be less than 5 centipoise (cP) or the rotation speed to be in the range of 3000 rpm to 10000 rpm, the first dimension is controlled to be below 100 nm; specifically, the first dimension is controlled to be in the range of 50 nm to 90 nm.

[0070] In some embodiments, the first mask pattern is a hard mask (HM), and the deposition process for forming the hard mask includes, but is not limited to, chemical vapor deposition. The size of the first dimension can be controlled by process parameters during the deposition process, or the size of the first dimension can be controlled by an etch-back method.

[0071] In this embodiment of the disclosure, the first size ranges from 50nm to 90nm.

[0072] It should be noted that the second dimension of the area exposed by the first mask pattern in the direction parallel to the substrate has multiple values, and the area exposed by the first mask pattern can specifically be the second device region. Figure 3A The minimum value W1 of the second dimension shown is merely an example, representing that in Figure 3A In the embodiment shown, the dimension of the second device region A2 along the arrangement direction of the first device region A1 and the second device region A2 is the minimum value of the second dimension, and the scope of protection of this disclosure should not be excessively limited here.

[0073] refer to Figures 3A to 3B Based on the first mask pattern 308, the bottom anti-reflective coating 307 on the area exposed by the first mask pattern 308 is removed. In some embodiments, the bottom anti-reflective coating 307 on the area exposed by the first mask pattern 308 can be removed by an ash-ing process (ASH).

[0074] refer to Figures 3B to 3CIn step S40, based on the first mask pattern 308, an etch-clean cycle process is used to remove the first gate stack layer 309 on the area exposed by the first mask pattern 308.

[0075] In this embodiment of the disclosure, based on the first mask pattern, an etch-clean cycle process is used to remove the first gate stack layer on the area exposed by the first mask pattern, including:

[0076] An etching operation is performed on the first gate stack layer 309 on the area exposed by the first mask pattern 308 using an etching solution;

[0077] Deionized water was used for the cleaning operation;

[0078] The etching and cleaning operations are performed cyclically until the first gate stack layer 309 and the byproducts generated during the etching of the first gate stack layer 309 are removed.

[0079] Since the ratio of the minimum value of the second dimension to the first dimension is greater than 10, the etching depth can be reduced and the contact area between the etching solution and deionized water and the first gate stack layer exposed in the first mask pattern can be increased during the etching-cleaning cycle process to remove the first gate stack layer. This improves the etching-cleaning effect and effectively removes the first gate stack layer and the byproducts generated during the etching of the first gate stack layer.

[0080] In addition, cyclically performing etching and cleaning operations can reduce the time spent on each etching and cleaning operation, prevent damage to the material layer below the first gate stack layer caused by prolonged single etching and cleaning, and help improve product yield.

[0081] In this embodiment of the disclosure, the number of times the etching and cleaning operations are performed cycle-by-cycle ranges from 2 to 10. For example, when the first mask pattern is photoresist, the number of times the etching and cleaning operations are performed cycle-by-cycle is 2 to 4; when the first mask pattern is a hard mask, the number of times the etching and cleaning operations are performed cycle-by-cycle is 2 to 10.

[0082] In this embodiment of the disclosure, the process parameters for the etching operation include: the temperature range of the etching operation is 20°C to 80°C, and the time range of a single etching operation is 30 to 200 seconds.

[0083] In some embodiments, the etching operation temperature may be 25°C, 40°C, or 60°C. In a preferred embodiment, the etching operation temperature is 40°C.

[0084] In some embodiments, when the first mask pattern is photoresist, the time range of a single etching operation is 100 to 200 seconds; when the first mask pattern is a hard mask, the time range of a single etching operation is 30 to 200 seconds.

[0085] In this embodiment of the disclosure, the process parameters for the cleaning operation include: the time range for a single cleaning operation is 10 to 30 seconds.

[0086] In this embodiment, the etching solution includes an ammonia-hydrogen peroxide mixed solution. In one specific embodiment, the etching solution includes, but is not limited to, SC1 cleaning solution, wherein the volume ratio of ammonia, hydrogen peroxide, and water in the SC1 cleaning solution is 1:1:5 to 1:2:10.

[0087] refer to Figure 3D After removing the first gate stack layer 309 on the area exposed by the first mask pattern 308, a second gate stack layer 310 is formed on the area where the first gate stack layer 309 has been removed. Specifically, the area where the first gate stack layer 309 has been removed can be the second device region A2. The second gate stack layer 310 includes a second work function metal layer 312 and a second barrier layer 313 sequentially stacked away from the substrate direction. The first work function metal layer 305 is different from the second work function metal layer 312. In some embodiments, the second gate stack layer 310 further includes a second bottom barrier layer 311.

[0088] In some embodiments, the first work function metal layer 305 is a P-type work function metal layer, and the second work function metal layer 312 is an N-type work function metal layer. The material of the second work function metal layer 312 includes, but is not limited to, at least one of lanthanum oxide (La₂O₃), scandium oxide (Sc₂O₃), yttrium oxide (Y₂O₃), tantalum oxide (Ta₂O₅), titanium oxide (TiO₂), and zirconium oxide (ZrO₂). In a preferred embodiment, the material of the second work function metal layer 312 is lanthanum oxide (La₂O₃).

[0089] In some embodiments, a second bottom barrier layer 311 is used to prevent the high-dielectric material layer 303 and the second work function metal layer 312 from reacting and affecting the work function value of the second work function metal layer 312. The material of the second bottom barrier layer 311 includes, but is not limited to, titanium nitride or tantalum nitride. A second barrier layer 313 is used to block the downward diffusion of metal from the subsequently formed metal conductive material layer, preventing the metal diffusion of the metal conductive material layer from affecting the work function value of the second work function metal layer 312, thereby keeping the threshold voltage of the PMOS device stable. The material of the second barrier layer 313 is titanium nitride.

[0090] In the embodiments of this disclosure, the first work function metal layer is an N-type work function metal layer and the second work function metal layer is a P-type work function metal layer; or, the first work function metal layer is a P-type work function metal layer and the second work function metal layer is an N-type work function metal layer.

[0091] In some embodiments, after forming the second gate stack layer, the first mask pattern 308 and the bottom anti-reflective coating 307 located on the first device region A1 are removed and an annealing process is performed to allow metal elements in the first work function metal layer and the second work function metal layer to diffuse to the interface between the high dielectric constant layer and the gate oxide layer to form an interface layer.

[0092] refer to Figure 3E After forming the second gate stack layer 310, a third barrier layer 314 is formed covering the first gate stack layer 309 and the second gate stack layer 310, and then a metal conductive material layer 315 is formed covering the third barrier layer 314.

[0093] In some embodiments, the processes for forming the third barrier layer 314 and the metal conductive material layer 315 include, but are not limited to, chemical vapor deposition, physical vapor deposition, and atomic layer deposition. Exemplarily, the material of the third barrier layer 314 includes, but is not limited to, titanium nitride, and the material of the metal conductive material layer 315 includes, but is not limited to, aluminum (Al), tungsten (W), copper (Cu), titanium nitride, and tungsten nitride.

[0094] In some embodiments, after forming the conductive metal material layer, an insulating capping layer may be formed to cover the conductive metal material layer and protect it from oxidation. Parts of the conductive metal material layer and the insulating capping layer will be etched in a subsequent etching process to form the gate structure.

[0095] In some embodiments, an annealing process is performed after forming the metal conductive material layer or the insulating capping layer to allow metal elements in the first work function metal layer and the second work function metal layer to diffuse to the interface between the high dielectric constant layer and the gate oxide layer to form an interface layer. Furthermore, the annealing process makes the metal conductive material layer more tightly bonded to the first gate stack layer and the second gate stack layer.

[0096] refer to Figure 3FAfter forming the conductive metal material layer 315, a composite mask layer 320 is formed covering the conductive metal material layer 315. Exemplarily, the composite mask layer 320 includes three layers, such as a silicon nitride layer 321, a spin-on hard mask (SOH) 322, and a silicon oxynitride layer 323. By forming a multi-layered composite mask layer 320, damage to the conductive metal material layer 315, the first gate stack layer 309, the second gate stack layer 310, the high-dielectric material layer 303, and the gate oxide layer 302 during subsequent etching processes is reduced.

[0097] Photoresist is coated onto the composite mask layer 320, followed by exposure and development to obtain a first photoresist 330 and a second photoresist 340 with mask patterns. The first photoresist 330 exposes the silicon oxynitride layer 323 to be removed in the first device region A1 and covers the silicon oxynitride layer 323 to be retained. The first photoresist 330 is used to define the first gate structure. The second photoresist 340 exposes the silicon oxynitride layer 323 to be removed in the second device region A2 and covers the silicon oxynitride layer 323 to be retained. The second photoresist 340 is used to define the second gate structure.

[0098] refer to Figure 3G The first photoresist 330 and the second photoresist 340 are etched onto the substrate 301 to remove part of the composite mask layer 320, the metal conductive material layer 315, the third barrier layer 314, the first gate stack layer 309, the second gate stack layer 310, the high dielectric material layer 303 and the gate oxide layer 302.

[0099] After removing the spin-coated hard mask 322 and the silicon oxynitride layer 323, a first gate structure 500 and a second gate structure 600 protected by the silicon oxynitride layer 321 are obtained. The first gate structure 500 includes a gate oxide layer 302, a high-dielectric material layer 303, a first gate stack layer 309, a third barrier layer 314, and a metal conductive material layer 315. The second gate structure 600 includes a gate oxide layer 302, a high-dielectric material layer 303, a second gate stack layer 310, a third barrier layer 314, and a metal conductive material layer 315.

[0100] In some embodiments, after the first gate structure and the second gate structure are formed, the source and drain are formed in the substrate exposed on both sides of the first gate structure and the second gate structure.

[0101] This disclosure provides a method for forming a semiconductor device. After forming a first gate stack layer on a first device region and a second device region with different doping types, the method controls the ratio of the minimum value of the second dimension to the first dimension of the first mask to be greater than 10. This allows for a reduction in etching depth and an increase in the contact area between the etching solution and deionized water and the first gate stack layer exposed by the first mask pattern during the etch-cleaning cycle process. This improves the etching-cleaning effect, effectively removing the first gate stack layer from the exposed area of ​​the first mask pattern, and thus enhancing the electrical performance of the final transistor device. Furthermore, cyclically performing etching and cleaning operations reduces the time required for each etching and cleaning cycle, preventing damage to the material layer beneath the first gate stack layer from prolonged single etching and cleaning operations, thereby improving product yield.

[0102] It should be understood that the phrases "an embodiment" or "some embodiments" throughout the specification mean that a specific feature, structure, or characteristic related to an embodiment is included in at least one embodiment of this disclosure. Therefore, "in an embodiment" or "in some embodiments" appearing throughout the specification do not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0103] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for forming a semiconductor device, characterized in that, The forming method includes: A substrate is provided, the substrate including a first device region and a second device region; wherein the first device region and the second device region have different doping types; A gate oxide layer and a high-dielectric material layer are sequentially formed to cover the first device region and the second device region; A first gate stack layer is formed covering the first device region and the second device region; the first gate stack layer includes a first work function metal layer and a first barrier layer sequentially stacked along a direction away from the substrate. A first mask pattern is formed on the first gate stack layer, the first mask pattern at least covers the first device region and at least exposes the second device region, wherein the first mask pattern has a first size in a direction perpendicular to the substrate, the area exposed by the first mask pattern has a second size in a direction parallel to the substrate, and the ratio of the minimum value of the second size to the first size is greater than 10. Based on the first mask pattern, the first gate stack layer on the area exposed by the first mask pattern is removed by an etch-clean cycle process; A second gate stack layer is formed on the region where the first gate stack layer has been removed; the second gate stack layer includes a second work function metal layer and a second barrier layer stacked sequentially away from the substrate, wherein the first work function metal layer is different from the second work function metal layer.

2. The forming method according to claim 1, characterized in that, The step of removing the first gate stack layer on the area exposed by the first mask pattern using an etch-clean cycle process based on the first mask pattern includes: An etching operation is performed on the first gate stack layer on the area exposed by the first mask pattern using an etching solution; Deionized water was used for the cleaning operation; The etching and cleaning operations are performed cyclically until the first gate stack layer and the byproducts generated during the etching of the first gate stack layer are removed.

3. The forming method according to claim 1, characterized in that, The first size ranges from 50nm to 90nm.

4. The method according to claim 2, characterized in that, The number of times the etching and cleaning operations are performed is between 2 and 10.

5. The method according to claim 4, characterized in that, The process parameters for the etching operation include: The etching operation has a temperature range of 20°C to 80°C, and the time range for a single etching operation is 30 to 200 seconds.

6. The method according to claim 5, characterized in that, The process parameters for the cleaning operation include: The time range for a single cleaning operation is 10 to 30 seconds.

7. The method according to claim 2, characterized in that, The etching solution includes a mixture of ammonia and hydrogen peroxide.

8. The forming method according to claim 1, characterized in that, The first work function metal layer is an N-type work function metal layer, and the second work function metal layer is a P-type work function metal layer; or, the first work function metal layer is a P-type work function metal layer, and the second work function metal layer is an N-type work function metal layer.

9. The forming method according to claim 8, characterized in that, After forming the second gate stack layer, the process includes: A third barrier layer is formed covering the first gate stack layer and the second gate stack layer; A layer of metallic conductive material is formed covering the third barrier layer; The metal conductive material layer, the third barrier layer, the first gate stack layer, and the second gate stack layer are etched to form a first gate structure and a second gate structure.

10. The forming method according to claim 9, characterized in that, After the second gate stack layer is formed, and before etching the metal conductive material layer, the third barrier layer, the first gate stack layer, and the second gate stack layer, the method further includes: Annealing is performed on the first gate stack layer and the second gate stack layer.

Images