Heterojunction bipolar transistor and its manufacturing method

Abstract

This invention provides a heterojunction bipolar transistor and its manufacturing method. A first-conductivity InGaP emitter layer (layers 1 to m) is formed on a GaAs base layer of a second conductivity type. Each InGaP emitter layer contains In... y Ga 1‑y P, and y decreases layer by layer from the first InGaP emitter layer to the mth InGaP emitter layer, m≥3 and is an integer. This results in a gradual bandgap difference between the materials of the first to mth InGaP emitter layers and the P GaAs base layer, which effectively reduces the barrier peak at the InGaP / GaAs heterojunction, avoids the turn-on voltage Vbe from becoming high when the HBT is working, and improves the device performance.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device manufacturing technology, and in particular to a heterojunction bipolar transistor and its manufacturing method. Background Technology

[0002] A heterojunction bipolar transistor (HBT) is a transistor structure formed by replacing the homogeneous emitter junction of a bipolar junction transistor (BJT) with a heterojunction, based on the bipolar junction transistor (BJT). It has advantages such as high speed and low power consumption.

[0003] For example, a specific structure of an existing HBT is as follows: Figure 1 As shown, the structure includes, from bottom to top, a GaAs substrate layer 100, an nGaAs sub-collector layer 101, an nGaAs collector layer 102, a pGaAs base layer 103, an nInGaP emitter layer 104, an nGaAs contact layer 105, and an InGaAs contact layer 106. A base 108 is embedded in the nInGaP emitter layer 104, a collector 107 is formed on the nGaAs sub-collector layer 101, and an emitter 109 is formed on the InGaAs contact layer 106. The nInGaP emitter layer 104 forms a heterojunction with the pGaAs base layer 103 on one hand, and serves as a passivation layer during the formation of the base 108 on the other.

[0004] Please refer to Figure 2 The nInGaP emitter layer 104 typically uses In 0.5 Ga 0.5 This is achieved using P semiconductor materials, meaning that the proportion of In composition in the nInGaP emitter layer 104 remains constant regardless of the thickness.

[0005] Regarding the aforementioned npn-type HBT, please refer to... Figure 3 Because of the inherent bandgap difference between the nInGaP emitter layer 104 and the pGaAs base layer 103, a barrier spike exists at the InGaP / GaAs heterojunction, resulting in a higher turn-on voltage Vbe during HBT operation. On the other hand, the formation of the base 108 typically requires an annealing process, but due to the use of InGaP in the nInGaP emitter layer 104... 0.5 Ga 0.5 A p-type semiconductor material (Bulk InGaP) is formed, and the n-type impurity (e.g., Si) in the InGaP emitter layer is lightly doped (the Si doping concentration is approximately 2e17 / cm). 3), so it is easy to cause the contact annealing process between the base 108 and the n InGaP emitter layer 104 to be incomplete, resulting in the base 108 failing to contact the P GaAs base layer 103 through the n InGaP emitter layer 104. This leads to the inability to form a good ohmic contact between the base 108 and the P GaAs base layer 103, increasing the base series resistance and further raising the turn-on voltage Vbe when the HBT operates. SUMMARY OF THE INVENTION

[0006] The purpose of the present invention is to provide a heterojunction bipolar transistor (HBT) and its manufacturing method, which can reduce the barrier spike of the InGaP / GaAs heterojunction and lower the turn-on voltage Vbe when the HBT operates.

[0007] To achieve the above object, the present invention provides a heterojunction bipolar transistor, which includes, stacked in sequence from bottom to top:

[0008] A GaAs substrate layer;

[0009] A GaAs collector layer of the first conductivity type;

[0010] A GaAs base layer of the second conductivity type;

[0011] The first layer to the mth layer of InGaP emitter layers of the first conductivity type, each of the InGaP emitter layers contains In y Ga 1-y P, and the y value decreases layer by layer from the first layer to the mth layer of InGaP emitter layers, where m ≥ 3 and is an integer;

[0012] And, an InGaAs contact layer of the first conductivity type.

[0013] Optionally, for each of the InGaP emitter layers from the first layer to the m - 1th layer, 0.4 ≤ y ≤ 0.7, and for the mth layer of InGaP emitter layer, 0 < y < 0.4; or, for each of the InGaP emitter layers from the first layer to the m - 1th layer, 0.45 ≤ y ≤ 0.7, and for the mth layer of InGaP emitter layer, 0 < y < 0.45.

[0014] Optionally, for each of the InGaP emitter layers from the first layer to the m - 1th layer, the y value is constant; for the mth layer of InGaP emitter layer, the y value gradually decreases as the stacking thickness increases.

[0015] Optionally, the total stacking thickness from the first InGaP emitter layer to the (m-2)th InGaP emitter layer is 1 nm to 200 nm, the film thickness of the (m-1)th InGaP emitter layer is 1 nm to 100 nm, and the film thickness of the mth InGaP emitter layer is no more than 50 nm.

[0016] Optionally, the doping concentration of the impurity of the first conductivity type in the m-th InGaP emitter layer is 5e17 / cm³. 3 ~5e19 / cm 3 ; and / or, the doping concentration of impurities of the first conductivity type in at least one InGaP emitter layer from the first InGaP emitter layer to the (m-1)th InGaP emitter layer is 5e15 / cm. 3 ~5e18 / cm 3 .

[0017] Optionally, the ratio between the content of group V elements and the total content of group III elements in at least one InGaP emitter layer from the first InGaP emitter layer to the mth InGaP emitter layer is 0.5 to 100.

[0018] Optionally, the heterojunction bipolar transistor further includes: a GaAs sub-collector layer of a first conductivity type located between the GaAs substrate layer and the GaAs collector layer; and / or, a GaAs contact layer of a first conductivity type located between the InGaAs contact layer and the m-th InGaP emitter layer.

[0019] Optionally, the heterojunction bipolar transistor further includes:

[0020] The emitter is formed on the InGaAs contact layer and its bottom is in electrical contact with the InGaAs contact layer;

[0021] The collector electrode is formed on the GaAs sub-collector region layer and is electrically in contact with the GaAs sub-collector region layer at the bottom, while its top is exposed by the film layer above the GaAs sub-collector region layer.

[0022] The base extends from the bottom to the top through the first InGaP emitter layer to the m-th InGaP emitter layer, and the bottom of the base is in electrical contact with the GaAs base layer.

[0023] Based on the same inventive concept, the present invention also provides a method for manufacturing a heterojunction bipolar transistor as described in any one of claims 1-7, characterized in that it comprises:

[0024] Provide a GaAs substrate layer;

[0025] A GaAs collector region layer of a first conductivity type is formed on the GaAs substrate layer;

[0026] A GaAs base region layer of a second conductivity type is formed on the GaAs current collector region layer;

[0027] On the GaAs base layer, layers of InGaP emitter regions of the first conductivity type, from the first layer to the m-th layer, are sequentially stacked, each InGaP emitter region layer containing In. y Ga 1-y P, and y decreases layer by layer from the first InGaP emitter layer to the m-th InGaP emitter layer, where m≥3 and is an integer;

[0028] An InGaAs contact layer of the first conductivity type is formed on the m-th InGaP emitter region layer.

[0029] Optionally, the growth temperature of the first InGaP emitter layer to the (m-2)th InGaP emitter layer decreases layer by layer, or the growth temperature of at least two adjacent InGaP emitter layers is the same.

[0030] Optionally, the formation process conditions for at least one InGaP emitter layer from the first InGaP emitter layer to the m-th InGaP emitter layer include: a growth temperature of 400℃ to 800℃, a growth pressure of 50mbar to 200mbar, and a ratio between the content of group V elements and the total content of group III elements of 0.5 to 100.

[0031] Optionally, the manufacturing method further includes:

[0032] Before forming a GaAs collector region layer of the first conductivity type on the GaAs substrate, a GaAs sub-collector region layer of the first conductivity type is first formed on the GaAs substrate.

[0033] Before forming the InGaAs contact layer on the m-th InGaP emitter region layer, a GaAs contact layer of the first conductivity type is first formed on the m-th InGaP emitter region layer.

[0034] Optionally, an emitter, a collector, and a base are formed. The emitter is formed on the InGaAs contact layer and its bottom is in electrical contact with the InGaAs contact layer. The collector is formed on the GaAs sub-collector layer and its bottom is in electrical contact with the GaAs sub-collector layer. The top of the collector is exposed by a film layer above the GaAs sub-collector layer. The base penetrates from the bottom to the first InGaP emitter layer to the m-th InGaP emitter layer, and the bottom of the base is in electrical contact with the GaAs base layer.

[0035] The m-th InGaP emitter layer is removed by etching in at least a portion of the region between the emitter and the base.

[0036] Compared with the prior art, the technical solution of the present invention has at least one of the following beneficial effects:

[0037] 1. A first-conductivity InGaP emitter layer, from the first layer to the mth layer, is formed on a GaAs base layer of the second conductivity type. Each InGaP emitter layer contains In. y Ga 1-y P, and y decreases layer by layer from the first InGaP emitter layer to the mth InGaP emitter layer, m≥3 and is an integer. Thus, the potential barrier at the InGaP / GaAs interface gradually increases from low to high as y decreases layer by layer (i.e., the In composition with small jumps). The InGaP emitter layer from the first to the mth layer as a whole forms a gradual bandgap difference with the PGaAs base layer, thereby effectively reducing the barrier peak at the InGaP / GaAs heterojunction, avoiding the turn-on voltage Vbe from becoming high when the HBT is working, and improving the device performance.

[0038] 2. Since the bandgap of InGaP is related to the orderliness of the In and Ga arrangement, by controlling the growth temperature of the InGaP emitter layer to be different, the disorder of each InGaP emitter layer can be made to become more ordered, thereby reducing the bandgap and further avoiding the high turn-on voltage Vbe during HBT operation, thus improving device performance.

[0039] 3. The m-th InGaP emitter layer is highly n-type doped, which allows the emitter to form a better ohmic contact with InGaP, further reducing the turn-on voltage Vbe when the HBT is working. Moreover, the m-th InGaP emitter layer can be easily removed by etching in at least part of the region between the base and the emitter, thereby avoiding leakage between the base and the emitter and ensuring device performance. Attached Figure Description

[0040] Those skilled in the art will understand that the accompanying drawings are provided to better understand the invention and do not constitute any limitation on the scope of the invention. Wherein:

[0041] Figure 1 This is a schematic diagram of the cross-sectional structure of an existing heterojunction bipolar transistor (HBT).

[0042] Figure 2 yes Figure 1 The diagram shows a curve illustrating the change in the In component percentage in HBT as a function of thickness.

[0043] Figure 3 yes Figure 1 The diagram shows the barrier curve of the InGaP / GaAs heterojunction in the HBT.

[0044] Figure 4 This is a cross-sectional structural diagram of a heterojunction bipolar transistor (HBT) according to a specific embodiment of the present invention.

[0045] Figure 5 yes Figure 4 The diagram shows a cross-sectional structure of an example of a heterojunction bipolar transistor (HBT) (i.e., m=5).

[0046] Figure 6 yes Figure 5 The diagram shows a curve illustrating how y changes with depth THK from top to bottom in the HBT.

[0047] Figure 7 Is Figure 5 The diagram shows a cross-sectional structure of an HBT after further forming a base, emitter, and collector based on the example structure shown.

[0048] Figure 8 yes Figure 5 The diagram shows the barrier curve of the InGaP / GaAs heterojunction in the HBT.

[0049] Figure 9 yes Figure 4 A schematic cross-sectional view of another example of a heterojunction bipolar transistor (HBT) (i.e., m=3). Detailed Implementation

[0050] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of the invention. However, it will be apparent to those skilled in the art that the invention may be practiced without one or more of these details. In other instances, certain technical features well-known in the art have not been described to avoid confusion with the invention. It should be understood that the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout. It should be understood that when an element or layer is referred to as "on," it may be directly on other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," there are no intervening elements or layers. Although the terms first, second, etc., may be used to describe various elements, parts, regions, layers, and / or portions, these elements, parts, regions, layers, and / or portions should not be limited by these terms. These terms are used only to distinguish one element, component, area, layer, or part from another element, component, area, layer, or part. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or part discussed below may be referred to as the second element, component, area, layer, or part. Spatial relation terms such as “below,” “under,” “below,” “above,” “on top,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figures and other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then the element or feature described as “below,” “under,” or “below” will be oriented “on top” of other elements or features. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptions used herein will be interpreted accordingly. The terminology used herein is intended only to describe particular embodiments and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to identify the presence of features, steps, operations, elements, and / or components, but does not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or groups. When used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0051] The technical solution proposed by the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0052] Please refer to Figure 4 An embodiment of the present invention also provides a heterojunction bipolar transistor, taking an n-type first conductivity type and a p-type second conductivity type as an example, which includes GaAs substrate layer 100, n GaAs sub-collector layer 101, n GaAs collector layer 102, p GaAs base layer 103, n-type first InGaP emitter layer to m-th InGaP emitter layer 1041 to 104m, nGaAs contact layer 105, and n InGaAs contact layer 106, stacked sequentially from bottom to top.

[0053] The p-GaAs base layer 103 is used to form the base region of the npn-type HBT transistor. It can be highly doped with p-type impurities such as C (carbon), with a doping concentration of, for example, 5e17–5e19 / cm³. 3 This provides a high hole concentration and reduces the resistance of the base region. The thickness of the pGaAs base layer 103 can be small, for example, controlled to be less than 100 nm (e.g., within 50 nm), which can reduce the recombination effect of electrons in the base region, reduce the electron transit time, and improve device gain and frequency.

[0054] The nGaAs sub-collector layer 101 and nGaAs collector layer 102 can use GaAs material identical to that of the GaAs substrate layer 100, or they can use other semiconductors, such as GaAs, AlGaAs, or stacked structures of these semiconductors, that do not exhibit lattice mismatch with the GaAs substrate layer 100. The nGaAs sub-collector layer 101 serves as the contact layer for the collector electrode of an npn-type HBT transistor. The n-type impurities doped in this layer can include Si, with a doping concentration, for example, 5e15 / cm³. 3 ~5e18 / cm 3 High n-type doping facilitates good ohmic contact and reduces series resistance. The n GaAs collector layer 102 is used to form the collector region of the npn-type HBT transistor. Its function is to collect electrons from the emitter region. An electric field exists inside, which accelerates the electrons and reduces capacitance.

[0055] The first InGaP emitter layer to the m-th InGaP emitter layer 1041 to 104m together constitute the emitter layer 104 of the npn-type HBT transistor, which is used to form the emitter region of the npn-type HBT transistor and is used to emit electrons.

[0056] In this embodiment, each of the InGaP emitter layers 1041 to 104m contains In y Ga1- y P, and y decreases layer by layer from the first InGaP emitter layer to the mth InGaP emitter layer 1041 to 104m, where m≥3 and is an integer. Specifically, the In y Ga1- y P of the first InGaP emitter layer to the mth InGaP emitter layer 1041 to 104m are denoted as In y1 Ga1- y1 P, In y2 Ga1- y2 P, ……, In ym Ga1- ym P respectively. At this time, 0.7≥y1>>y2……>ym-1≥0.4 and 0<ym<0.4, or 0.7≥y1>>y2……>ym-1≥0.45 and 0<ym<0.45.

[0057] Optionally, from the first InGaP emitter layer to the m-1th InGaP emitter layer 1041 to 104m-1, y of each InGaP emitter layer is constant respectively, that is, y1 to ym-1 are different constant values. ym of the mth InGaP emitter layer 104m gradually decreases as the thickness of the film stack increases from bottom to top. The advantage of doing this is that the potential barrier at the interface between the InGaP emitter layer 104 and the p GaAs base layer 103 is gradually changed through the y value with a small jump and gradually decreasing from bottom to top, effectively reducing the potential barrier peak at the InGaP / GaAs heterojunction.

[0058] It should be understood that the thickness of each emitter layer from the first InGaP emitter layer to the mth InGaP emitter layer 1041 to 104m also has a certain design. If the overall thickness of the InGaP emitter layer 104 is too thick, the formed base 108 cannot effectively penetrate the InGaP emitter layer 104 serving as a passivation layer after annealing, resulting in poor ohmic contact and an increase in Vbe. If the overall thickness of the InGaP emitter layer 104 is too thin, the reverse breakdown voltage Bvebo between the emitter and the base will decrease, affecting the device performance. Therefore, further optionally, the total stack thickness sum X1+X2+……Xm-2 of the first InGaP emitter layer to the m-2th InGaP emitter layer 1041 to 104m-2 is 1nm to 200nm, the film thickness Xm-1 of the m-1th InGaP emitter layer 104m-1 is 1nm to 100nm, and the film thickness Xm of the mth InGaP emitter layer 104m is not higher than 50nm.

[0059] Furthermore, the n-type impurities in the 10⁴m InGaP emitter layer can be highly doped, for example, with a doping concentration of 5e¹⁷ / cm². 3 ~5e19 / cm 3 This facilitates a good ohmic contact at the base 108 and reduces series resistance. The doping concentration of n-type impurities in at least one of the InGaP emitter layers from the first InGaP emitter layer to the (m-1)th InGaP emitter layer (1041~104m-1) is 5e15 / cm². 3 ~5e18 / cm 3 This is to control the lattice defects generated and ensure device performance.

[0060] The n-type impurities in the n GaAs contact layer 105 can be highly doped. High n-type doping is beneficial for achieving good ohmic contact of the emitter and reducing series resistance.

[0061] The n-type InGaAs contact layer 106 serves as the contact layer for the emitter 109 on the surface. Its n-type impurities can be highly doped, which is beneficial for achieving good ohmic contact and reducing series resistance, and can also reduce the surface recombination effect of electrons.

[0062] Optionally, the ratio V / III between the proportion of group V elements (P) and the total proportion of group III elements (In+Ga) in at least one InGaP emitter layer from the first InGaP emitter layer 1041 to the m-th InGaP emitter layer 104m is 0.5 to 100.

[0063] Please refer to Figure 5 Taking m=5 as an example, the npn type HBT transistor includes, from bottom to top, a GaAs substrate layer 100, an n GaAs sub-collector layer 101, an n GaAs collector layer 102, a p GaAs base layer 103, an n-type first InGaP emitter layer 1041, an n-type second InGaP emitter layer 1042, an n-type third InGaP emitter layer 1043, an n-type fourth InGaP emitter layer 1044, an n-type fifth InGaP emitter layer 1045, an n GaAs contact layer 105, and an n InGaAs contact layer 106.

[0064] The first InGaP emitter layer 1041 has a thickness of X1 and contains In. y1 Ga1- y1 P, the second InGaP emitter layer 1042 has a thickness of X2 and contains In y2 Ga1- y2 P, the third InGaP emitter layer 1043 has a thickness of X3 and contains In y3Ga1- y3 P, the fourth InGaP emitter layer 1044 has a thickness of X4 and contains In y4 Ga1- y4 P, the 5th InGaP emitter layer 1045 has a thickness of X5 and contains In y5 Ga1- y5 P.

[0065] Furthermore, along the direction where the film stacking depth THK gradually increases from top to bottom, the curve showing the change in y-value from the nGaAs contact layer 105 to the pGaAs base layer 103 is as follows: Figure 6 THK1 represents the stacking depth from the top surface of nInGaAs contact layer 106 to the bottom surface of nGaAs contact layer 105, X5 = THK2 - THK1, X4 = THK3 - THK2, X3 = THK4 - THK3, X2 = THK5 - THK4, X1 = THK6 - THK5. From Figure 6 As can be seen, y1 in the first InGaP emitter layer 1041 is a constant, not changing with the top-down stacking depth THK or the bottom-up stacking height. y2 in the second InGaP emitter layer 1042 is a constant less than y1, also not changing with the top-down stacking depth THK or the bottom-up stacking height. y3 in the third InGaP emitter layer 1043 is a constant less than y2, also not changing with the top-down stacking depth THK or the bottom-up stacking height. y4 in the fourth InGaP emitter layer 1044 is a constant less than y3, also not changing with the top-down stacking depth THK or the bottom-up stacking height. y5 in the fifth InGaP emitter layer 1045 is a variable, decreasing with decreasing top-down stacking depth THK or increasing bottom-up stacking height.

[0066] Where X1+X2+X3=1nm~200nm, 1nm <X4<100nm,0<X5<50nm。0.7≥y1> y2>y3>y4≥0.4, 0 <y5<0.4。

[0067] In other words, along the direction from the 5th InGaP emitter layer 1045 to the 1st InGaP emitter layer 1041, the y-value increases layer by layer, and the larger the y-value, the smaller the band gap. This allows the barrier of the heterojunction formed by the InGaP emitter layer 104 and the pGaAs base layer 103 to gradually change. (Comparison) Figure 3 and Figure 8, it can be found that the technical solution of this embodiment can reduce the barrier peak at the heterojunction formed by the entire InGaP emitter layer 104 and the p GaAs base layer 103, avoid the increase of the turn-on voltage Vbe during the operation of the HBT, and improve the device performance.

[0068] Please refer to Figure 7 , further, in order to lead out the base region, emitter region, and collector region of the heterojunction bipolar transistor or access electrical signals such as voltages, the heterojunction bipolar transistor further includes a collector 107, a base 108, and an emitter 109. Among them, the emitter 109 is formed on the top surface of the n InGaAs contact layer 106 and is electrically contacted with the top surface of the n InGaAs contact layer 106 at the bottom (for example, an ohmic contact). The collector 107 is formed on the top surface of the n GaAs sub-collector layer 101, the bottom of the collector 107 is electrically contacted with the top surface of the n GaAs sub-collector layer 101 (for example, an ohmic contact), and the top of the collector 107 is exposed by the film layer above the n GaAs sub-collector layer 101 (that is, from the n GaAs collector layer 102 to the nInGaAs contact layer 109). The base 108 sequentially penetrates from the bottom up through the first layer InGaP emitter layer 1041 to the mth layer InGaP emitter layer 104m, and the bottom of the base 108 is electrically contacted with the p GaAs base layer 103 (for example, an ohmic contact). The top of the base 108 is exposed by the n InGaAs contact layer 106 and the n GaAs contact layer 105.

[0069] It should be understood that the above example uses m = 5 to illustrate the structure of the heterojunction bipolar transistor of the present invention, but the technical solution of the present invention is not limited thereto. In other examples of the present invention, m can also be equal to 3, as Figure 9 shown. At this time, y1 and y2 are different constant constants, y3 is a variable that gradually increases with the increase of the stacking depth from top to bottom, and 0.7≥y1>y2≥0.4, 0<y3<0.4. In other examples of the present invention, m can also be 4 or any suitable integer greater than 5, and the larger m is, the smoother the barrier transition of the heterojunction formed by the InGaP emitter layer 104 and the GaAs base layer 103 is, and the better the improvement effect of the barrier peak is.

[0070] Based on the same inventive concept, please refer to Figures 4 to 7 , an embodiment of the present invention also provides a manufacturing method for a heterojunction bipolar transistor, which can manufacture the heterojunction bipolar transistor of the present invention. The manufacturing method includes:

[0071] S1, providing a GaAs substrate layer 00;

[0072] S2, a GaAs collector region layer 102 of the first conductivity type is formed on the GaAs substrate layer 100;

[0073] S3, a GaAs base layer 103 of the second conductivity type is formed on the GaAs current collector layer 102;

[0074] S4, on the GaAs base layer 103, the first InGaP emitter layer of the first conductivity type to the m-th InGaP emitter layer 1041 to 104m are stacked sequentially. Each InGaP emitter layer contains InyGa1-yP, and the y value decreases layer by layer from the first InGaP emitter layer to the m-th InGaP emitter layer, where m ≥ 3 and is an integer, i.e., y1 > y2 > y3 > ... > ym;

[0075] S5, an InGaAs contact layer 106 of the first conductivity type is formed on the m-th InGaP emitter layer 104m.

[0076] In step S2, the first InGaP emitter layer to the m-th InGaP emitter layer 1041 to 104m are grown sequentially, and the process parameters for growing each InGaP emitter layer include: growth temperature of 400℃ to 800℃, growth pressure of 50mbar to 200mbar, and element content ratio of V / III of 0.5 to 100.

[0077] Since the band gap of InGaP material is related to the orderliness of In and Ga arrangement, the band gap decreases when InGaP becomes more ordered from disordered to ordered. The growth temperature can change the orderliness of InGaP material. Therefore, in step S3, when growing the first InGaP emitter layer to the m-th InGaP emitter layer 1041~104m in sequence, controlling the growth temperature can control the gradual change of the band gap of each InGaP emitter layer.

[0078] As an example, in step S3, when growing the first InGaP emitter layer to the m-th InGaP emitter layer 1041~104m in sequence, the growth temperature can be controlled to decrease layer by layer. That is, when the growth temperatures of the first InGaP emitter layer to the m-th InGaP emitter layer 1041~104m are T1, T2, ... Tm in sequence, T1>T2>T3>...>Tm is satisfied.

[0079] As an example, in step S3, when growing the first InGaP emitter layer to the m-th InGaP emitter layer 1041~104m sequentially, the growth temperature from the first InGaP emitter layer to the (m-2)-th InGaP emitter layer 1041~104m-2 can be controlled to decrease sequentially, satisfying T1>T2>T3>…>Tm-2. The growth temperature from the (m-2)-th InGaP emitter layer 104m-2 to the m-th InGaP emitter layer 104m decreases layer by layer, or at least the growth temperature of adjacent InGaP emitter layers is the same. For example, when m=5, if the growth temperatures of the first InGaP emitter layer to the fifth InGaP emitter layer 1041~1045 are T1, T2, T3, T3, T5 respectively, then T1>T2>T3≥T4≥T5 is satisfied.

[0080] Optionally, the formation process conditions for at least one InGaP emitter layer from the first InGaP emitter layer to the m-th InGaP emitter layer include: a growth temperature of 400℃ to 800℃, a growth pressure of 50mbar to 200mbar, and a ratio between the content of group V elements and the total content of group III elements of 0.5 to 100.

[0081] Optionally, the manufacturing method of this embodiment further includes:

[0082] After step S1 and before step S2, that is, before forming the GaAs collector region layer 102 of the first conductivity type on the GaAs substrate layer 100, the GaAs sub-collector region layer 101 of the first conductivity type is first formed on the GaAs substrate layer 100.

[0083] And, after step S4 and before step S5, that is, before forming the InGaAs contact layer 106 on the m-th InGaP emitter layer 104m, a GaAs contact layer 105 of the first conductivity type is first formed on the m-th InGaP emitter layer 104m.

[0084] Furthermore, the manufacturing method of this embodiment, after step S5, further includes:

[0085] First, an emitter 109, a collector 107, and a base 108 are formed. The emitter 109 is formed on the InGaAs contact layer 106 and its bottom is electrically in contact with the InGaAs contact layer 106. The collector 107 is formed on the GaAs sub-collector layer 101 and its bottom is electrically in contact with the GaAs sub-collector layer 101. The top of the collector 107 is exposed by a film layer above the GaAs sub-collector layer 101. The base 108 penetrates from the first InGaP emitter layer 1041 to the m-th InGaP emitter layer 104m from bottom to top, and the bottom of the base 108 is electrically in contact with the GaAs base layer 103.

[0086] Then, the m-th InGaP emitter layer 104m is etched away in at least a portion of the region between the emitter 109 and the base 108 to avoid leakage between the two electrodes 109 and 108.

[0087] In summary, the technical solution of this invention replaces the InGaP emitter layer in the bulk block of the prior art with InGaP emitter layers from the 1st to the mth layer, where the gradient decreases with each subsequent layer. This creates a gradual bandgap difference between the 1st to mth InGaP emitter layers and the P-GaAs base layer, effectively reducing the barrier spike at the InGaP / GaAs heterojunction and lowering the turn-on voltage Vbe during HBT operation. Furthermore, by controlling the growth temperature of each InGaP emitter layer, the disordered InGaP emitter layers become more ordered, further reducing the bandgap and further lowering the turn-on voltage Vbe during HBT operation.

[0088] The above description is only a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the present invention.

Claims

1. A heterojunction bipolar transistor, characterized in that, Comprising, stacked from bottom to top: GaAs substrate layer; GaAs collector region layer of the first conduction type; GaAs base region layer of the second conduction type; the first layer to the mth layer of InGaP emitter region layers each containing In y Ga 1-y P, and y decreases from the first layer to the mth layer of InGaP emitter region layers, m is an integer greater than or equal to 3; And, InGaAs contact layer of the first conduction type; Wherein, the growth temperature of the first layer of InGaP emitter region layer to the m-2th layer of InGaP emitter region layer decreases layer by layer, and the growth temperature from the m-2th layer of InGaP emitter region layer to the mth layer of InGaP emitter region layer decreases layer by layer or at least the growth temperatures of adjacent two layers of InGaP emitter region layers are the same.

2. The heterojunction bipolar transistor as described in claim 1, characterized in that, For each layer of InGaP emitter region layer from the first layer of InGaP emitter region layer to the m-1th layer of InGaP emitter region layer, 0.4 ≤ y ≤ 0.7, and for the mth layer of InGaP emitter region layer, 0 < y < 0.4; or, for each layer of InGaP emitter region layer from the first layer of InGaP emitter region layer to the m-1th layer of InGaP emitter region layer, 0.45 ≤ y ≤ 0.7, and for the mth layer of InGaP emitter region layer, 0 < y < 0.

45.

3. The heterojunction bipolar transistor as described in claim 1, characterized in that, From the first layer of InGaP emitter region layer to the m-1th layer of InGaP emitter region layer, the y of each layer of InGaP emitter region layer is constant respectively; the y of the mth layer of InGaP emitter region layer gradually decreases as the stacking thickness increases.

4. The heterojunction bipolar transistor as described in claim 1, characterized in that, The total stacking thickness of the first layer of InGaP emitter region layer to the m-2th layer of InGaP emitter region layer is 1 nm to 200 nm, the film thickness of the m-1th layer of InGaP emitter region layer is 1 nm to 100 nm, and the film thickness of the mth layer of InGaP emitter region layer is not higher than 50 nm.

5. The heterojunction bipolar transistor as described in claim 1, characterized in that, the doping concentration of the impurity of the first conductivity type in the mth InGaP emitter layer is 5e17 / cm3 3 ~5e19 / cm3 3 ; and / or the doping concentration of the impurity of the first conductivity type in at least one of the first to the m-1th InGaP emitter layers is 5e15 / cm3 3 ~5e18 / cm3 3 .

6. The heterojunction bipolar transistor as described in claim 1, characterized in that, The ratio between the total content of group V elements and the total content of group III elements in at least one layer of InGaP emitter region layer from the first layer of InGaP emitter region layer to the mth layer of InGaP emitter region layer is 0.5 to 100.

7. The heterojunction bipolar transistor according to any one of claims 1-6, characterized in that, Further comprising: GaAs sub-collector region layer of the first conduction type located between the GaAs substrate layer and the GaAs collector region layer; And / or, GaAs contact layer of the first conduction type located between the InGaAs contact layer and the mth layer of InGaP emitter region layer.

8. The heterojunction bipolar transistor as described in claim 7, characterized in that, Further comprising: Emitter, formed on the InGaAs contact layer and in electrical contact with the InGaAs contact layer at the bottom; Collector, formed on the GaAs sub-collector region layer and in electrical contact with the GaAs sub-collector region layer at the bottom, and the top is exposed by the film layer above the GaAs sub-collector region layer; Base, penetrating through the first layer of InGaP emitter region layer to the mth layer of InGaP emitter region layer from bottom to top, and the bottom of the base is in electrical contact with the GaAs base region layer.

9. A method for manufacturing a heterojunction bipolar transistor, characterized in that, Comprising: Providing a GaAs substrate layer; Forming a GaAs collector region layer of the first conduction type on the GaAs substrate layer; Forming a GaAs base region layer of the second conduction type on the GaAs collector region layer; On said GaAs base region layer, a first conductive type first layer InGaP emitting region layer to mth layer InGaP emitting region layer are sequentially stacked, each of said InGaP emitting region layers contains In y Ga 1-y P, and y decreases from the first layer InGaP emitting region layer to the mth layer InGaP emitting region layer, m≥3 and is an integer; Forming an InGaAs contact layer of the first conduction type on the mth layer of InGaP emitter region layer; The growth temperature of the first InGaP emitter layer to the (m-2)th InGaP emitter layer decreases layer by layer, and the growth temperature of the (m-2)th InGaP emitter layer to the mth InGaP emitter layer decreases layer by layer, or at least the growth temperature of two adjacent InGaP emitter layers is the same.

10. The manufacturing method as described in claim 9, characterized in that, The formation process conditions for at least one InGaP emitter layer from the first InGaP emitter layer to the m-th InGaP emitter layer include: a growth temperature of 400℃ to 800℃, a growth pressure of 50mbar to 200mbar, and a ratio between the content of group V elements and the total content of group III elements of 0.5 to 100.

11. The manufacturing method as described in claim 9, characterized in that, Also includes: Before forming a GaAs collector region layer of the first conductivity type on the GaAs substrate layer, a GaAs sub-collector region layer of the first conductivity type is first formed on the GaAs substrate layer. Before forming the InGaAs contact layer on the m-th InGaP emitter region layer, a GaAs contact layer of the first conductivity type is first formed on the m-th InGaP emitter region layer.

12. The manufacturing method as described in claim 11, characterized in that, Also includes: An emitter, a collector, and a base are formed. The emitter is formed on the InGaAs contact layer and its bottom is in electrical contact with the InGaAs contact layer. The collector is formed on the GaAs sub-collector layer and its bottom is in electrical contact with the GaAs sub-collector layer. The top of the collector is exposed by a film layer above the GaAs sub-collector layer. The base penetrates from the bottom to the first InGaP emitter layer to the m-th InGaP emitter layer, and its bottom is in electrical contact with the GaAs base layer. The m-th InGaP emitter layer is etched away from at least a portion of the region between the emitter and the base.

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