Semiconductor element and method for manufacturing the same

Abstract

The present invention relates to a semiconductor device comprising a two-dimensional semiconductor layer, a two-dimensional metal conductor layer, and a metal layer. The two-dimensional semiconductor layer is formed from a two-dimensional semiconductor material having a first heat of formation energy. The two-dimensional metal conductor layer is formed from a two-dimensional metal material and covers the surface of the two-dimensional semiconductor layer. The two-dimensional metal material has a second heat of formation energy that is less than the first heat of formation energy. The metal layer covers the surface of the two-dimensional metal conductor layer. The two-dimensional metal conductor layer is formed by bonding cations in the metal layer with anions in the two-dimensional semiconductor layer. This effectively reduces the contact resistance between the two-dimensional material and the metal, enabling the successful application of the two-dimensional material in semiconductor devices such as field-effect transistors.

Description

Technical Field

[0001] The present invention relates to semiconductor components, and in particular to a semiconductor component using two-dimensional materials and a method for manufacturing the same. Background Art

[0002] Two-dimensional materials are materials whose crystal structures consist of a single layer of molecules in the vertical direction, like a piece of paper. For example, consider molybdenum disulfide (MoS2). Viewed from the side, the molybdenum atom is centered, with a sulfur atom above and below, resulting in a single layer thickness of approximately 0.7 nanometers. Viewed from above, these repeating MoS2 molecules form a hexagonal honeycomb structure. MoS2 is the first material considered for sub-5nm semiconductor processes, used as the transistor channel. Its primary benefit is that its leakage current is orders of magnitude lower than silicon, resulting in minimal power consumption. This is primarily due to MoS2's electron-equivalent mass being approximately three times greater than silicon's. Experiments have demonstrated its excellent properties in field-effect transistors, making it a promising candidate for replacing silicon as the primary semiconductor channel material for sub-2nm node technologies.

[0003] However, due to the lack of dangling bonds on the surface of two-dimensional materials, covalent bonding with metals is difficult to achieve. Furthermore, the large van der Waals gap at the interface makes it difficult to lower the Schottky barrier. Furthermore, high contact resistance with metals, coupled with the susceptibility to Fermi level pinning at the metal / two-dimensional semiconductor interface, remains a significant obstacle to the application of two-dimensional materials in field-effect transistors.

[0004] To achieve ohmic contact between two-dimensional materials and metals, hydrogen (H2) or helium (He) plasma is currently used to treat the surface of two-dimensional materials such as WSe2, which can form selenium vacancy on the surface and increase the surface carrier concentration (N) at room temperature. D )>4×10 17 cm –3 The high-carrier-concentration WSe2 surface in contact with metal can lower the Schottky barrier, thereby reducing contact resistance. However, this approach damages the WSe2 surface, making it susceptible to oxidation by ambient oxygen and making process stability difficult to control.

[0005] In addition, some people have used two-dimensional materials with metallic properties, such as graphene, to insert them between Ag and MoS2, showing good electrical properties. The Schott barrier (SBH) has been significantly reduced from 300meV to 190meV, and the current switching ratio has been increased to 4×10 8However, the current mature graphene production process mainly requires high-temperature growth on copper foil and then transfer to the device using a peel-and-stick method, which is not easily compatible with semiconductor CMOS processes.

[0006] Therefore, how to create ohmic contact between two-dimensional materials and metals in a stable and feasible way so that two-dimensional materials can be successfully applied to semiconductor components such as field-effect transistors has become an urgent issue that needs to be solved in the industry. Summary of the Invention

[0007] One object of the present invention is to provide a semiconductor element that can effectively reduce the contact resistance between two-dimensional materials and metals, so that two-dimensional materials can be successfully applied to semiconductor elements such as field-effect transistors; another object of the present invention is to provide a method for manufacturing a semiconductor element that can reduce the contact resistance between two-dimensional materials and metals and avoid oxidation during the manufacturing process.

[0008] To achieve the above objectives, the semiconductor device of the present invention includes a two-dimensional semiconductor layer, a two-dimensional metal conductor layer, and a metal layer. The two-dimensional semiconductor layer is formed of a two-dimensional semiconductor material having a first heat of formation; the two-dimensional metal conductor layer is formed of a two-dimensional metal material and covers the surface of the two-dimensional semiconductor layer, the two-dimensional metal material having a second heat of formation that is less than the first heat of formation; and the metal layer covers the surface of the two-dimensional metal conductor layer. The two-dimensional metal conductor layer is formed by bonding cations in the metal layer with anions in the two-dimensional semiconductor layer. This effectively reduces the contact resistance between the two-dimensional material and the metal, enabling the successful application of the two-dimensional material in semiconductor devices such as field-effect transistors.

[0009] To achieve the above objectives, the present invention provides a method for fabricating a semiconductor device, comprising the following steps: (A) forming a metal layer on a two-dimensional semiconductor layer; and (B) annealing the layer at 600-1000°C in a controlled atmosphere to allow metal cations in the metal layer to bond with anions in the two-dimensional semiconductor layer, thereby forming a two-dimensional metal conductor layer. This reduces the contact resistance between the two-dimensional material and the metal, and prevents oxidation during the fabrication process. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A schematic diagram of a partial manufacturing process of a semiconductor device according to a preferred embodiment of the present invention;

[0011] Figure 2 A schematic diagram of a semiconductor device applied to a field effect transistor according to a preferred embodiment of the present invention;

[0012] Figure 3 A perspective view of a semiconductor device according to a preferred embodiment of the present invention applied to a gate-around field-effect transistor;

[0013] Figure 4 for Figure 3 Cross-sectional view along AA direction;

[0014] Figure 5 FIG2 is a cross-sectional view of a semiconductor device according to a preferred embodiment of the present invention applied to another gate-around field-effect transistor.

[0015]

Explanation of symbols

[0016] 1. Semiconductor components

[0017] 10 substrate

[0018] 12 Two-dimensional semiconductor layers

[0019] 14 Two-dimensional metal conductor layer

[0020] 16 Metal Layers

[0021] 2 Field-effect transistors

[0022] 20 substrate

[0023] 21 channel layer

[0024] 22 Source

[0025] 23 Drain

[0026] 24 dielectric layer

[0027] 25 Gate

[0028] 26 Source pad

[0029] 27 Drain pad

[0030] 3,4 Gate-Wrap-Around Field Effect Transistor

[0031] 30 substrate

[0032] 31,41 channel layer

[0033] 32,42 source

[0034] 33,43 Drain

[0035] 34 dielectric layer

[0036] 35 Gate

[0037] 36 Insulation layer DETAILED DESCRIPTION

[0038] The following describes the technical content and features of the present invention in detail through a preferred embodiment with accompanying drawings. Figure 1As shown, a partial process of the semiconductor element 1 provided by a preferred embodiment of the present invention includes the following steps: (A) forming a two-dimensional semiconductor layer 12 on a substrate 10 by chemical vapor deposition (CVD), molecular beam epitaxy, or laser epitaxy, and then forming a metal layer 16 on the two-dimensional semiconductor layer 12 by sputtering, electron gun evaporation, or thermal evaporation; and (B) annealing at 600-1000°C in a controlled atmosphere to allow the cations in the metal layer 16 to bond with the anions in the two-dimensional semiconductor layer 12, thereby forming a two-dimensional metal conductor layer 14 between the metal layer 16 and the two-dimensional semiconductor layer 12.

[0039] The substrate 10 is made of a three-dimensional material such as silicon (Si). In other embodiments, the substrate 10 may be made of sapphire, quartz, silicon carbide (SiC), aluminum nitride (AlN), gallium nitride (GaN), silicon grown on silicon dioxide (SiO2 / Si), silicon grown on silicon nitride (SiN x / Si) or other amorphous insulating materials, or two-dimensional materials such as mica.

[0040] The two-dimensional semiconductor layer 12 is formed of a two-dimensional semiconductor material such as molybdenum disulfide (MoS2), which has semiconductor properties. The two-dimensional semiconductor material has a first formation energy. In this embodiment, the formation energy of molybdenum disulfide is -1.059 eV / atom. The larger the negative value of the formation energy (i.e., the smaller the value), the more stable the synthetic reactants are and the easier they are to form.

[0041] The metal layer 16 is niobium (Nb), and the controlled atmosphere contains 85 vol% nitrogen and 15 vol% hydrogen. During annealing, since the formation heat of niobium disulfide (NbS2) -1.207 eV / atom is smaller than the formation heat of molybdenum disulfide -1.059 eV / atom, the Nb in the metal layer 12 is + Can be combined with S in the two-dimensional semiconductor layer 12 (i.e., molybdenum disulfide) - A bond is formed, forming a niobium disulfide layer between the metal layer 16 and the two-dimensional semiconductor layer 12. Because niobium disulfide is a two-dimensional metal material with metallic conductor properties, this niobium disulfide layer is referred to as the two-dimensional metallic conductor layer 14. Structurally, it covers the surface of the two-dimensional semiconductor layer 12. This two-dimensional metal material has a second heat of formation that is lower than the first heat of formation. Once the two-dimensional metallic conductor layer 14 is formed, the metal layer 16 structurally covers the surface of the two-dimensional metallic conductor layer 14. The two-dimensional metallic conductor layer 14 is formed by bonding cations in the metal layer 16 with anions in the two-dimensional semiconductor layer 14.

[0042] Because the sulfur atoms in the molybdenum disulfide of the two-dimensional semiconductor layer 12 are robbed by niobium, a surface sulfur deficiency (Svacancy) phenomenon occurs. This can increase the surface carrier concentration without damaging the surface or even causing oxidation. Niobium disulfide, which has metallic conductor properties, plays the role of graphene in conventional technology, which can significantly reduce the Schott barrier between the metal layer 16 and the two-dimensional semiconductor layer 12. The process of the present invention is also compatible with semiconductor CMOS processes. Therefore, the manufacturing method provided by the present invention can successfully achieve ohmic contact between the two-dimensional material and the metal, reducing the contact resistance between the two-dimensional material and the metal, allowing the two-dimensional material to be successfully applied to semiconductor devices such as field-effect transistors, thereby achieving the purpose of the present invention.

[0043] It should be noted that the controlled atmosphere in step (B) contains nitrogen and hydrogen, and the ratio of nitrogen to hydrogen can be varied between 80:20 and 90:10 as needed. The annealing temperature can also be adjusted as needed.

[0044] In addition to the aforementioned embodiments, there are other applicable two-dimensional semiconductor materials and two-dimensional metal materials, as long as they meet the aforementioned condition that the second heat of formation is less than the first heat of formation. Table 1 shows the first heat of formation values ​​of various two-dimensional semiconductor materials (with semiconductor properties), and Table 2 shows the second heat of formation values ​​of various two-dimensional metal materials (with metal conductor properties).

[0045] Table 1

[0046]

[0047] Table 2

[0048]

[0049]

[0050] Since the heat of formation in Table 1 and Table 2 are values ​​obtained under the same equipment and the same parameters, their relative sizes are of reference value. Pairing is carried out based on them. After actual experiments, for sulfides, the combination of the two-dimensional semiconductor material / the two-dimensional metal material can be molybdenum disulfide (MoS2) / niobium disulfide (NbS2), tungsten disulfide (WS2) / niobium disulfide (NbS2), vanadium disulfide (VS2) / niobium disulfide (NbS2), nickel disulfide (NiS2) / niobium disulfide (NbS2), palladium disulfide (PdS2) / niobium disulfide (NbS2), platinum disulfide (PtS2) / niobium disulfide (NbS2), molybdenum disulfide (MoS2) / tantalum disulfide (TaS2), tungsten disulfide (WS2) / tantalum disulfide (TaS2), Vanadium disulfide (VS2) / tantalum disulfide (TaS2), nickel disulfide (NiS2) / tantalum disulfide (TaS2), palladium disulfide (PdS2) / tantalum disulfide (TaS2), platinum disulfide (PtS2) / tantalum disulfide (TaS2), tungsten disulfide (WS2) / vanadium disulfide (VS2), nickel disulfide (NiS2) / vanadium disulfide (VS2), palladium disulfide (PdS2) / vanadium disulfide (VS2), platinum disulfide (PtS2) / vanadium disulfide (VS2), nickel disulfide (NiS2) / ferrous disulfide (FeS2), palladium disulfide (PdS2) / ferrous disulfide (FeS2), or platinum disulfide (PtS2) / ferrous disulfide (FeS2). Conversely, the metal layer 16 can be made of niobium, tantalum, vanadium or iron.

[0051] For selenides, the combination of the two-dimensional semiconductor material / the two-dimensional metal material can be molybdenum diselenide (MoSe2) / niobium diselenide (NbSe2), tungsten diselenide (WSe2) / niobium diselenide (NbSe2), palladium diselenide (PdSe2) / niobium diselenide (NbSe2), platinum diselenide (PtSe2) / niobium diselenide (NbSe2), molybdenum diselenide (MoSe2) / tantalum diselenide (TaSe2), tungsten diselenide (WSe2) / tantalum diselenide (TaSe2), palladium diselenide (PdSe2) / tantalum diselenide (TaSe2), platinum diselenide (PtSe2) / tantalum diselenide ( The metal layer 16 may be made of niobium, tantalum, vanadium or titanium.

[0052] For tellurides, the combination of the two-dimensional semiconductor material / the two-dimensional metal material can be molybdenum ditelluride (MoTe2) / niobium ditelluride (NbTe2), molybdenum ditelluride (MoTe2) / titanium ditelluride (TiTe2), molybdenum ditelluride (MoTe2) / hafnium ditelluride (HfTe2), or molybdenum ditelluride (MoTe2) / zirconium ditelluride (ZrTe2). Conversely, the metal layer 16 can be made of niobium, titanium, hafnium, or zirconium. However, the two-dimensional semiconductor materials / two-dimensional metal materials that can be used are not limited to the examples listed above.

[0053] The semiconductor device of the present invention can be applied to field effect transistors, gate-around field effect transistors or other devices. Figure 2 As shown, it is a schematic diagram of the semiconductor element of the present invention applied to a field effect transistor 2, wherein the field effect transistor 2 has a substrate 20, a channel layer 21, a source 22, a drain 23, a dielectric layer 24, a gate 25, a source pad 26 and a drain pad 27, wherein the two-dimensional semiconductor layer 12 serves as the channel layer 21, and the metal layer 16 serves as the source 22 and the drain 23. Thus, due to the presence of the two-dimensional metal conductor layer 14, the channel layer 21 made of two-dimensional semiconductor material and the source 22 and the drain 23 made of metal material have good ohmic contact, which effectively reduces the contact resistance between the two-dimensional material and the metal in the known technology, so that the two-dimensional material can be successfully applied to semiconductor elements such as field effect transistors.

[0054] again Figures 3-4 FIG2 is a schematic diagram of a semiconductor element of the present invention applied to a gate-wrap field-effect transistor 3. The gate-wrap field-effect transistor 3 has a substrate 30, three channel layers 31, a source 32, a drain 33, a dielectric layer 34, a gate 35, and three insulating layers 36. The two-dimensional semiconductor layer 12 serves as the channel layer 31, and the metal layer 16 serves as the source 32 and the drain 33. Thus, due to the presence of the two-dimensional metal conductor layer 14, the channel layer 31 made of the two-dimensional semiconductor material and the source 32 and the drain 33 made of the metal material have good ohmic contact, thereby achieving the purpose of the present invention.

[0055] like Figure 5 FIG. 1 is a schematic diagram showing the semiconductor element of the present invention applied to another gate-wrap field-effect transistor 4. The structure of the gate-wrap field-effect transistor 4 is substantially the same as that of the aforementioned field-effect transistor 3, with the difference being that the two ends of the three-channel layer 41 extend into the source 42 and the drain 43. The channel layer 41 made of a two-dimensional semiconductor material and the source 42 and drain 43 made of a metal material also have good ohmic contact due to the presence of the two-dimensional metal conductor layer 14, thereby achieving the purpose of the present invention.

Claims

1. A semiconductor device, characterized in that: Includes: A two-dimensional semiconductor layer is formed of a two-dimensional semiconductor material having a first formation energy; a two-dimensional metal conductor layer formed of a two-dimensional metal material and covering the surface of the two-dimensional semiconductor layer, wherein the two-dimensional metal material has a second heat of formation that is lower than the first heat of formation; as well as a metal layer covering the surface of the two-dimensional metal conductor layer; The two-dimensional metal conductor layer is formed by bonding cations in the metal layer and anions in the two-dimensional semiconductor layer.

2. The semiconductor device according to claim 1, wherein The combination of the two-dimensional semiconductor material / the two-dimensional metal material is molybdenum disulfide (MoS2) / niobium disulfide (NbS2), tungsten disulfide (WS2) / niobium disulfide (NbS2), vanadium disulfide (VS2) / niobium disulfide (NbS2), nickel disulfide (NiS2) / niobium disulfide (NbS2), palladium disulfide (PdS2) / niobium disulfide (NbS2), platinum disulfide (PtS2) / niobium disulfide (NbS2), molybdenum disulfide (MoS2) / tantalum disulfide (TaS2), tungsten disulfide (WS2) / tantalum disulfide (TaS2), vanadium disulfide (VS2) / tantalum disulfide (TaS2), nickel disulfide (NiS2) / tantalum disulfide (TaS2), palladium disulfide (PdS2) / tantalum disulfide (TaS2), platinum disulfide (PtS2) / Tantalum disulfide (TaS2), tungsten disulfide (WS2) / vanadium disulfide (VS2), nickel disulfide (NiS2) / vanadium disulfide (VS2), palladium disulfide (PdS2) / vanadium disulfide (VS2), platinum disulfide (PtS2) / vanadium disulfide (VS2), nickel disulfide (NiS2) / ferrous disulfide (FeS2), palladium disulfide (PdS2) / ferrous disulfide (FeS2), or platinum disulfide (PtS2) / ferrous disulfide (FeS2).

3. The semiconductor device according to claim 2, wherein The metal layer is formed of niobium, tantalum, vanadium or iron.

4. The semiconductor device according to claim 1, wherein The two-dimensional semiconductor material / the combination of the two-dimensional metal material is molybdenum diselenide (MoSe2) / niobium diselenide (NbSe2), tungsten diselenide (WSe2) / niobium diselenide (NbSe2), palladium diselenide (PdSe2) / niobium diselenide (NbSe2), platinum diselenide (PtSe2) / niobium diselenide (NbSe2), molybdenum diselenide (MoSe2) / tantalum diselenide (TaSe2), tungsten diselenide (WSe2) / tantalum diselenide (TaSe2), palladium diselenide (PdSe2) / tantalum diselenide (TaSe2), platinum diselenide (PtSe2) / tantalum diselenide (TaSe2), molybdenum diselenide (MoSe2) / vanadium diselenide (VSe2), tungsten diselenide (WSe2) / vanadium diselenide (VSe2), palladium diselenide (PdSe2) / vanadium diselenide (VSe2), platinum diselenide (PtSe2) / Vanadium diselenide (VSe2), molybdenum diselenide (MoSe2) / titanium diselenide (TiSe2), tungsten diselenide (WSe2) / titanium diselenide (TiSe2), palladium diselenide (PdSe2) / titanium diselenide (TiSe2), or platinum diselenide (PtSe2) / titanium diselenide (TiSe2).

5. The semiconductor device according to claim 4, wherein The metal layer is formed of niobium, tantalum, vanadium or titanium.

6. The semiconductor device according to claim 1, wherein The combination of the two-dimensional semiconductor material / the two-dimensional metal material is molybdenum ditelluride (MoTe2) / niobium ditelluride (NbTe2), molybdenum ditelluride (MoTe2) / titanium ditelluride (TiTe2), molybdenum ditelluride (MoTe2) / hafnium ditelluride (HfTe2), or molybdenum ditelluride (MoTe2) / zirconium ditelluride (ZrTe2).

7. The semiconductor device according to claim 6, wherein: The metal layer is formed of niobium, titanium, hafnium or zirconium.

8. The semiconductor element according to any one of claims 1 to 7, wherein: The two-dimensional semiconductor layer is a channel layer, and the metal layer is a source electrode or a drain electrode.

9. A method for manufacturing a semiconductor element according to any one of claims 1 to 7, characterized in that The following steps are involved: (A) forming a metal layer on the two-dimensional semiconductor layer; and (B) Annealing is performed at 600-1000° C. in a controlled atmosphere to allow metal cations in the metal layer to bond with anions in the two-dimensional semiconductor layer to form a two-dimensional metal conductor layer.

10. The method for manufacturing a semiconductor device according to claim 9, wherein: In step (B), the controlled atmosphere comprises nitrogen and hydrogen, and the ratio of nitrogen to hydrogen is between 80:20 and 90:10.

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