LED structure for reduced non-radiative sidewall recombination

Abstract

The present disclosure relates to LED structures for reduced non-radiative sidewall recombination. An LED structure is disclosed for reducing non-radiative sidewall recombination along sidewalls of a vertical LED including a p-n diode sidewall across a top current spreading layer, a bottom current spreading layer, and an active layer between the top current spreading layer and the bottom current spreading layer.

Description

[0001] Related patent applications

[0002] This application is a divisional application of the invention patent application with international application number PCT / US2017 / 039038, international application date of June 23, 2017, entry into the Chinese national phase date of November 22, 2018, Chinese national application number 201780031841.0, and invention title "LED Structure for Reduced Non-Radiative Sidewall Composite".

[0003] This patent application is a continuation-in-part of co-pending U.S. Patent Application No. 15 / 199,803, filed June 30, 2016, which is a continuation-in-part of U.S. Patent Application No. 14 / 853,614, filed September 14, 2015, now published as U.S. Patent No. 9,484,492, and claims priority to U.S. Provisional Application No. 62 / 100,348, filed January 6, 2015. The entire disclosures of these applications are incorporated herein by reference. Technical Field

[0004] The implementation scheme described in this article relates to LEDs. More specifically, the implementation scheme relates to micro LEDs. Background Technology

[0005] Light-emitting diodes (LEDs) are increasingly recognized as a replacement technology for existing light sources. For example, LEDs are found in signs, traffic signals, car taillights, mobile electronic displays, and televisions. The various advantages of LEDs compared to traditional lighting sources include increased efficiency, longer lifespan, variable emission spectrum, and the ability to be combined with a wide range of form factors.

[0006] One type of LED is the organic light-emitting diode (OLED), in which the diode's emitting layer is formed from organic compounds. One advantage of OLEDs is the ability to print the organic emitting layer onto flexible substrates. OLEDs have been integrated into thin, flexible displays and are often used in the manufacture of displays for portable electronic devices such as mobile phones and digital cameras.

[0007] Another type of LED is the inorganic semiconductor-based LED, where the diode's emitting layer comprises one or more semiconductor-based quantum well layers sandwiched between thicker semiconductor-based cladding layers. Some advantages of semiconductor-based LEDs compared to OLEDs include improved efficiency and longer lifetime. High luminous efficiency, expressed in lumens per watt (lm / W), is one of the main advantages of semiconductor-based LED lighting, allowing for lower energy or power usage compared to other light sources. Illuminance (luminance) is the amount of light emitted per unit area of ​​a light source in a given direction, and is expressed in cadmium per square meter (cd / m²). 2 Illuminance is measured in nits (nt) and is often referred to as illuminance. Illuminance increases with increasing operating current, but luminous efficiency depends on current density (A / cm²). 2 The luminous efficiency of an LED initially increases with increasing current density, reaching a maximum, and then decreases due to a phenomenon known as "efficiency decay." Many factors affect the luminous efficiency of an LED device, including its ability to generate photons internally, known as internal quantum efficiency (IQE). Internal quantum efficiency is a function of the quality and structure of the LED device. External quantum efficiency (EQE) is defined as the number of emitted photons divided by the number of injected electrons. EQE is a function of both the IQE and light extraction efficiency of the LED device. At low operating current densities (also known as injection current density or forward current density), the IQE and EQE of an LED device initially increase with increasing operating current density, and then begin to decrease with increasing operating current density due to a phenomenon known as efficiency decay. At low current densities, efficiency is low due to strong effects of defects or other processes that cause electrons and holes to recombine in the absence of light generation (known as nonradiative recombination). As those defects become saturated, radiative recombination becomes dominant, and efficiency increases. When the injection current density exceeds the characteristic value of the LED device, "efficiency decay" or a gradual decrease in efficiency begins. Attached Figure Description

[0008] Figure 1A This is a cross-sectional side view of the LED substrate according to the implementation scheme.

[0009] Figures 1B to 1F This is a cross-sectional side view of a single-sided process sequence for manufacturing an LED array, according to the implementation plan.

[0010] Figure 2 It is a cross-sectional side view of the LED, including the edge of the active layer along the sidewall of the LED.

[0011] Figure 3 This is a cross-sectional side view of an LED with a bottom current extension layer pillar structure having a reduced width compared to the active layer, according to the implementation scheme.

[0012] Figures 4A to 4EThis is a cross-sectional side view of a method for forming an LED with an in-situ regenerated pn junction sidewall passivation layer according to an implementation scheme.

[0013] Figure 4F This is a cross-sectional side view of an LED with an in-situ regenerated pn junction sidewall passivation layer, according to the implementation scheme.

[0014] Figures 5A to 5H This is a cross-sectional side view illustration of a method for forming an LED with vapor-phase etched sidewalls and a regenerated long sidewall passivation layer according to an embodiment.

[0015] Figure 5I This is a cross-sectional side view of an LED with a regenerated sidewall passivation layer according to the implementation scheme.

[0016] Figures 6A to 6E This is a cross-sectional side view illustration of a method for forming an LED with a diffusion sidewall passivation layer according to an implementation scheme.

[0017] Figure 6F This is a cross-sectional side view of an LED with a diffusion sidewall passivation layer according to the implementation scheme.

[0018] Figures 7A to 7E This is a cross-sectional side view of a method for forming a pn junction within an LED by selective diffusion according to an implementation scheme.

[0019] Figure 7F This is a cross-sectional side view of an LED with a selectively diffused pn junction according to the implementation scheme.

[0020] Figures 8A to 8E This is a cross-sectional side view illustration of a method for forming an LED with a diffused transverse junction according to an implementation scheme.

[0021] Figure 8F This is a cross-sectional side view of an LED with a diffused lateral junction, according to the implementation scheme.

[0022] Figures 9A to 9E This is a cross-sectional side view of a method for forming an LED by selective region growth and in-situ growth of a sidewall passivation layer, according to an implementation scheme.

[0023] Figure 9F It is a cross-sectional side view of an LED with an in-situ grown sidewall passivation layer selectively grown according to the implementation scheme, along the x-direction (111) plane.

[0024] Figure 9G It is a cross-sectional side view of an LED with an in-situ grown sidewall passivation layer selectively grown according to the implementation scheme, along the y-direction (111) plane.

[0025] Figures 10A to 10D This is a cross-sectional side view illustration of a method for forming an LED with a regenerated sidewall passivation layer according to an implementation scheme.

[0026] Figure 10E It is a cross-sectional side view of an LED with a regenerated sidewall passivation layer according to the implementation scheme along the x-direction (111) plane.

[0027] Figure 10F It is a cross-sectional side view of an LED with a regenerated sidewall passivation layer according to the implementation scheme along the y-direction (111) plane.

[0028] Figure 10G It is a cross-sectional side view of an LED with a regenerated sidewall passivation layer and a wide top current extension layer according to the embodiment, along the x-direction (111) plane.

[0029] Figure 10H It is a cross-sectional side view of an LED with a regenerated sidewall passivation layer and a wide top current extension layer according to the embodiment, along the y-direction (111) plane.

[0030] Figure 11A This is a close-up cross-sectional view of a pn diode layer formed on a patterned substrate according to an embodiment and including an orientation-dependent doped layer.

[0031] Figures 11B to 11D This is a cross-sectional side view illustration of a method for forming an LED pn junction with orientation-dependent doping according to an implementation scheme.

[0032] Figures 11E to 11F This is a cross-sectional side view illustration of an LED pn junction with orientation-dependent doping according to an embodiment.

[0033] Figures 12A to 12F This is a cross-sectional side view illustration of a method for forming an LED by selective etching and mass delivery according to an embodiment.

[0034] Figures 12G to 12H This is a cross-sectional side view of an LED including a notched active layer, according to the implementation scheme.

[0035] Figures 13A to 13C This is a cross-sectional side view illustration of a method for passivating the sidewalls of an LED by surface transformation according to an implementation scheme.

[0036] Figure 14A This is a cross-sectional side view of an LED having quantum dots in the active layer according to the implementation scheme.

[0037] Figure 14B This is a schematic top view of an LED active layer with quantum dots according to the implementation scheme.

[0038] Figures 15A to 15C This is a cross-sectional side view illustration of a method for forming an LED with nanopillars in the active layer according to the implementation scheme.

[0039] Figure 15D This is a cross-sectional side view illustration of an LED having nanopillars in the active layer according to the implementation scheme.

[0040] Figure 15E This is a cross-sectional side view illustration of an LED with a nanopillar and top cap configuration in an active layer, according to the implementation scheme.

[0041] Figures 16A to 16D This is a cross-sectional side view illustration of a method for forming an LED having a heterogeneous structure mixed at the sidewall of the pn diode layer, according to an embodiment.

[0042] Figure 16E This is a cross-sectional side view of the hybrid LED heterostructure according to the implementation plan.

[0043] Figure 16F This is a cross-sectional side view of the hybrid LED heterostructure and quantum well doped layer according to the implementation scheme.

[0044] Figures 17A to 17F This is a cross-sectional side view illustration of a method for forming an LED with a sidewall passivation layer according to an implementation scheme.

[0045] Figures 18A to 18D This is a cross-sectional side view illustration of a method for forming an LED having a heterogeneous structure mixed at the sidewall of the pn diode layer, according to an embodiment.

[0046] Figure 18E This is a cross-sectional side view of the hybrid LED heterostructure according to the implementation plan.

[0047] Figure 18F This is a cross-sectional side view of the hybrid LED heterostructure and quantum well doped layer according to the implementation scheme.

[0048] Figures 19A to 19D This is a cross-sectional side view illustration of a method for forming an LED having a heterogeneous structure mixed at the sidewall of the pn diode layer, according to an embodiment.

[0049] Figure 19E This is a cross-sectional side view of the hybrid LED heterostructure according to the implementation plan.

[0050] Figure 19F This is a cross-sectional side view of the hybrid LED heterostructure and quantum well doped layer according to the implementation scheme.

[0051] Figure 20 It is an in-plane band structure of quantum well material with unstrained, compressive, and tensile strain according to the implementation scheme.

[0052] Figure 21 This is a cross-sectional side view of an LED heterostructure with tensile strain and modulation-doped quantum well active regions, according to an embodiment.

[0053] Figure 22 This is a cross-sectional side view of an LED with a current-spreading layer pillar structure having a width reduced compared to the active layer, according to the implementation scheme.

[0054] Figure 23 This is a cross-sectional side view of an LED with a current-spreading column structure and a recessed partition, according to the implementation scheme.

[0055] Figures 24A to 24C This is a cross-sectional side view illustration of a method for forming an LED with a plasma processing restricted area according to an embodiment.

[0056] Figure 25A This is a side view illustration of an LED integrated into a display panel with embedded circuitry, according to the implementation scheme.

[0057] Figure 25B This is a side view illustration of an LED integrated into a display panel with a microchip, according to the implementation scheme.

[0058] Figure 26 This is a schematic diagram of the display system according to the implementation plan.

[0059] Figure 27 This is a schematic diagram of the lighting system according to the implementation plan. Detailed Implementation

[0060] The embodiments describe LEDs and LED manufacturing methods having various structural configurations for mitigating nonradiative recombination at the LED sidewalls. For example, various configurations may include sidewall passivation techniques, current limiting techniques, and combinations thereof. However, some embodiments may be implemented without one or more of these specific details or without combining with other known methods and configurations. In the following description, numerous specific details such as particular configurations, dimensional processes, etc., are shown to provide a thorough understanding of the embodiments. In other instances, well-known semiconductor processes and manufacturing techniques are not described in particular detail to avoid unnecessarily obscuring the embodiments. The phrase "an embodiment" as used throughout the specification means that a particular feature, structure, configuration, or characteristic described in connection with the embodiment is included in at least one embodiment. Therefore, the phrase "in one embodiment" appearing multiple times throughout the specification does not necessarily refer to the same embodiment. Furthermore, particular features, structures, configurations, or characteristics may be combined in any suitable manner in one or more embodiments.

[0061] As used herein, the terms “above,” “over,” “to,” “between,” “across,” and “on” can refer to the relative position of one layer with respect to other layers. A layer being “above,” “over,” “across,” or “on” another layer, or being bonded “to” or “in contact” with another layer, can mean directly contacting other layers or having one or more interlayers. A layer being “between” multiple layers can mean directly contacting those multiple layers or having one or more interlayers.

[0062] In one aspect, embodiments describe LEDs, which may be microLEDs, comprising specific structural configurations to mitigate nonradiative recombination at the LED sidewalls. It has been observed that the sidewalls of emitting LEDs can represent the nonradiative recombination sites for injected carriers. This can be due to sidewalls characterized by unsatisfactory adhesion, chemical contamination, and structural damage (especially if dry-etched). Injected carriers recombine nonradiatively in states associated with these defects. Consequently, the periphery of the LED can be an optical dead zone, and the overall efficiency of the LED is reduced. This nonradiative recombination can also be due to band bending at the surface, resulting in a density of states where electrons and holes can be confined before nonradiative recombination. The characteristic distance at which sidewall surface effects occur is related to the carrier diffusion length, which, according to embodiments, can typically be 1–10 μm in some applications. Therefore, efficiency degradation is particularly severe in microLEDs where the lateral dimensions of the LED are close to the carrier diffusion length.

[0063] Such nonradiative recombination can significantly impact LED device efficiency, especially when the LED is driven at low current densities in the pre-decay region of its characteristic internal quantum efficiency (IQE) curve, where the current cannot saturate the defects. According to embodiments, sidewall passivation techniques, current-limiting structures, and combinations thereof are described that reduce the amount of nonradiative recombination near the outer or side surfaces of the active layer and improve the efficiency of the LED device.

[0064] In some embodiments, the term "micro" LED as used herein may refer to a descriptive size of the LED, such as length or width. In some embodiments, the scale of a "micro" LED may be from 1 μm to about 300 μm, or in some applications 100 μm or less. More specifically, in some embodiments, the scale of a "micro" LED may be from 1 μm to 20 μm, such as 10 μm or 5 μm, where the lateral dimension of the LED is close to the carrier diffusion length. However, it should be understood that embodiments are not necessarily limited to this, and certain aspects of the embodiments may be applicable to larger, and possibly smaller, scales.

[0065] In the implementation, the sidewall surfaces of the LED, including at least the active layer, are passivated to restore the LED's radiative efficiency. Various structural configurations have been disclosed for sidewall passivation, encompassing various regrowth and diffusion techniques. Such sidewall passivation can have several effects, depending on the specific passivation technique. One effect could be maintaining the lattice structure and minimizing defects at the LED sidewalls and / or active layer edges, thereby mitigating the effects of non-radiative combinations at the LED sidewalls and / or active layer edges. Another effect could be moving the LED sidewalls and / or active layer edges into the interior of the pn diode layer, such that the current injection path is confined within the pn diode layer away from potentially defective pn diode layer sidewalls.

[0066] In this implementation, in-situ etching is performed to form LED sidewalls adjacent to the active layer. This is, for example, performed in an MOCVD epitaxial growth reactor. Thus, pure chemical etching introduces minimal structural damage compared to dry etching techniques such as ICP / RIE. The in-situ etching is then immediately followed by in-situ epitaxial regeneration of a passivation layer on the newly formed surface sidewalls. Since there is no air exposure, oxidation of the sidewalls is eliminated. Because the passivation layer is epitaxially grown on the LED sidewalls, any dangling bonds at the free surface (before regeneration) are satisfied. Therefore, the lattice structure is preserved, and defects at the LED sidewalls are minimized. This reduces surface recombination at the LED sidewalls.

[0067] In some implementations, the diffusion technique results in the movement of the LED sidewalls and / or the lateral edges of the active layer (e.g., including one or more quantum wells) into the interior of the pn diode layer. Therefore, by forming a passivation layer within the pn diode layer and laterally surrounding the internally confined active layer, a barrier is formed for lateral carrier diffusion from the active layer. This barrier prevents lateral carrier diffusion from the active layer edges to the sidewalls of adjacent pn diode layers where defects may exist. Therefore, in some implementations, the passivation layer can be narrower than the 1-10 μm carrier diffusion length mentioned above.

[0068] Several other structural configurations are described for passivating LED sidewalls and reducing surface recombination. In some embodiments, the epitaxial growth of the sidewall passivation layer is performed anatomically. For example, this can be performed after vapor etching of the LED sidewalls of a GaN-based LED.

[0069] In the implementation, sidewall passivation is achieved by diffusion into the exposed pn diode layer sidewalls to shift the edge of the active layer into the interior of the pn diode layer.

[0070] In this implementation, the active layer is formed inside the LED by diffusion. This allows the current injection path to be internally guided through the LED and away from the sidewalls.

[0071] In the implementation scheme, the LED mesa is selectively grown, and then a sidewall passivation layer is grown in situ to cover the edge of the active layer.

[0072] In this embodiment, the LED active layer and the cladding layer are grown on a patterned substrate such that the n-doping and p-doping within the layers depend on the surface orientation. For example, in this embodiment, p-dops and n-dops flow into the chamber simultaneously, where they preferentially deposit on different exposed planes.

[0073] In one implementation, the active layer is selectively etched to create a notch between the n-doped cladding layer (or current spreading layer) and the p-doped cladding layer (or current spreading layer). This notch is then filled by mass delivery, resulting in the edge of the active layer being confined to the interior of the pn diode layer.

[0074] In this implementation, the bandgap energy at the sidewalls of the pn diode layer is enhanced through surface conversion. For example, the sidewalls of the pn diode layer can be exposed to vapor-phase chemistry at high temperatures, where Group V species evaporate (e.g., As) and are replaced by Group V vapor-phase species (e.g., P). Thus, the higher bandgap energy at the sidewall surface effectively confines the active layer to the interior of the pn diode layer.

[0075] In this implementation, deposition conditions and layer strain are controlled to utilize the miscibility gaps between the deposited components in the active layer and to form a heterogeneous composition in which certain species segregate and form agglomerates. This achieves a quantum dot effect, which reduces lateral propagation throughout the active layer and minimizes the resulting sidewall recombination at the surface.

[0076] In this implementation, the nanopillars are formed through selective growth or patterning. The formation of nanopillars can contribute to the quantum dot effect, which utilizes carrier localization at the point or pillar, thus reducing lateral spread across the entire active layer. The formation of nanopillars can also increase the surface area within the active layer, thereby reducing the relative surface area of ​​the active layer at the LED sidewalls.

[0077] In this implementation, selective diffusion is used to generate vacancies, resulting in interdiffusion at the sidewalls of the pn diode layer. This generates higher bandgap energy at the sidewall surfaces that effectively confine the active layer to the interior of the pn diode layer.

[0078] In the implementation, atomic layer deposition (ALD) is used to form a sidewall passivation layer (e.g., Al2O3) around the sidewalls of the pn diode layer.

[0079] According to some embodiments, any of the above structural configurations can be combined with a current-spreading layer pillar structure. For example, either the p-doped or n-doped layer in a pn configuration can be considered a current-spreading layer. In embodiments, any of the current-spreading layers is patterned such that it is narrower than the active layer including the pn diode. In some of the illustrated exemplary embodiments, the bottom current-spreading layer (e.g., a p-doped layer) is patterned to form a pillar structure with reduced width. Thus, when a potential is applied to the LED, the current injection region within the active layer is modified by the area relationship between the bottom current-spreading layer pillar and the top current-spreading layer. In operation, the current injection region decreases as the bottom current-spreading layer pillar configuration decreases. Thus, the current injection region can be internally confined within the active layer away from the outer or side surfaces of the active layer.

[0080] Furthermore, when employing a current-spreading layer pillar structure, it is possible to design LEDs where the top surface area of ​​the pn diode layer is larger than the surface area of ​​the current-limited region within the active layer. This allows for the fabrication of larger LED devices, which may be advantageous for transferring the LED device using an electrostatic transfer head assembly. This also provides a structure where the limited current injection region leads to increased current density and efficiency in the LED device, especially when operating with injection current and injection current density below or near the pre-decay region of the LED device's IQE curve.

[0081] In the following description, an exemplary processing sequence is described for forming an LED array, where the LEDs may be microLEDs. See now. Figure 1A A cross-sectional side view of a bulk LED substrate 100, including a pn diode layer 115 formed on a growth substrate, is provided according to an embodiment. For example, Figure 1A The pn diode layer 115 shown may be designed to emit primary red light (e.g., 620-750 nm wavelength), primary green light (e.g., 495-570 nm wavelength), or primary blue light (e.g., 450-495 nm wavelength), but the implementation is not limited to these exemplary emission spectra. The pn diode layer 115 may be formed of multiple compound semiconductors having band gaps corresponding to specific regions in the spectrum. For example, the pn diode layer 115 may comprise one or more layers based on II-VI materials (e.g., ZnSe) or III-V materials (including III-V nitride materials (e.g., GaN, AlN, InN, InGaN and alloys thereof), III-V phosphide materials (e.g., GaP, AlGaInP and alloys thereof), and III-V arsenide alloys (AlGaAs)). The growth substrate 100 may comprise any suitable substrate, such as, but not limited to, silicon, SiC, GaAs, GaN, and sapphire.

[0082] The pn diode layer 115 can include various configurations depending on the application. Generally, the pn diode layer 115 includes a current spreading layer 104 of a first dopant type (e.g., n-doped), a current spreading layer 112 of the opposite dopant type (e.g., p-doped), and an active layer 108 between the current spreading layers 104 and 112. For example, the active layer 108 can be a single quantum well (SQW) or multiple quantum well (SQW) layer. In embodiments, a reduced number of quantum wells provides greater resistance to lateral current spread, higher carrier density, and helps to internally confine the current within the completed LED. In embodiments, the active layer 108 includes an SQW. In embodiments, the active layer 108 is a MWQ structure with fewer than 10 quantum well layers. In embodiments, the active layer 108 is a MWQ structure with 1-3 quantum wells. Additional layers may optionally be included in the pn diode layer 115. For example, cladding layers 106 and 110 may be formed on opposite sides of the active layer 108 to confine current within the active layer 108, and may have a larger bandgap than the active layer 108. Cladding layers 106 and 110 may be doped to match the doping of adjacent current spreading layers 104 and 112. In one embodiment, cladding layer 106 is doped with an n-type dopant, and cladding layer 110 is doped with a p-type dopant, or vice versa. According to another embodiment, the current spreading layer may function similarly to the cladding layer.

[0083] By way of example, in one embodiment, the pn diode layer 115 is designed to emit red light, and the material is phosphorus-based. The following list of materials used for red light emission is intended to be exemplary and not limiting. For example, the layers forming the pn diode layer 115 may include AlInP, AlInGaP, AlGaAs, GaP, and GaAs. In one embodiment, the current spreading layer 104 comprises n-AlInP or n-AlGaInP, the cladding layer 106 comprises n-AlInGaP, the cladding layer 110 comprises p-AlGaInP, and the current spreading layer 112 comprises p-GaP or p-AlInP. The quantum well 108 may be formed of a variety of materials, such as, but not limited to, AlGaInP, AlGaAs, and InGaP. In such embodiments, a suitable growth substrate 102 may include, but is not limited to, silicon, SiC, and GaAs.

[0084] By way of example, in one embodiment, the pn diode layer 115 is designed to emit blue or green light, and the material is nitride-based. The following list of materials used for blue or green light emission is intended to be exemplary and not limiting. For example, the layers forming the pn diode layer 115 may include GaN, AlGaN, or InGaN. In one embodiment, the current spreading layer 104 comprises n-GaN, the cladding layer 106 is optionally absent, the cladding layer 110 comprises p-AlGaN, and the current spreading layer 112 comprises p-GaN. The quantum well 108 may be formed of a variety of materials, such as, but not limited to, InGaN. In such embodiments, a suitable growth substrate 102 may include, but is not limited to, silicon and sapphire. In one embodiment, the cladding layer 106 may not be necessary for nitride-based LEDs due to the internal piezoelectric and spontaneous polarization field.

[0085] Figures 1B to 1F This is a cross-sectional side view of a single-sided process sequence used to manufacture LED arrays. (See diagram.) Figure 1B As shown, an array of conductive contacts 116 is formed on a pn diode layer 115, and the pn diode layer 115 is etched to form trenches 118 between mesa structures 120. The conductive contacts 116 may comprise a multilayer stack. Exemplary layers may include electrode layers, mirror layers, adhesive / barrier layers, diffusion barriers, and adhesive layers for bonding the completed LED to a receiving substrate. In an embodiment, the conductive contacts 116 are formed on a p-doped current spreading layer 112 and are functionally p-contacts. Etching can be performed using suitable techniques such as dry etching or wet etching. Figure 1B In the illustrated embodiment, the trench is not formed completely through the n-doped current spreading layer 104. Alternatively, the trench is formed completely through the n-doped current spreading layer 104. In some embodiments, the pillars partially penetrate the p-doped current spreading layer 112 (see [link to embodiment]). Figure 3 ).For example, Figure 3 The structure formed can be formed using a single-sided or double-sided process. In the double-sided process, the pillars are formed using a single-sided process, and the mesa structure is etched using a double-sided process after being transferred to the receiving substrate.

[0086] After forming the mesa structure 120, a sacrificial release layer 122 can be formed on the patterned pn diode layer 115 and then patterned to form an opening 124 above the conductive contact 116. The sacrificial release layer 122 can be made of an oxide (e.g., SiO2) or a nitride (e.g., SiN). x The opening 124 can be formed, but other materials that can be selectively removed relative to other layers can be used. The height, width, and length of the opening 124 will correspond to the height, length, and width of the stabilizing pile to be formed, and the result will correspond to the adhesive strength that must be overcome in order to pick up the array of LEDs (e.g., microLEDs) held stable for use on the stabilizing pile array.

[0087] See now Figure 1D The patterned structure on the growth substrate 102 is bonded to the carrier substrate 140 with an adhesive bonding material to form a stabilizing layer 130. In an embodiment, the adhesive bonding material is a thermosetting material, such as benzocyclobutene (BCB) or epoxy resin. A portion of the filling opening 124 of the stabilizing material corresponds to a stabilizing post 132 of the stabilizing layer, and a portion of the filling groove 118 of the stabilizing material becomes a stabilizing cavity sidewall 134 of the stabilizing layer.

[0088] After bonding to the carrier substrate 140, the growth substrate can be removed using suitable techniques such as laser lift-off, etching, or grinding to expose the pn diode layers 115. Any remaining portions of the n-doped current extension layers 104 connecting the separated mesa structures 120 can then be removed using etching or grinding to form laterally separated pn diode layers 115. A top conductive contact layer 142 can then be formed over each laterally separated pn diode layer to obtain the LED 150. Figure 1E and Figure 1F The alternative structures that are available depend on the amount of material removed after removing the growth substrate 102 and etching or grinding it back to expose the mesa structure 120.

[0089] In the single-sided process described above, the pn diode layer 115 is patterned to form a mesa structure 120 before being transferred to the carrier substrate 140. Alternatively, the LED according to the embodiment can be manufactured using a double-sided process, wherein the pn diode layer 115 is transferred from the growth substrate to the carrier substrate 140, and then the pn diode layer is patterned to form the mesa structure 120. A variety of processing techniques can be used to obtain a similar final structure, including sidewall passivation techniques, current limiting techniques, and combinations thereof. Therefore, although the LED structures described below are all described using a single-sided processing sequence, this is exemplary and not intended to be limiting.

[0090] Figures 2 to 3 It can be used and referenced Figures 1B to 1F An exemplary cross-sectional side view illustration of an LED formed using a similar single-sided process as described above. Figure 2 This is a cross-sectional side view of an LED including the edge 151 of the active layer 108 along the sidewall 153 of the pn diode layer. Figure 3 This is a cross-sectional side view of an LED with a bottom current extension layer 112 pillar structure whose width is reduced compared to the active layer 108. Figure 3 In the specific structure shown, the current spreading layer pillar 112 can be used to internally limit the current injection path away from the edge 151 of the active layer 108 along the sidewall 153 of the pn diode layer. Figure 2 and Figure 3 In each case, the edge 151 of the active layer 108 may be damaged due to etching of the sidewalls 153 of the mesa structure 120 of the pn diode layer 115. Therefore, the edge of the active layer may be a site of nonradiative recombination. Various structural configurations are described herein to mitigate nonradiative recombination at the edges of the active layer, according to embodiments thereof. For example, these various configurations may include sidewall passivation techniques, current limiting techniques, and combinations thereof.

[0091] See now Figures 4A to 4E A cross-sectional side view illustration is provided for a method of forming an LED with an in-situ regenerated pn junction sidewall passivation layer according to an implementation scheme. Figures 4A to 4E The specific processing sequence shown can be generally applied to any LED emitting colored light, including red, blue, and green, and may include the above references. Figure 1A Any of the pn diode layer 115 configurations. Furthermore... Figures 4A to 4EThe processing sequence shown may include in-situ etching and regrowth. As shown, a mask 117 is formed over a pn diode layer 115 to etch trench 118 at least partially into a doped current spreading layer 104. The mask 117 may be formed of a dielectric material such as SiO2 capable of withstanding the high temperatures and aggressive etching chemicals associated with the etching and regrowth processes. In an embodiment, the etching process is a purely chemical etching performed in a metal-organic chemical vapor deposition (MOCVD) chamber. In an embodiment, trench 118 is formed by a first partial dry etching, after which the wafer is transferred to the MOCVD chamber to complete the etching of trench 118. Thus, the final etched surface is tempered by etching in the MOCVD chamber, and physical damage generated during the dry etching operation is removed by chemical etching in the MOCVD chamber. Exemplary dry etching techniques that may be used include reactive ion etching (RIE), electron cyclotron resonance (ECR), inductively coupled plasma reactive ion etching (ICP-RIE), and chemically assisted ion beam etching (CAIBE). Dry etching chemistry can be halogen-based, containing species such as Cl2, BCl3, or SiCl4. Etching temperatures within the MOCVD chamber can also be high, such as 400°C to 700°C. Specific etching chemistry may include a combination of corrosive etchants and Group V decomposition inhibitors to stabilize Group V components and inhibit decomposition that might otherwise occur at the high etching temperatures.

[0092] In one embodiment, the LED is designed for red light emission, and the pn diode layer 115 is phosphorus-based. In such embodiments, the etching chemical composition includes a corrosive etchant such as HCl or Cl2, and a Group V decomposition inhibitor such as PH3. In another embodiment, the LED is designed for green or blue light emission, and the pn diode layer 115 is nitride-based. In such embodiments, the etching chemical composition includes a corrosive etchant such as HCl, Cl2, or H2 (or combinations thereof), and a Group V decomposition inhibitor such as NH3.

[0093] After trench 118 is formed, passivation layer 402 is epitaxially regrown within trench 118. The regrowing of passivation layer 402 is performed in situ within the MOCVD chamber immediately after etching trench 118 without exposure to air or removal from the MOCVD chamber. Since passivation layer 402 is epitaxially regrown on the original surface, it acts as a surface passivator for pn diodes, specifically for active layer 108. According to embodiments, passivation layer 402 has a higher bandgap than the individual layers within pn diode layer 115. Passivation layer 402 can also be p-type. For phosphorus-based red emitting LEDs, passivation layer 402 can be p-type doped with Mg or Zn dopants. For example, the passivation layer can be AlInGaP:Mg,Zn. For nitride-based green or blue emitting LEDs, passivation layer 402 can be p-type doped with Mg. For example, the passivation layer can be AlGaN:Mg. For nitride-based green or blue emitting LEDs, the passivation layer 402 can be insulated with C or Fe dopants. For example, the passivation layer can be AlGaN:C,Fe.

[0094] The mask 117 can then be removed, and conductive contacts 116 can be formed on the exposed portion of the pn diode layer 115 (e.g., a p-doped current spreading layer 112), such as... Figure 4C As shown. Then, trench 410 is etched through passivation layer 402 and pn diode layer 115 to form mesa structure 420, as shown. Figure 4D As shown. For example, dry etching technology can now be used. Alternatively, trench 410 is wet-etched to reduce surface damage to the sidewalls of the pn diode layer 115, which become the pn diode layer sidewalls 153 of the LED. In another embodiment, a combination of dry etching followed by wet etching is used. The mesa structure 420 can then be transferred to the configuration described above. Figures 1B to 11F The carrier substrate 140 and the top conductive contact 142 are similarly formed as discussed.

[0095] Figure 4F This is a cross-sectional side view of an LED with an in-situ regrown pn junction sidewall passivation layer according to an embodiment. As shown, the passivation layer 402 laterally surrounds the LED sidewall 151 (which also corresponds to the edge of the active layer 108) and the pn diode layer sidewall 153. In this embodiment, no structural damage is introduced because the in-situ etching is purely chemical, and chemical contamination is eliminated because there is no air exposure. The passivation layer 402 is epitaxially grown, thereby satisfying all adhesion at the original surface. In this way, surface recombination is minimized, and the radiative efficiency of the LED is restored. Still referring to... Figure 4F The regenerated long pn junction passivation layer 402 can be formed from a high bandgap material, thus possessing a higher Ve than the emitter pn junction. o1 Higher turn-on voltage (V) o2), that is, V o2 >V o1 Therefore, the current will preferentially flow through the intended region of emitted light.

[0096] Figures 5A to 5H This is a cross-sectional side view illustration of a method for forming an LED with vapor-phase etched sidewalls and a regenerated long sidewall passivation layer according to an embodiment. In the embodiment, Figures 5A to 5H The processing sequence shown involves nitride-based LEDs emitting green or blue light. As mentioned above, the AlGaN cladding layer 106 can be omitted due to its internal piezoelectricity and spontaneous polarization field. Furthermore, the cladding layer 110 can also be derived from... Figure 5A The pn diode layer shown is omitted. As described above, the microLED according to the embodiment can operate at a lower current than conventional LEDs. Therefore, in the embodiment, the AlGaN cladding layers 106, 110 on either side of the quantum well 108 may not be necessary. In the embodiment, the pn diode layer 115 includes a p-GaN layer 112, an InGaN active layer 108, and an n-GaN layer 104.

[0097] like Figure 5B As shown, a thin semiconductor mask layer 513 is formed above the pn diode layer 115. In an embodiment, the semiconductor mask layer 513 is formed of AlGaN. See now. Figures 5C to 5D The trench 118 is etched at least partially through the pn diode layer 115 to form a mesa structure 520. An initial RIE / ICP etching can be used to etch the shallow trench 118 through the AlGaN semiconductor mask layer 513. This can be followed by a high-temperature H₂+NH₃ vapor phase etching to complete the etching of the trench 118. For example, H₂+NH₃ vapor phase etching results in minimal structural damage compared to RIE / ICP etching and can be etched at a planar rate of approximately 200 nm / h, thereby forming vertical m-planar sidewalls. Since the AlGaN cladding layers 106 and 110 are absent, they do not hinder or block the H₂+NH₃ vapor phase etching. Vertical sidewalls are obtained when the trench is correctly oriented.

[0098] See now Figures 5E to 5HThe epitaxially regenerated passivation layer 502 can be formed over the patterned pn diode layer and the semiconductor mask layer 513. For example, the passivation layer 502 can be regenerated p-GaN. According to an embodiment, the epitaxial regeneration of the passivation layer 502 is dissimilar to the vapor-phase etching of the trench 118. In an exemplary embodiment, there is no aluminum-containing layer within the pn diode layer 115, therefore, the sidewalls of the mesa structure 520 are not oxidized after vapor-phase etching. Thus, the epitaxially regenerated passivation layer 502 can match the lattice structure of the vapor-phase etched sidewalls to a minimum defect. In a specific embodiment, the passivation layer 502 is epitaxially regenerated in situ, i.e., immediately after vapor-phase etching in the MOCVD reactor, thus without air exposure. The trench 518 is then etched through the epitaxially regenerated passivation layer 502, and the structure is transferred to the carrier substrate 140, as described above. Figure 5I This is a cross-sectional side view of an LED with a regenerable long sidewall passivation layer according to an embodiment. As shown, the LED 550 includes a passivation layer 502 formed around the sidewall 153 and below the pn diode layer 115, and bottom conductive contacts 116 are formed on the p-doped passivation layer 502. As shown, the passivation layer 502 does not completely cover the sidewall of the n-doped current extension layer 104 and does not reach the top surface of the pn diode layer. Thus, a pn junction is formed at the interface of 502-104, which has a higher turn-on voltage than at the active layer 108, and current preferentially flows through the intended region of emitted light. In addition, in the illustrated embodiment, the passivation layer 502 is laterally positioned around the active layer 108 within the LED 550, such that the edge 151 of the active layer 108 is passivated by the passivation layer 502.

[0099] Figures 6A to 6E This is a cross-sectional side view illustrating a method for forming an LED with a diffused sidewall passivation layer according to an embodiment. In the embodiment, Figures 6A to 6E This relates to phosphorus-based LEDs designed to emit red light. In one embodiment, the pn diode layer 115 includes the features described above. Figure 1A Any of the compositions discussed. See now. Figure 6AThe pn diode layer 115 is patterned to form a trench 118 that at least partially penetrates the current spreading layer 104. A mask 605 may be used to define a mesa structure 120 during the etching of the trench 118. After the trench 118 is formed, a diffusion operation is performed to diffuse species into the sidewalls of the mesa structure 120 and form a passivation layer 602. Diffusion may also occur on the exposed surfaces of the pn diode layers 115 between the mesa structures 120, and optionally on the top of the mesa structure 120 (if the mask 605 has been removed). The diffusion and formation of the passivation layer 602 displaces the previously exposed pn junction (and active layer 108) into the interior of the LED. Thus, the pn junction does not intersect the surface and is formed of undamaged material. In one embodiment, a hybrid heterostructure is formed. Specifically, in this embodiment, the AlInGaP heterostructure is grown under specific conditions and substrate orientation to spontaneously generate an ordered alloy crystal structure (CuPt-type ordering, comprising a GaAlP-InP monolayer superlattice on the (111) crystal plane). The ordered alloy cladding layer 106 (e.g., n-AlInGaP), quantum well layer 108 (InGaP), and cladding layer 110 (e.g., p-AlGaInP) are characterized by low bandgap energies. The aforementioned diffusion process randomizes the alloy, thereby increasing its bandgap energy. The randomized sidewalls with higher bandgap energies naturally form a barrier that suppresses sidewall recombination. Thus, randomized AlInGaP forms a passivation layer 602. Various methods can be used to form the passivation layer 602, including implantation, vapor diffusion, and coating a source layer followed by heating (solid-state source diffusion).

[0100] In the implementation, a p-dopant such as Zn or Mg is implanted and / or diffused to change the n-type layer (110, 112) to p-type in the passivation layer 602. Alternatively, another species such as Fe, Cr, Ni, or another dopant may be added to make the passivation layer 602 semi-insulating. Alternatively, He or H may be implanted, also known as proton bombardment or proton implantation. The damage produced by proton bombardment further increases the resistivity of the implanted passivation layer 602. The implantation energy can be controlled so as not to produce too much damage and act as a significant source of nonradiative recombination.

[0101] After the passivation layer 602 is formed, refer to the above. Figures 1B to 1F The same processing structure is used to form LED650. Figure 6FThis is a cross-sectional side view of an LED with a diffused sidewall passivation layer according to an embodiment. As shown, the LED 650 includes a passivation layer 602 formed within the sidewall 153 of the pn diode layer 115. As shown, the passivation layer 602 does not completely cover the sidewall of the n-doped current extension layer 104 and does not reach the top surface of the pn diode layer. Thus, a pn junction is formed at the interface of 602-104, where a higher turn-on voltage is obtained than at the active layer 108, and current preferentially flows through the intended region of emitted light. Additionally, in the illustrated embodiment, the passivation layer 602 laterally surrounds the active layer 108 within the LED 650, such that the LED sidewall 151 (corresponding to the edge of the active layer 108) is internally confined within the pn diode layer sidewall 153, which has been converted into the passivation layer 602.

[0102] Figures 7A to 7E This is a cross-sectional side view illustrating a method for forming a pn junction within an LED via selective diffusion, according to an embodiment. Figure 7A In the specific implementation shown, the epitaxial layer 715 and Figure 1A The pn diode layer 115 shown differs slightly in that layers 710 and 712 are n-doped instead of p-doped (layers 110 and 112). Therefore, the initial epitaxial layer 715 comprises an n- / n heterostructure, and the pn junction has not yet formed. In an embodiment, the epitaxial layer 715 includes an (n)-AlInP current spreading layer 104, an (n)-AlInGaP cladding layer 106, a quantum well layer 108, an (n-)-AlGaInP cladding layer 710, and an (n-)AlInP current spreading layer 712. According to... Figures 7A to 7E In the embodiment shown, the pn junction is formed by diffusing a p-dopant, such as Mg or Zn, into the current spreading layer 712 and the cladding layer 710. The diffusion can originate from a solid-state source or vapor, as referenced above. Figures 6A to 6E As stated above.

[0103] refer to Figure 7B The p-doped region 702 is diffused into the cladding layer 710 and the current spreading layer 712, as described above, stopping before the p-dopant penetrates into the active layer 108. After diffusion, an insulating layer 711 is formed over the epitaxial layer 715. The insulating layer 711 can be formed from various materials, including SiO2 and SiN. x See now. Figure 7C An opening is formed in the insulating layer 711, and a conductive contact 116 is formed above the opening. Then, a trench 118 is etched through the insulating layer 711 and the epitaxial layer 715 to form a mesa structure 720. Figures 7D to 7E The processing sequence shown can then be similar to that described above. Figures 1B to 1F The above is used to form LED 750.

[0104] Figure 7F This is a cross-sectional side view of an LED with a selectively diffused pn junction according to an embodiment. As shown, the LED 750 includes an internally confined p-doped region 702 extending through an (n-)doped current spreading layer 712 and an (n-)doped cladding layer 710. An insulating layer 711 may optionally be formed to cover the junction between the p-doped region 702 and the (n-)doped current spreading layer 712, such that the bottom conductive contact 116 does not contact the (n-)doped current spreading layer 712. Figure 7F In the embodiment shown, the current injection region into the active layer 108 is internally confined within the LED by the p-doped region 702.

[0105] Figures 8A to 8E This is a cross-sectional side view illustration of a method for forming an LED with a diffused lateral junction according to an embodiment. In the embodiment, Figure 8A The epitaxial layer 815 shown is Figure 7A The epitaxial layer 715 shown is the same, where layers 810 and 812 correspond to layers 710 and 712. Figures 8A to 8E The processing sequence shown is basically similar to Figures 7A to 7E As shown, the difference is that the p-doped region 812 is formed through layers 812, 810, 108, 106 and partially enters the current spreading layer 104.

[0106] Figure 8F This is a cross-sectional side view of an LED 850 with a diffused lateral junction according to an embodiment. As shown, the pn junction forms a lateral junction within the active layer 108. Figure 8F In the embodiment shown, the current injection region into the active layer 108 is internally confined within the LED by the p-doped region 802. Furthermore, the pn junction is lateral and is internally confined within the LED 850.

[0107] Figures 9A to 9E This is a cross-sectional side view illustrating a method for forming an LED by selective region growth and in-situ growth of a sidewall passivation layer, according to an embodiment. In the embodiment, Figures 9A to 9E The method shown involves phosphorus-based LEDs designed to emit red light and having a cubic crystal structure. Figures 9A to 9E The method shown can be applied to other types of crystal structures and can yield more complex sidewall shapes. (Reference) Figure 9AA patterned mask layer 111 is formed over the growth substrate 102. In one embodiment, the patterned mask layer 111 is formed directly on the growth substrate 102, which will eventually be removed. In the specific embodiment shown, the patterned mask layer 111 is formed on a partially formed current spreading layer 104. A mesa structure 920 can then be selectively grown in pre-defined openings within the patterned mask layer 111. The mesa structure 920 may include features referenced above. Figure 1A The epitaxial layer, similar to the pn diode layer 115, is used for red light emission. In an embodiment, selective region growth results in no growth (111) sidewalls near the (100) surface. After forming the mesa structure 920 including the pn diode layer, an in-situ sidewall passivation layer 902 is grown (as with the mesa structure growth). In an embodiment, the passivation layer comprises AlInP, which may be p-doped. In an embodiment, the passivation layer 902 is grown in situ immediately after the formation of the mesa structure 920 without being removed from the MOCVD reactor. The passivation layer 902 is conformally grown by lowering the growth temperature to avoid evaporation or migration of deposited species. After forming the sidewall passivation layer 902, conductive contacts 116 are formed and can be referenced above. Figures 1B to 1F The same processing sequence is executed to form LED950.

[0108] Figure 9F It is a cross-sectional side view of an LED with an in-situ grown sidewall passivation layer selectively grown according to the implementation scheme, along the x-direction (111) plane. Figure 9G This is a cross-sectional side view along the y-direction (111) plane of a selectively grown LED with an in-situ grown sidewall passivation layer according to the implementation scheme. Figures 9F to 9G As shown, the passivation layer 902 can be similar to the one described in the reference above. Figure 5I As shown, LED 950 includes a passivation layer 902 formed around sidewall 153 and below pn diode layer 115, and bottom conductive contacts 116 are formed on p-doped passivation layer 902. As shown, passivation layer 902 does not completely cover the sidewall of n-doped current extension layer 104 and does not reach the top surface of pn diode layer. Thus, a pn junction is formed at the interface of 902-104, having a higher turn-on voltage than at active layer 108, and current preferentially flows through the intended region of emitted light. Additionally, in the illustrated embodiment, passivation layer 902 is laterally positioned around active layer 108 within LED 950, such that the edge 151 of active layer 108 is passivated by passivation layer 902.

[0109] Figures 10A to 10D This is a cross-sectional side view illustrating a method for forming an LED with a regenerated long sidewall passivation layer according to an embodiment. In the embodiment, Figures 10A to 10DThe method shown involves phosphorus-based LEDs (e.g., AlGaInP) designed to emit red light and having a cubic crystal structure. See also... Figure 10A The pn diode layer 115 is formed on the growth substrate 102, as described above. Figure 1A Similarly, the pn diode layer 115 is then wet chemically etched to form (111) sidewalls. See also... Figure 10B The mask layer 1010 used during wet chemical etching can be retained or removed before the passivation layer 1002 is epitaxially grown along the (111) sidewalls. In one embodiment, the passivation layer 1002 comprises GaN, which can be insulating compared to the pn diode layer 115. Alternatively, it can be p-type grown. Since the sidewalls have a (111) crystal orientation, they serve as suitable seed surfaces for the epitaxial growth of hexagonal AlGaN. This improves the quality of the regrown epitaxial interface to reduce surface recombination. In another embodiment, this structure can be formed entirely in situ, wherein the (111) sidewall mesa structure is formed by referencing Figures 9A to 9G The selective growth described above is used to form the structure, followed immediately by in-situ passivation via epitaxial growth of insulating or p-type GaN. (See reference...) Figures 10C to 10D Remove mask layer 1010, and refer to the above. Figures 1B to 1F The similar processing structure is used to form LED1050.

[0110] Figure 10E It is a cross-sectional side view of an LED with a regenerated long sidewall passivation layer according to the embodiment along the x-direction (111) plane. Figure 10F This is a cross-sectional side view of an LED with a regenerated long sidewall passivation layer according to the embodiment, along the y-direction (111) plane. Figures 10E to 10F As shown, a passivation layer 1002 is formed around the sidewall 153 of the pn diode layer (which also corresponds to the LED sidewall 151). Since the passivation layer 1002 is epitaxially grown, adhesion to the LED sidewall 151 is satisfied. This minimizes surface recombination. Furthermore, since the LED 1050 does not include an Al-containing layer in the pn diode layer 115, the pn diode layer 115 can be wet-etched and then transferred to a chamber for epitaxial growth without oxidation of the layers exposed after wet etching.

[0111] Figures 10G to 10H Similar to Figures 10E to 10F The difference lies in that the LED is patterned to include a wide top current extension layer 104. This allows the top conductive contact 104 to be larger, reducing the risk of direct contact through the passivation layer 1002.

[0112] Now refer to Figures 11A to 11DA cross-sectional side view illustration is provided for a method of forming an orientation-dependent doped LED pn junction according to an embodiment. Figure 11A This is a close-up cross-sectional view of a pn diode layer formed on a patterned substrate according to an embodiment, including an orientation-dependent doped layer. In the embodiment, Figures 11A to 11D The method shown involves a phosphorus-based LED designed to emit red light. For example... Figure 11A As shown, the growth substrate 1002, such as a (100) GaAs substrate, is formed using an etching step 1101. Then, a pn diode layer 1115 is epitaxially grown on the patterned growth substrate 1002. In an embodiment, the pn diode layer includes an n-AlInP current spreading layer 104, an n-AlInGaP:Se or Si cladding layer 106, an InGaP active layer 108, a p-AlInGaP:Mg cladding layer 1110A, a co-doped AlGaInP:Mg+Se cladding layer 1110B, a p-AlInGaP:Mg cladding layer 1110C, and a p-GaP current spreading layer 112.

[0113] Specifically, the specific method for forming cladding layers 1110A to 1110C, particularly cladding layer 1110B, implements the orientation dependence of n and p doping within cladding layer 1110B. Specifically, the n-type cladding layer 1110B is formed on a (100) flat surface, and the net p-type cladding layer 1110B is formed along a tilted region. Therefore, Se is oriented in (100) and bonded within the AlGaInP cladding layer 1110B, while Mg is preferentially oriented tilted within the AlGaInP cladding layer 1110B, thereby obtaining a pn diode layer 1115, wherein the pn junction is located on the tilted sidewall, and the npnp junction is formed on the (100) surface. Therefore, the current injection path preferentially (in Figure 11A (Indicated by arrows) flows through the pn junction formed on the sloping sidewalls. Now see Figures 11B to 11D The processing sequence is the same as the one mentioned above. Figures 1B to 1F The same principle applies to the formation of LED 1150.

[0114] Figures 11E to 11F This is a cross-sectional side view illustration of an LED pn junction with orientation-dependent doping according to an embodiment. (See illustration.) Figures 11E to 11F As shown, the pn junction and the current injection path (in) Figures 11E to 11F (Indicated by arrow) It is located internally within LED 1150 away from the edge of the active layer 108 along the sidewall 153 of the pn diode layer. Figure 11E In the embodiment shown, a portion of the growth substrate 102 remains within the resulting LED 1150. Figure 11FIn the embodiment shown, the thickness of the pn diode layer 1115 is sufficient to fill the internal portion of the LED 1150. For example, the current spreading layer 104 may fill the internal portion of the LED 1150.

[0115] Figures 12A to 12F This is a cross-sectional side view illustration of a method for forming an LED using selective etching and mass delivery according to an embodiment. See also... Figure 12A The pn diode layer 115 is formed on the growth substrate 102, as described above. Figure 1A Similarly, the pn diode layer 115 can be designed for emitting red, green, or blue light. However, the specific processing sequence may depend on whether the pn diode layer 115 is based on phosphorus or nitride.

[0116] See now Figure 12B Trench 118 is formed through pn diode layer 115 to form mesa structure 120, as described above. In an embodiment, pn diode layer 115 is phosphorus-based, and selective etching of InGaP active layer 108 is performed to create notches in the active layer, as... Figure 12C As shown. In this embodiment, the pn diode layer 115 is nitride-based, and photoactivated (e.g., between 365 and 450 nm) photoelectrochemical etching selectively removes a portion of the InGaN active layer 108 to create a notch. See now. Figure 12D Mass transport at high temperatures leads to mass transport of adjacent materials to form a new pn junction encapsulating the notch active layer 108. It is anticipated that mass transport may be possible to encapsulate the edge of the active layer 108 without first forming the notch. In a phosphorus-based embodiment of the pn diode layer 115, mass transport is caused by exposure to PH3+H2 at high temperatures. In such embodiments, adjacent p-AlInGaP cladding layers 110 and n-AlInGaP cladding layers 106 encapsulate the InGaP active layer 108. In a nitride-based embodiment of the pn diode layer 115, mass transport is caused by exposure to NH3+H2 at high temperatures. In such embodiments, adjacent p-GaN current spreading layers 112 and n-GaN current spreading layers 104 encapsulate the InGaN active layer 108. (Refer to...) Figures 12E to 12F Then you can refer to the above. Figures 1B to 1F The similarly processed structure is used to form LED 1250.

[0117] Figures 12G to 12H This is a cross-sectional side view of an LED including a notched active layer, according to the implementation scheme. (See diagram below.) Figure 12G As shown, adjacent p-AlInGaP cladding layers 110 and n-AlInGaP cladding layers 106 encapsulate the InGaP active layer 108. Figure 12H As shown, adjacent p-GaN current spreading layers 112 and n-GaN current spreading layers 104 encapsulate the InGaN active layer 108. In each embodiment, the edge 151 of the active layer 108 is internally confined within the LED 1250, inside the sidewall 153 of the pn diode layer.

[0118] Figures 13A to 13C This is a cross-sectional side view illustration of a method for passivating the sidewalls of an LED by surface transformation according to an implementation scheme. Figures 13A to 13B The structure of phosphorus-based pn diodes is basically similar to Figures 12A to 12B They differ slightly in composition. See also Figure 13C The active layer 108, and optionally cladding layers 106 and 110, comprise arsenic in their alloy. In an embodiment, aluminum may be additionally included in layers 106, 108, and 110 to restore the bandgap value. The mesa structure 120 is exposed to PH3+H2 vapor at high temperatures, which causes disharmony sublimation of group V species evaporating therein. The escaped As species are replaced by P, and the surface bandgap energy is increased. Therefore, the edge 151 of the active layer 108 becomes internally confined within the LED 1250, inside the sidewall 153 of the pn diode layer.

[0119] Figure 14A This is a cross-sectional side view illustration of an LED having quantum dots in the active layer according to an embodiment. In the embodiment, Figure 14A The structure shown relates to a phosphorus-based LED designed to emit red light. In one embodiment, the LED 1450 includes a quantum dot active region 1408, wherein injected charge carriers are localized at the quantum dot and are less likely to diffuse to the LED sidewalls 151. Figure 14B This is a schematic top view illustration of an LED active layer with quantum dots 1409 according to an embodiment. In this embodiment, cladding layer 1410 is formed of p-AlInP, cladding layer 1406 is formed of n-AlInP, and active layer 108 is formed of (Al)GaInP. During the formation of these layers, deposition is controlled such that compressive strain causes In to segregate into the In-rich regions. Deposition conditions can also be controlled to utilize miscibility gaps to form In-rich regions. Thus, In-rich quantum dot clusters with lower band gaps trap carriers and suppress lateral diffusion toward the LED sidewall 151. Detection of quantum dot clusters in the non-uniform active layer 108 can be achieved, for example, by photoluminescence. The exemplary quantum dot clusters 1409 depend on the lens scale forming the low band gap regions and can be approximately 10-20 nm in this embodiment.

[0120] Figures 15A to 15C This is a cross-sectional side view illustration of a method for forming an LED having nanopillars in the active layer according to an embodiment. In the embodiment, Figure 15A The structure shown relates to a nitride-based LED designed to emit green or blue light. In one embodiment, the pn diode layer 1515 includes an n-GaN current spreading layer 104, a p-AlGaN cladding layer 110, and a p-GaN current spreading layer 112. Multiple layers may form active layers. In one embodiment, the multiple active layers include InGaN. In one embodiment, the first In1GaN active layer 1508A includes multiple nanopillars 1509. The nanopillars 1509 can spontaneously form through compressive strain in the In1GaN active layer 1508A. In one embodiment, the nanopillars 1509 are formed by selective growth or patterning. After the formation of the first In1GaN active layer 1508A, a second In2GaN active layer 1508B is formed with a higher indium content than the first In1GaN active layer 1508A. Therefore, a higher concentration of indium can be located on the quantum dots or nanopillars 1509. Indium segregation can further increase the size of the nanopillars 1509. After the formation of the second In2GaN active layer 1508B, a third In3GaN active layer 1508C is grown over and buries the quantum dots or nanopillars 1509. In an embodiment, the indium content in the In3GaN active layer 1508C is less than the indium content in the In2GaN active layer 1508B, and can be the same as that in the In1GaN active layer 1508A. (Refer to...) Figures 15B to 15C This can be referenced in the text above. Figures 1B to 1F The same processing structure is used to form LED 1550. Figure 15D This is a cross-sectional side view illustration of an LED having nanopillars in the active layer according to the implementation scheme. Figure 15E This is a cross-sectional side view of an LED with a nanopillar and top cap configuration in an active layer according to an embodiment. As shown, a bottom p-doped current extension layer 112 is formed during pillar formation. In the illustrated embodiment, the LED 1550 includes quantum dots or nanopillars 1509 within an active region 1508, where injected carriers are localized and less likely to diffuse to the LED sidewall 151, which also corresponds to the pn diode layer sidewall 153.

[0121] Figures 16A to 16D This is a cross-sectional side view illustrating a method for forming an LED with heterogeneous structures hybridized at the sidewalls of the pn diode layer, according to an embodiment. In the embodiment, Figure 16A The structure shown relates to a phosphorus-based LED designed to emit red light, and may include components similar to those described above. Figure 1A The similar pn diode layer 115. See also... Figure 16AA mask 1601 is formed over the current spreading layer 112. A thermal process is then performed to result in diffusion or hybridization, depending on the material of the implanted mask 1601. In one embodiment, the implanted mask 1601 is formed of silicon. In such embodiments, silicon diffuses from the surface to form hybrid regions 1602. The diffusion of silicon results in group III vacancies, which allows group III atoms (Al, Ga, In) to exchange lattice positions on the group III sublattice to form homogeneous alloys on layers 106 (initially AlInGaP), 108 (initially InGaP), and 110 (initially AlGaInP). See also... Figure 16B After silicon diffusion, a masking Zn donor layer is optionally formed over the current spreading layer 112 and diffuses into the surface to form a p-doped layer 1603 on the surface, especially where silicon (n-doped) has diffused.

[0122] See now Figures 16C to 16D The trench 118 is etched through the pn diode layer 115, and the structure is the same as described above. Figures 1B to 11F The pattern is similarly used to form LED 1650. Figure 16E This is a cross-sectional side view of the hybrid LED heterostructure according to the embodiment. As shown, the hybrid region 1602 is formed adjacent to the active layer 108, such that the edge 151 of the active layer 108 is internally confined within the pn diode layer sidewall 153.

[0123] In another embodiment, the implantation mask 1601 is formed of SiO2, which implants group III vacancies into the underlying material. In this embodiment, Al, Ga, and In diffuse into the SiO2 to form a hybrid region 1602 where Al, Ga, and In are mixed. In this embodiment, since the n-dopant is not being diffused into the substrate, it may not be necessary to form a p-doped layer 1603.

[0124] exist Figure 16F In another embodiment shown, the implantation mask 1601 is formed of SiO2, and a Si-doped layer 1611 is formed near the one or more active layers 108. The Si-doped layer 1611 can be used to accelerate doping near the active layers 108.

[0125] According to the implementation scheme, the LED array can then be transferred from the carrier substrate to the receiving substrate, such as a lighting or display substrate. In the implementation scheme, the transfer can be achieved by selectively removing the sacrificial release layer, for example by vapor phase HF etching, and then electrostatically transferring the LED array using a transfer tool including an array of electrostatic transfer heads.

[0126] Figures 17A to 17F This is a cross-sectional side view illustrating a method for forming an LED with a sidewall passivation layer according to an embodiment. See also... Figure 17A The physical LED substrate 100 is shown, similar to the one described above. Figure 1A As previously described. Furthermore, a conductive oxide layer 160, such as ITO, may be formed over the pn diode layer 115. For example, the conductive oxide layer 160 may have an ohmic contact with the current spreading layer (e.g., 112) or overlay layer (e.g., 110) of the pn diode layer 115. The conductive oxide layer 160 and the pn diode layer 115 can then be patterned to form a trench 118, such as... Figure 17B As shown. After trench 118 is formed, the substrate can be adjusted. For example, this may include acid immersion to remove native oxides or residual contaminants from HCl or bromine-based mixtures. In-situ plasma treatment, such as using argon, hydrogen, or nitrogen, may then be optionally performed.

[0127] See now Figure 17C A sidewall passivation layer 170 is formed above and between the mesa structure 120. In an embodiment, the sidewall passivation layer 170 is formed using atomic layer deposition (ALD). For example, the sidewall passivation layer 170 can be Al2O3, but other materials can be used. In an embodiment, the sidewall passivation layer 170 is between 0 and 1,000 nm thick, such as 1 to 100 nm thick, and can have a uniform thickness conforming to the underlying substrate morphology, forming a contour around the mesa structure 120. The sidewall passivation layer 170 can then be patterned to form an opening 170 above the mesa structure 120, which exposes the patterned conductive oxide layer 160. For example, this can be achieved using a fluorine-based dry etching technique.

[0128] Bottom conductive contacts 116 can then be formed on the exposed portion of the conductive oxide layer 160 within the opening 172, as shown in 17D. See also Figure 17E A patterned sacrificial oxide layer 122 is formed and bonded to a carrier substrate 140 via an adhesive bonding material to form a stabilizing layer 130. After bonding to the carrier substrate 140, the growth substrate 102 can be removed using suitable techniques such as laser lift-off, etching, or grinding to expose the pn diode layer 115. Any remaining portions of the pn diode layers 115 connecting the separated mesa structures 120 can then be removed using etching or grinding to form laterally separated pn diode layers 115. A top conductive contact layer 142 can then be formed over each laterally separated pn diode layer to obtain an LED 150, such as... Figure 17F As shown, the ALD sidewall passivation layer 170 extends along the sidewall 153 of the pn diode layer 115 (including, for example, the top current spreading layer 104, the active layer 108, and the bottom current spreading layer 112) and across the conductive oxide layer 160.

[0129] Figures 18A to 18DThis is a cross-sectional side view illustration of a method for forming an LED with a heterogeneous structure hybridized at the sidewall of the pn diode layer, according to an embodiment. Specifically, Figures 18A to 18D The top-to-bottom diffusion method is shown. (Example) Figure 18A As shown, an LED substrate 100 is illustrated, which is consistent with the reference above. Figure 1A Similar to the previous description, an exemplary quantum well 107 and a quantum barrier layer 109 are illustrated within the active layer 108. While a single quantum well layer 107 is shown, this is exemplary, and multi-quantum well layer structures can be used. The bulk LED substrate 100 structure is adaptable to a variety of compositions and designed emission spectra. For example, the bulk LED substrate 100 may comprise II-VI materials, III-V nitride materials, or III-phosphide materials, and may be designed to emit multiple emission spectra. For example, the bulk LED substrate 100 may be fabricated using an AlInGaP material system or a ZnMgBeSSe material system. In a particular embodiment, the bulk LED substrate 100 is based on an AlInGaP material system and is designed for red light emission. For example, the bulk LED substrate 100 may be designed for peak emission wavelengths between 600 nm and 750 nm, such as 620 nm. Therefore, although the following structure is described with reference to an AlInGaP material system, the exemplary structure can be used for LEDs based on different material systems.

[0130] In this embodiment, the formation of the bulk LED substrate begins with the formation of a device layer 115 on a growth substrate 102, such as a GaAs growth substrate, having a thickness of 250–1,000 μm. The growth substrate 102 may optionally be doped, for example, with n-type dopant, such as silicon (Si) or tellurium (Te). Layers 104-112 of the device layer 115 can then be grown on the growth substrate 102 using a suitable technique such as metal-organic chemical vapor deposition (MOCVD). An n-type current spreading layer 104 is grown over the growth substrate 102, for example, to a thickness of 0.05–0.5 μm. The n-type current spreading layer 104 may be formed from materials such as AlInP, AlGaInP, and AlGaAs. In this embodiment, the n-type current spreading layer 104 is formed of AlInP with a Si dopant concentration of 1 × 10⁻⁶. 18 cm -3An n-side (top) cladding layer 106 is then grown on an n-type current-spreading layer 104, for example, to a thickness of 0.05-0.5 μm. The n-side cladding layer 106 may be formed of materials such as AlInP, AlGaInP, and AlGaAs, and may or may not be doped. In one embodiment, the n-side cladding layer 106 is formed of AlInGaP and is unintentionally doped during growth. In another embodiment, the n-side cladding layer 106 does not have a gradient composition (e.g., the aluminum content is uniform). An active region 108 is then grown on the n-side cladding layer 106. The active region 108 may include one or more quantum well (QW) layers 107 and quantum barrier layers 109, which may be formed of the same alloy system (e.g., an AlInGaP system) as the surrounding cladding layers 106, 110. The p-side (bottom) cladding layer 110 is then optionally grown on the active layer 108, for example, to a thickness of 0.05-0.5 μm, or more specifically, about 100 nm. The p-side cladding layer 110 can be formed of materials such as AlInP, AlGaInP, and AlGaAs, and may or may not be doped. In an embodiment, the p-side cladding layer 110 is formed of AlInGaP and is unintentionally doped during growth. A p-type (bottom) current spreading layer 112 can then be formed on the p-side cladding layer 110. The p-type current spreading layer 112 can be formed of materials such as AlInP, AlGaInP, and AlGaAs. In an embodiment, the p-type current spreading layer 112 is formed of AlInP with a Mg dopant concentration of 5 × 10⁻⁶. 17 cm -3 –1.5×10 18 cm -3 In one embodiment, the p-type current spreading layer 112 may have a substantially uniform p-doped concentration with a small concentration gradient due to diffusion with the surrounding layers. In another embodiment, the p-doped concentration is non-uniform.

[0131] According to an embodiment, the cladding layers 106, 110 can be formed of a material having a large conduction band offset relative to one or more quantum well layers 107 in the active layer 108. In this respect, the maximum conduction band offset of the quantum well confines electrons to the quantum well. According to an embodiment, the doped current spreading layers 104, 112 can be selected to have a high band gap in order to confine the injected carriers. For example, the doped current spreading layers 104, 112 can have a higher band gap energy than adjacent cladding layers. In an embodiment, the cladding layers 106, 110 are (Al) x Ga 1-x ) 0.5 In 0.5 P alloy, wherein 0.2 ≤ x ≤ 0.8, such as 0.5 ≤ x ≤ 0.8. In the embodiment, the doped current spreading layers 104, 112 are (Al)x Ga 1-x ) 0.5 In 0.5 P alloy, where 0.6≤x≤1.0.

[0132] Then, a doped well 1801 is formed in the bulk LED substrate, such as... Figure 18B As shown. In Figure 18B In the illustrated embodiment, the doped well extends through the one or more quantum wells 107 and quantum barrier layer 109 within the active layer 108. The doped well 1801 can be formed using techniques such as implantation, solid-state source diffusion, or vapor-phase diffusion. In an embodiment, the doped well 1801 is p-type and includes a dopant such as Zn or Mg, or more specifically, a dopant distribution of Zn. In an embodiment, the current spreading layer 112, and optionally the cladding layer 110, is p-type doped with p-dops such as Zn or Mg, or more specifically, Mg, during the growth of the pn diode layer 115. In-situ doping with Mg can be selected due to its correspondingly low activation energy and ability to generate free holes, while Zn can be selected for forming the doped well 1801 due to its higher diffusion capability.

[0133] According to the implementation scheme, an array of mesa trenches 118 can then be formed in the device layer to form an array of mesa structures 1820. As shown, the mesa trenches 118 can be formed through the dopant trap 1801 to create a doping-restricted region along the sidewall 153 of the mesa structure 1820. After forming the mesa trenches 118, the patterned bulk LED substrate can be processed similarly to those described above to form an array of LEDs 1850 that remain stable for pickup and transfer to a receiving substrate.

[0134] Figures 18E to 18F This is a cross-sectional side view of a hybrid LED heterostructure according to an embodiment. As shown, the hybrid region 1802 is formed adjacent to the active layer 108, such that the edge 151 of the active layer 108 is internally confined within the pn diode layer sidewall 153. Specifically, the hybrid region 1802 is formed within the original quantum well layer 107 and quantum barrier layer 109 that form the original active layer 108, wherein the diffusion distribution of the doped well 1801 overlaps the active layer 108. According to the embodiment, the hybrid region 1802 may be characterized by a larger bandgap than the original quantum well layer 107 due to diffusion between the quantum well layer 107 and the quantum barrier layer 109, and the resulting alloy hybridity. See also Figure 18FHybridization can lead to the transformation of multiple quantum well layers 107 and quantum barrier layers 109 to form a single hybrid region 1802 with a larger bandgap than the original quantum well layer 107. More specifically, dopants (e.g., Zn) in the doped well 1801 can facilitate diffusion from the original quantum barrier layer 109 into the quantum well layer 107 to form the hybrid region 1802, and / or In can diffuse from the quantum well layer 107 into the quantum barrier layer 109 to form the hybrid region 1802. Therefore, dopants in the doped well 1801 can facilitate alloying within the hybrid region 1802, which can increase the bandgap of the hybrid region 1802 relative to the quantum well layer 107 confined within the LED inside the hybrid region 1802. As described in further detail below, diffusion and alloying can be further promoted by controlling layer thickness, compositional differences, and strain.

[0135] In some embodiments, LED 1850 is a microLED with a maximum width between sidewalls 153 of 1-300 μm, 1-100 μm, or more specifically 1-20 μm, such as 10 μm or 5 μm, wherein the lateral dimension of the microLED can be close to the carrier diffusion length. In some embodiments, the edge 151 of the active layer 108 is internally confined within the pn diode layer sidewalls 153 for at least 200 nm. Therefore, the hybrid region 1802 can be at least 200 nm wide.

[0136] Figures 19A to 19D This is a cross-sectional side view illustration of a method for forming an LED with a heterogeneous structure hybridized at the sidewall of the pn diode layer, according to an embodiment. Specifically, Figures 19A to 19D It shows the relationship with Figures 6A to 6F Similar sidewall diffusion methods. For example... Figure 19A As shown, an LED substrate 100 is illustrated, which is consistent with the reference above. Figure 1A and Figure 18A Similar to the previous description, an exemplary quantum well layer 107 and a quantum barrier layer 109 are illustrated within the active layer 108.

[0137] See Figure 19B According to one embodiment, an array of mezzanine trenches 118 is formed in the device layer to form an array of mezzanine structures 1920. In one embodiment, the trenches 118 may be formed through the confinement layer 106 and partially or completely through the current spreading layer 104. Etching may be performed using suitable wet etching or dry etching techniques or combinations thereof, such as dry etching followed by a final wet etching to remove physical sidewall damage caused by dry etching. The mezzanine structure 1920 may be patterned using a mask layer 1910.

[0138] See now Figure 19CDopants are implanted or diffused into the exposed surfaces of the array of mesa structures 1950 and laterally into the device layers 115 between adjacent mesa structures. The doped regions 1901 can be n-type or p-type. In an embodiment, the doped regions 1901 are p-type, such as Mg or Zn. In an embodiment, p-type dopants are elements that produce high doping concentrations and relatively low mobility, such as Mg. After forming the doped regions 1901, the patterned bulk LED substrate can be processed similarly to those described above to form an array of LEDs 1950 that remain stable for pickup and transfer to a receiving substrate.

[0139] Figures 19E to 19F This is a cross-sectional side view of a hybrid LED heterostructure according to an embodiment. As shown, the hybrid region 1902 is formed adjacent to the active layer 108, such that the edge 151 of the active layer 108 is internally confined within the pn diode layer sidewall 153. Specifically, the hybrid region 1902 is formed within the original quantum well layer 107 and quantum barrier layer 109 that form the original active layer 108, wherein the diffusion distribution of the doped region 1901 overlaps the active layer 108. According to the embodiment, the hybrid region 1902 is characterized by a larger band gap than the original quantum well layer 107 due to diffusion between the quantum well layer 107 and the quantum barrier layer 109, and the resulting alloy hybridity. See also Figure 19F Hybridization can lead to the transformation of multiple quantum well layers 107 and quantum barrier layers 109 to form a single hybrid region 1902 with a larger bandgap than the original quantum well layer 107. More specifically, dopants (e.g., Mg) in the doped region 1901 can promote diffusion from the original quantum barrier layer 109 into the quantum well layer 107 to form the hybrid region 1902, and / or In can diffuse from the quantum well layer 107 into the quantum barrier layer 109 to form the hybrid region 1902. Therefore, dopants in the doped region 1901 can promote alloying within the hybrid region 1902, which can increase the bandgap of the hybrid region 1902 relative to the quantum well layer 107 confined inside the LED. As described in further detail below, diffusion and alloying can be further promoted by controlling layer thickness, compositional differences, and strain.

[0140] In some embodiments, LED 1950 is a microLED with a maximum width between sidewalls 153 of 1-300 μm, 1-100 μm, or more specifically 1-20 μm, such as 10 μm or 5 μm, wherein the lateral dimension of the microLED can be close to the carrier diffusion length. In some embodiments, the edge 151 of the active layer 108 is internally confined within the pn diode layer sidewalls 153 for at least 200 nm. Therefore, the hybrid region 1902 can be at least 200 nm wide.

[0141] In an embodiment, the LED (e.g., LED 1850, 1950, etc.) may include a pn diode layer comprising a top doped layer (e.g., 104 or 106) doped with a first dopant type (e.g., n-type) and a bottom doped layer (e.g., 1120 or 110) doped with a second dopant type opposite to the first type (e.g., p-type), but the doping types may be interchanged. An active layer 108 lies between the top and bottom doped layers, and a pn diode layer sidewall 153 spans the top doped layer, the active layer 108, and the bottom doped layer. Hybrid regions (e.g., 1802, 1902, etc.) may surround the active layer 108 within the pn diode layer sidewall. Similar hybrid regions may be additionally incorporated in the reference... Figures 6A to 6F and Figures 16A to 16F The processing sequences described and shown are generated.

[0142] The active layer 108 may include a plurality of quantum well layers 107 and a plurality of quantum blocking layers 109. Hybrid regions (e.g., 1802, 1902, etc.) may have a higher band gap than each of the plurality of quantum well layers 107. This may be attributed, for example, to the hybrid regions (e.g., 1802, 1902, etc.) having a higher Al concentration than each of the plurality of quantum well layers 107, and / or the hybrid regions (e.g., 1802, 1902, etc.) having a lower In concentration than each of the plurality of quantum well layers 107. Therefore, in an embodiment, the originally grown quantum well layer 107 becomes part of the inner quantum well layer 107 and the surrounding hybrid regions (e.g., 1802, 1902, etc.) after hybridization, and the hybrid regions (corresponding to the transformed portion of the originally grown quantum well layer) comprise more Al than the remaining inner quantum well layers 107 while the total Al content in the system is maintained. In an embodiment, the bottom doped layer is in situ doped with a second dopant type (e.g., p-type) dopant (e.g., Mg). The LED may also include a distribution of a second dopant of a second dopant type (e.g., Zn or Mg) across the sidewall 153 of the pn diode layer along the top doped layer, the active layer 108, and the bottom doped layer. In an embodiment, the Zn doping distribution is the result of a top-down diffusion method, while the Mg doping distribution is the result of a sidewall diffusion method, but the embodiment is not limited thereto.

[0143] According to the implementation scheme, hybridization within hybrid regions such as hybrid regions 1802 and 1902 can be promoted by designing the active layer 108, for example, by controlling the layer thickness, composition, and strain of the forming layer. Various implementation schemes that can promote hybridization are described below. In a structure designed for approximately 620 nm emission, relative to including an 8 nm thick (Al... 0.1 Ga 0.9 ) 0.5 In 0.5P quantum well layer 107 nm thick and 10 nm thick (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The baseline active layer structure of the quantum blocking layer 109 describes each embodiment. For example, an Al concentration of 0.7 can be expressed as the value at which the quantum blocking layer 109 achieves the maximum conduction-valence band shift. However, it should be understood that the following embodiments are also applicable to modified structures designed for emission at different wavelengths.

[0144] In one embodiment, the thickness of the one or more quantum well layers 107 is reduced to facilitate doping. A thinner quantum well layer 107 can experience greater energy movement for a given doping distance. A thinner quantum well layer 107 also allows for lower dopant concentrations in the doped wells 1801 and doped regions 1901. In one embodiment, the quantum well layers 107 are thinner than each of the quantum barrier layers 109. In another embodiment, each quantum well layer 107 has a thickness between 2-8 nm, or more specifically between 2-5 nm, such as 4 nm.

[0145] In this embodiment, the composition of the constituent layers of the active layer 108 is selected to promote hybridization. This compositional selection can also be combined with a reduction in the thickness of the quantum well layer 107. In this embodiment, the material system of the quantum barrier layer 109 and the active layer 107 is (Al... x Ga (1-x) ) y In (1-y) P. In the implementation scheme, increasing the difference in Al content between the quantum barrier layer 109 and the active layer 107 can promote Al diffusion and hybridization. For example, the Δx between the quantum barrier layer 109 and the active layer 107 can be greater than 0.6 or greater than 0.8.

[0146] The following example is a reference baseline (Al). 0.1 Ga 0.9 ) 0.5 In 0.5 P quantum well layer 107, and baseline (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The quantum barrier layer 109 is given. More generally, the quantum barrier layer 109 can have (Al) x Ga 1-x In 0.5 The composition of P is x = 0.5-0.8, or more specifically, x = 0.7 in the baseline quantum barrier layer 109. In an embodiment, the Al concentration in the quantum barrier layer 109 is increased. For example, the quantum barrier layer 109 may be (Al... x Ga 1-xIn 0.5 P, x = 0.6–1, or more specifically, x = 0.8–1 or x = 1. Similarly, the Al concentration in quantum well layer 107 can be reduced. In embodiments, quantum well layer 107 has an InGaP or InGaAsP composition and therefore does not contain Al (e.g., x = 0). Alternatively, Sb can completely or partially replace P. In such embodiments, reducing or removing Al increases the Ga concentration, while adding As decreases the P concentration; the effect of both is to reduce the band gap.

[0147] In one embodiment, the quantum well layer 107 is subjected to compressive strain. For example, a lattice mismatch between 0 and 2% can be generated between the quantum well layer 107 and the adjacent quantum barrier layer 109. According to one embodiment, the strain can be controlled at least partially by the composition. For example, increasing the In concentration can increase the lattice parameter of the quantum well layer 107. In one embodiment, the quantum barrier layer 109 has a thickness of (Al) 0.7 Ga 0.3 ) 0.5 In 0.5 The baseline composition of P, and for example, it can be 8 nm thick. In such embodiments, the indium concentration in the baseline quantum well layer 107 can be increased to (Al) 0.2 Ga 0.8 ) 0.4 In 0.6 This results in an increased lattice size, and the quantum barrier layer 109 compresses the quantum well layer 107. In such embodiments, In diffusion can function in the hybrid regions 1802 and 1902, where In from the active layer 107 diffuses into the quantum barrier layer 109, which has the effect of increasing the band gap in the hybrid regions 1802 and 1902. This can also have the effect of allowing a lower Al concentration gradient between the quantum well layer 107 and the quantum barrier layer 109.

[0148] In an embodiment, the quantum well layer 107 and the quantum barrier layer 109 can be strain balanced. For example, the quantum well layer 107 can be under compressive strain, while the quantum barrier layer 109 can be under tensile strain. In an embodiment, the net thickness of the active layer 108 is strain balanced. In an embodiment, the strain-balanced active layer 108 can include a larger Al concentration difference and In concentration difference compared to the baseline composition. For example, the In concentration difference can be greater than 0.1, such as 0.2. In an embodiment, the strain-balanced active layer 108 comprises (Al... 0.2 Ga 0.8 ) 0.4 In 0.6 P active layer 107 and (Al) 0.7 Ga 0.3 ) 0.6 In 0.4P quantum barrier layer 109. Therefore, an increased In concentration in the active layer 107 can increase the lattice size, while a decreased In concentration in the quantum barrier layer 109 can decrease the lattice size. A larger lattice active layer 107 can place the quantum barrier layer 109 under tension, while a smaller lattice size quantum barrier layer 109 can place the active layer 107 under compressive strain.

[0149] In the implementation, the active region is designed to reduce carrier mobility toward the sidewall 153 of the pn diode layer. Figure 20 This describes the in-plane band structure of GaInP quantum well layer material under unstrained, compressive, and tensile strain conditions, according to the implementation scheme. As shown in the figure, for unstrained Ga... 0.5 In 0.5 P, Indium-rich Ga under compressive strain 0.4 In 0.6 P, and indium-deficient Ga under tensile strain 0.6 In 0.4 The energy (E) of electrons (e), light holes (lh), and heavy holes (hh) in P is plotted against torque (k). In biaxial compression (Ga 0.4 In 0.6 In the case of P), the heavy hole valence band is the ground state and is deformed near the center of the region (k=0). In the case of biaxial stretching, the light hole (lh) valence band is the ground state and is relatively flat, which corresponds to a high effective mass. It is believed that the high effective mass of holes in the case of tensile strained quantum wells translates into low hole mobility and, correspondingly, reduced diffusion toward the LED sidewalls.

[0150] Figure 21 This is a cross-sectional side view of an LED 2150 heterostructure with a tensile strained and modulated doped quantum well active region according to an embodiment. Similar to the previously described structure, the LED heterostructure may include a current spreading layer 104 of a first dopant type (e.g., n-doped), a current spreading layer 112 of an opposite dopant type (e.g., p-doped), and an active layer 108 between the current spreading layers 104 and 112. Cladding layers 106 and 110 may optionally be formed on opposite sides of the active layer 108 to confine current within the active layer 108, and may have a larger bandgap than the active layer 108. Cladding layers 106 and 110 may be doped with dopants matching those of adjacent current spreading layers 104 and 112. In an embodiment, cladding layer 106 is doped with an n-type dopant, and cladding layer 110 is doped with a p-type dopant, or vice versa. According to an embodiment, the current spreading layer may be functionally similar to the cladding layer.

[0151] By way of example, in this embodiment, the LED heterostructure is designed to emit red light, and the material is phosphorus-based. The following list of materials used for red light emission is intended to be exemplary and not limiting. For example, the layers forming the pn diode may include AlInP, AlInGaP, AlGaAs, GaP, and GaAs. In this embodiment, the current spreading layer 104 comprises n-AlInP or n-AlGaInP, the cladding layer 106 comprises AlInGaP, the cladding layer 110 comprises AlGaInP, and the current spreading layer 112 comprises p-GaP or p-AlInP. The quantum well 108 may be formed of a variety of materials, such as, but not limited to, AlGaInP, AlGaAs, and InGaP.

[0152] In one embodiment, the active layer 108 includes a plurality of quantum well layers 107 and a quantum barrier layer 109. In another embodiment, the quantum barrier layer 109 is formed of the same material system as the cladding layers 106 and 110. For example, the quantum barrier layer 109 can be made of AlInGaP, such as (Al 0.7 Ga 0.3 ) 0.5 In 0.5 P is formed. The quantum barrier layer 109 can be modulated with doping, such as n-type doping, with suitable n-type dopant such as Si. For example, an exemplary doping concentration could be 1 × 10⁻⁶. 17 cm -3 –1×10 18 cm -3 The quantum well layer 107 can be strained, such as by tensile strain, as referenced. Figure 20 As described above. In this embodiment, the quantum well layer 107 is formed of InGaAlP, and the indium concentration is reduced. For example, the quantum well layer 107 may be In... x (Ga y Al 1-y ) 1-x P(x<0.5,y>0.9), such as Ga 0.6 In 0.4 P. According to the implementation scheme, x < 0.5 corresponds to a reduced indium concentration, where the lower limit of the reduction in indium concentration can be defined by the critical thickness of the layer.

[0153] According to the implementation scheme, it is believed that the n-type modulation doping of the quantum barrier layer 109 generates a high concentration of majority electrons in the quantum well layer 107. These electrons are available for recombination with injected holes, thereby increasing the radiative rate relative to the undoped quantum well layer 107. In the presence of majority electrons, radiative recombination is advantageous and carrier diffusion is restricted by hole transport. If the quantum well layer 107 is stretched and strained, the stretching strain makes holes less mobile and less likely to diffuse to the sidewalls. Therefore, the carrier diffusion length is reduced, and correspondingly, nonradiative sidewall recombination is also reduced. According to the implementation scheme, it is believed that both the n-type modulation and the stretched and strained quantum layer reduce nonradiative sidewall recombination individually and in combination. Therefore, these designs can be used together, as well as with other sidewall treatments described herein, for reducing nonradiative sidewall recombination.

[0154] Figure 22 This is a cross-sectional side view of an LED with a current-spreading layer pillar structure having a width reduced compared to the active layer, according to an embodiment. Similar to the previously described structure, the LED heterostructure may include a current-spreading layer 104 of a first dopant type (e.g., n-doped), a current-spreading layer 112 of an opposite dopant type (e.g., p-doped), and an active layer 108 between the current-spreading layers 104 and 112. Clad layers 106 and 110 may optionally be formed on opposite sides of the active layer 108 to confine current within the active layer 108, and may have a larger bandgap than the active layer 108. Clad layers 106 and 110 may be doped with dopants matching those of adjacent current-spreading layers 104 and 112. In an embodiment, cladding layer 106 is doped with an n-type dopant, and cladding layer 110 is doped with a p-type dopant, or vice versa.

[0155] By way of example, in this embodiment, the LED heterostructure is designed to emit blue or green light, and the material is nitride-based. The following list of materials used for blue or green light emission is intended to be exemplary and not limiting. For example, the layers forming the pn diode may include GaN, AlGaN, or InGaN. In this embodiment, the current spreading layer 104 comprises n-GaN, the cladding layer 106 comprises n-InGaN, the cladding layer 110 comprises p-AlGaN (e.g., Mg doped), and the current spreading layer 112 comprises p-GaN. The quantum well 108 may be formed of a variety of materials, such as, but not limited to, InGaN. In this embodiment, the active layer 108 comprises a plurality of quantum well layers 107 and a quantum blocking layer 109. In this embodiment, the quantum blocking layer 109 is formed of undoped GaN, and the quantum well layers are formed of InGaN.

[0156] exist Figure 22In the illustrated embodiment, the LED may include a centrally located pillar structure 220 with a width reduced compared to the active layer 108. The LED may optionally include a mesa structure comprising pillar structures 220 extending from mesa 222 and extending from the current spreading layer 104. Figure 22 As shown, the pillar structure 220 may include a current spreading layer 112 and a cladding layer 110. For example, the pillar structure 220 may extend completely through the cladding layer 110, as shown, or partially through the cladding layer 110. The pillar structure 220 can prevent nonradiative recombination along the sidewalls 253 of the LEDs laterally adjacent to the active layer 108, such as along the mesa structure 222.

[0157] According to the implementation plan, suitable etching techniques such as dry etching can be used to form the column structure 220 and the mesa structure 222. See now. Figure 23 A cross-sectional side view of an LED with a current-spreading layer pillar structure 220 and a recessed spacer 232 according to an embodiment is provided. It has been observed that dry etching can be accompanied by defects generated beneath the etched surface (such as surface 221 of the mesa structure 222 above quantum well layer 107). Such defects propagating into quantum well layer 107 can adversely affect device performance. It has also been observed that Mg doping within the cladding layer 110 experiences a surface riding effect due to the growth conditions of the cladding layer 110 during MOCVD, with the Mg doping concentration being highest at the top growth surface, corresponding to the surface adjacent to the current-spreading layer 112. In a particular embodiment, the Mg doping concentration within the p-AlGaN cladding layer 110 is highest adjacent to the interface with the p-GaN current-spreading layer 112. This Mg doping concentration within the cladding layer 110 can also have a significant relationship with the LED injection efficiency. Therefore, the Mg dopant concentration and proximity to the quantum well layer 107 can be tightly controlled parameters for device performance.

[0158] exist Figure 23 The illustrated embodiment shows an LED structure that separates the cladding layers 110 by a spacer 232, allowing the first cladding layer 110A to be formed to a thickness sufficient to absorb defects caused by dry etching of the pillar structure 220, while the second cladding layer 110B can be thin enough to keep the Mg doping concentration close to the quantum well layer 107, despite some observed surface riding effects. Additionally, the thicknesses of the first and second cladding layers 110A and 110B can each be kept below a critical thickness to avoid epitaxial film breakage. In this embodiment, the first cladding layer 110A is relatively thick, such as greater than 10 nm, or even greater than 50 nm, such as 50 to 100 nm thick. For example, the first cladding layer 110A can be formed of AlGaN, where the Al content is approximately 10%, and lightly doped with Mg (e.g., 1 × 10⁻⁶). 19 cm -3In addition to providing indentation for defects, the first cladding layer 110A can also act as an etch stop / end signal layer during the etching of the pillar structure 220.

[0159] In this embodiment, the spacer layer 232 is thin and lightly doped. For example, the spacer layer 232 may be approximately 5 mm thick to reduce current spread within the layer, and the light doping reduces conductivity. For example, the spacer layer 232 may be formed of p-GaN.

[0160] In this implementation, the second cladding layer 110B (which corresponds to the first grown cladding layer on the bulk LED substrate) can be relatively thin and more heavily doped than the first cladding layer 110A. For example, the second cladding layer 110B can be less than 50 nm thick, such as 5 to 10 nm thick, with a peak Mg doping concentration of at least 1 × 10⁻⁶. 19 cm -3 The second cladding layer 110B can be formed of p-AlGaN. In this configuration, the spacer 232 can break the Mg surface riding effect and is used to keep the peak Mg doping concentration close to the quantum well layer 107 within the second cladding layer 110B. The second cladding layer 110B can also act as an electron blocking layer.

[0161] After forming the column structure 220 and the mesa structure 222, the sidewall passivation layer 170 may optionally be formed along the exposed sidewalls. For example, the sidewall passivation layer 170 may be Al2O3, but other materials may be used. Similar to the structure described previously, Figures 22 to 23 The LED may include a top conductive contact 142 formed on the current spreading layer 104 and a bottom conductive contact formed on the current spreading layer 112. Additionally, Figures 22 to 23 The LED structure can be combined with other sidewall treatments described herein to reduce non-radiative sidewall combinations.

[0162] In the implementation plan, Figures 22 to 23 The maximum lateral dimension between the sidewalls of the LED is 1 to 300 μm, or more specifically 1 to 100 μm, 1 to 30 μm, 1 to 10 μm, or 1 to 5 μm. The maximum lateral dimension between the sidewalls of the mesa structure 222 can be 1 to 300 μm, or more specifically 1 to 100 μm, 1 to 30 μm, 1 to 10 μm, or 1 to 5 μm. In an embodiment, the width difference between the column structure 220 and the mesa structure 222 is less than 5 μm, such as approximately 2 μm on the laterally opposite sides, totaling 4 μm.

[0163] In one embodiment, the LED includes a mesa structure 222, which includes a first bottom cladding layer 110A, a spacer layer 232 above the first bottom cladding layer 110A, a second bottom cladding layer 110B above the spacer layer 232, an active layer 108 above the second cladding layer 110B, and a top cladding layer 106 above the active layer 108. A pillar structure 220 is located below the first bottom cladding layer 110A. In one embodiment, the pillar structure 220 is in direct contact with the first bottom cladding layer 110A, centrally positioned at the first bottom cladding layer 110A, and protrudes from the first bottom cladding layer 110A. In one embodiment, the first bottom cladding layer 110A is thicker than the second bottom cladding layer 110B, and the second bottom cladding layer 110B has a higher Mg doping concentration than the first bottom cladding layer 110A.

[0164] Figures 24A to 24C This is a cross-sectional side view illustration of a method for forming an LED with a plasma processing restricted area according to an embodiment. Figure 24A Is used for Figure 22 or Figure 23 The diagram illustrates a cross-sectional side view of a bulk LED substrate, similar to the one used for forming the LED. Multiple patterned mask layers 241 are then formed by a current spreading layer 112 to define the current injection region for the LED to be formed, followed by a plasma treatment such as N2 plasma. According to an embodiment, a nitrogen plasma treatment is performed to generate nitrogen vacancies (V0) in the p-doped layers (e.g., p-GaN current spreading layer 112 and p-AlGaN cladding layer 110). N This is used to generate current limiting.

[0165] Following plasma treatment, mesa trenches can be formed through the LED stack, and with reference... Figure 16C Similarly, a sidewall passivation layer 170 is then optionally formed. Figure 24C This is a cross-sectional side view of an LED structure including confinement regions 242 within the p-doped layer due to plasma treatment, wherein nitrogen vacancies in the confinement regions 242 insulate the LEDs and provide lateral confinement of the current. Similar to the previously described structure, Figure 24C The LED may include a top conductive contact 142 formed on the current spreading layer 104 and a bottom conductive contact formed on the current spreading layer 112. Additionally, Figure 24C The LED structure can be combined with other sidewall treatments described herein to reduce non-radiative sidewall combinations.

[0166] See now Figure 25AIn this embodiment, the array of LEDs 150 is transferred and bonded to the display substrate. Although LEDs 150 are shown, they are exemplary and any of the LEDs described above can be used. For example, the display substrate 300 can be a thin-film transistor (TFT) display substrate (i.e., a backplane) similar to those used in active-matrix OLED display panels. Figure 25A This is a side view illustration of a display panel according to an embodiment. In such embodiments, the display substrate is a TFT substrate including operating circuitry (e.g., transistors, capacitors, etc.) for independently driving each sub-pixel. The substrate 300 may include non-pixel regions and pixel regions (e.g., display regions), the pixel regions including sub-pixels arranged as pixels. The non-pixel regions may include data driving circuitry connected to each sub-pixel to enable the transmission of a data signal (Vdata) to the sub-pixel, scan driving circuitry connected to scan lines of the sub-pixel to enable the transmission of a scan signal (Vscan) to the sub-pixel, power supply lines for transmitting a power signal (Vdd) to the TFT, and termination lines or loops for transmitting termination signals (e.g., ground or some other low voltage (Vss) or reverse bias, power supply or some other high voltage level (Vdd), current source output or voltage source output) to the sub-pixel array. The data driving circuitry, scan driving circuitry, power supply lines, and termination lines or loops may all be connected to a flexible circuit board (FCB) including a power source for supplying power to the power supply lines and power source termination lines electrically connected to the termination lines or loops. It should be understood that this is one exemplary embodiment of the display panel, and alternative configurations are possible. For example, any of the driving circuitry may not be located on the display substrate 300, or alternatively may be located on the back surface of the display substrate 300. Similarly, the operating circuitry (e.g., transistors, capacitors, etc.) formed within the substrate 300 may be replaced by a micro-driver chip 350 bonded to the top surface of the substrate 300, such as... Figure 25B As shown.

[0167] exist Figure 25AIn the specific embodiment shown, the TFT substrate includes a switching transistor T1 connected to a data line from a driving circuit and a driving transistor T2 connected to a power line connected to a power supply line. The gate of the switching transistor T1 may also be connected to a scan line of the scan driving circuit. A patterned dam layer 326, including a dam opening 327, is formed over the substrate 300. In this embodiment, the dam opening 327 corresponds to a sub-pixel. The dam layer 326 can be formed using various techniques such as inkjet printing, screen printing, lamination, spin coating, CVD, and PVD, and can be formed from opaque, transparent, or translucent materials. In this embodiment, the dam layer 326 is formed from an insulating material. In this embodiment, the dam layer is formed from a black matrix material to absorb emitted light or ambient light. The thickness of the dam layer 326 and the width of the dam opening 327 may depend on the height of the LED 150 transferred and bonded within the opening, the height of the electrostatic transfer head, and the resolution of the display panel. In this embodiment, an exemplary thickness of the dam layer 326 is between 1 μm and 50 μm.

[0168] The conductive bottom electrode 342, the termination connection line 344, and the termination ring 316 may optionally be formed above the display substrate 300. In the illustrated embodiment, the termination connection line 344 is arranged between the dike openings 328 in the pixel region 304 of the display panel. The termination connection line 344 may be formed on the dike layer 326, or alternatively, the openings 332 may be formed in the dike layer 326 to expose the termination connection line 344 beneath the dike layer 326. In another embodiment, the termination connection line 344 is formed between the dike openings 327 in the pixel region and electrically connected to the termination ring 316 or termination line in the non-display region. This allows the termination signal to be applied more uniformly to the matrix of sub-pixels, resulting in more uniform brightness across the entire display panel.

[0169] The passivation layer 348 formed within the dam opening 327 surrounding the LED 150 performs functions such as preventing electrical short circuits between the top electrode layer 318 and the bottom electrode layer 342, and providing sufficient stepped coverage of the top electrode layer 318 between the top conductive contact 142 and the terminal connection line 344. The passivation layer 348 may also cover any portion of the bottom electrode layer 342 to prevent possible short circuits with the top electrode layer 318. According to embodiments, the passivation layer 348 may be formed from a variety of materials, such as, but not limited to, epoxy resins, acrylic (polyacrylate) such as poly(methyl methacrylate) (PMMA), benzocyclobutene (BCB), polyamides, and polyesters. In embodiments, the passivation layer 348 is formed by inkjet printing or screen printing around the LED device 156 to fill the sub-pixel region defined by the dam opening 327.

[0170] The top electrode layer 318 can be opaque, reflective, transparent, or translucent, depending on the specific application. In a top-emitting display panel, the top electrode layer 318 can be a transparent conductive material, such as amorphous silicon, a transparent conductive polymer, or a transparent conductive oxide. After forming the top electrode layer 318, an encapsulation layer 346 is formed over the substrate 300. For example, the encapsulation layer 346 can be a flexible encapsulation layer or a rigid layer.

[0171] In one embodiment, one or more LEDs 150 are arranged in a sub-pixel circuit. A first terminal of the LED 150 (e.g., a bottom conductive contact) is coupled to a driving transistor. For example, the LED 150 may be bonded to a pad coupled to the driving transistor. In another embodiment, a redundant pair of LEDs 150 is bonded to a bottom electrode 342 coupled to the driving transistor T2. The one or more LEDs 150 may be any of the LEDs described herein. A termination line is electrically coupled to a second terminal (e.g., a top conductive contact) of the one or more LEDs.

[0172] Current can be driven through the one or more LEDs, for example from the driving transistor T2. In a high-side driving configuration, the one or more LEDs can be on the drain side of a PMOS driving transistor or the source side of an NMOS driving transistor, such that the sub-pixel circuit drives current through the p-terminal of the LED. Alternatively, the sub-pixel circuit can be arranged in a low-side driving configuration, in which case the termination line becomes a power line and current is drawn through the n-terminal of the LED.

[0173] Figure 26 A display system 2600 according to an embodiment is shown. The display system includes a processor 2610, a data receiver 2620, a display 2630, and one or more display driver ICs 2640, which may be scan driver ICs and data driver ICs. The data receiver 2620 can be configured to receive data wirelessly or wiredly. Wireless can be implemented in any of a variety of wireless standards or protocols. The one or more display driver ICs 2640 can be physically and electrically coupled to the display 2630.

[0174] In some embodiments, display 2630 includes one or more LEDs formed according to the embodiments described above. Depending on its application, display system 2600 may include other components. These other components include, but are not limited to, memory, touchscreen controller, and battery. In various specific embodiments, display system 2600 may be a television, tablet computer, telephone, laptop computer, computer monitor, kiosk, digital camera, handheld game console, media display, e-book display, or large-area signage display.

[0175] Figure 27 A lighting system 2700 according to an embodiment is shown. The lighting system houses a power supply 2710, which may include a receiving interface 2720 for receiving power and a power control unit 2730 for controlling the power to be supplied to a light source 2740. Power may be supplied from outside the lighting system 2700 or from a battery optionally included in the lighting system 2700. In some embodiments, the light source 2740 includes one or more LEDs formed according to the embodiments described above. In various specific embodiments, the lighting system 2700 may be an internal or external lighting application, such as billboard lighting, building lighting, street lighting, light bulbs, and lamps.

[0176] When utilizing the various aspects of the embodiments, it will become apparent to those skilled in the art that combinations or variations of the above embodiments are possible for forming an LED. Although the embodiments have been described in language specific to structural features and / or methodological behavior, it should be understood that the appended claims are not necessarily limited to the specific features or behaviors described. Rather, the specific features and behaviors disclosed should be understood as embodiments used for illustrative purposes.

Claims

1. A light-emitting component, comprising: Display substrate; Light-emitting diodes (LEDs) are bonded to the display substrate, and the LEDs include: A top current spreading layer, wherein the top current spreading layer is N-doped; A semiconductor mesa structure, wherein the top current spreading layer of the semiconductor mesa structure protrudes, and the semiconductor mesa structure includes: Sidewall; The active layer spanning between the sidewalls; and Bottom surface; A passivation layer, the passivation layer being formed directly on the semiconductor mesa structure and spanning the sidewalls and the bottom surface of the semiconductor mesa structure, wherein the passivation layer is p-doped; and A conductive contact, which is located beneath the passivation layer.

2. The light-emitting component according to claim 1, wherein the conductive contacts comprise multiple layers stacked.

3. The light-emitting component according to claim 1, wherein the conductive contacts are bonded to the bottom electrode layer of the display substrate.

4. The light-emitting component according to claim 3, wherein the bottom electrode layer is connected to the sub-pixel circuit of the display substrate.

5. The light-emitting component according to claim 3, wherein the semiconductor mesa structure has a maximum width of less than 20µm.

6. The light-emitting component of claim 5, wherein the top current spreading layer comprises a material selected from the group consisting of n-AlInP and n-AlGaInP.

7. The light-emitting component according to claim 6, wherein the passivation layer comprises p-AlInP.

8. The light-emitting component of claim 7, wherein the active layer comprises a material selected from the group consisting of AlGaInP, AlGaAs, and InGaP.

9. The light-emitting component according to claim 7, wherein the active layer comprises AlGaInP.

10. The light-emitting component of claim 9, wherein the LED is embedded in a passivation layer surrounding the LED.

11. The light-emitting component of claim 10, wherein the LED further comprises a top conductive contact layer on the n-doped current spreading layer.

12. The light-emitting component of claim 11, further comprising a transparent top electrode layer above the top conductive contact layer of the LED and extending across the passivation layer.

13. The light-emitting component according to claim 9, wherein the semiconductor mesa structure has a maximum width of less than 5µm.

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