Isolated switching converter, controller and control method thereof

Abstract

The present invention discloses an isolated switching converter, a controller, and a control method thereof. The switching converter includes a transformer, a primary switching tube, and an isolation circuit. The control method includes: generating a first compensation signal based on the difference between an output feedback signal representing an output signal of the switching converter and a reference voltage; generating a first control signal and a second control signal based on the first compensation signal; sending the first control signal to a first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the first control signal; sending the second control signal to a second channel of the isolation circuit to generate a second synchronization signal electrically isolated from the second control signal; providing an upper threshold voltage above a first upper threshold when the switching converter has a peak power demand; providing a peak current signal based on the first and second synchronization signals and the upper threshold voltage; and shutting down the primary switching tube based on the current detection signal and the peak current signal.

Description

Technical Field

[0001] The present invention relates to an electronic circuit, and in particular to a quasi-resonant controlled isolated switching converter and a controller and a control method thereof. Background Art

[0002] Many loads, such as printers or scanners, have varying power requirements depending on the specific functions they perform. Most of these functions have low to medium power requirements, which existing isolated switching converters are capable of meeting and performing during normal operation. However, some functions, such as the paper scrolling function in a printer that requires a motor, have high or peak power requirements that exceed the range of an isolated switching converter for normal operation. Therefore, there is a need for an improved isolated switching converter, controller, and method thereof that can achieve normal operation during low to medium power periods while providing the maximum power possible to the load during high or peak power demand periods. Summary of the Invention

[0003] In response to one or more problems existing in the prior art, the object of the present invention is to provide an isolated switching converter and its controller and control method that can operate normally during medium and low power periods and provide the maximum power that can be expected to the load during high power or peak power demand periods.

[0004] According to an embodiment of the present invention, a controller for an isolated switching converter includes a transformer and a primary switch tube. The controller includes: an error amplification circuit, which receives an output feedback signal related to an output signal of the switching converter and generates a first compensation signal at an output end based on a difference between the output feedback signal and a reference voltage; a control signal generation circuit, which generates a first control signal and a second control signal at an output end based on the first compensation signal; an isolation circuit, which has a first channel for transmitting the first control signal and a second channel for transmitting the second control signal, and provides a first synchronization signal electrically isolated from the first control signal at a first output end and a second synchronization signal electrically isolated from the second control signal at a second output end; and an upper threshold generation circuit. An upper limit threshold voltage is provided at the output end, wherein the upper limit threshold voltage is adjusted to above a first upper limit threshold when a peak power demand occurs in the switching converter; a peak current generating circuit has a first input end, a second input end, a third input end and an output end, wherein the first input end receives a first synchronization signal, the second input end receives a second synchronization signal, and the third input end is coupled to the output end of the upper limit threshold generating circuit to receive the upper limit threshold voltage, and based on the first synchronization signal, the second synchronization signal and the upper limit threshold voltage, a peak current signal is provided at the output end; and a peak comparison circuit compares the current detection signal representing the current flowing through the primary switching tube with the peak current signal, and generates a shutdown control signal at the output end to control the shutdown of the primary switching tube.

[0005] An isolated switching converter according to an embodiment of the present invention includes the controller as described above.

[0006] According to an embodiment of the present invention, a control method for an isolated switching converter is provided. The switching converter includes a transformer, a primary switching tube, and an isolation circuit. The control method includes: generating an output feedback signal according to an output signal of the switching converter; generating a first compensation signal based on a difference between the output feedback signal and a first reference voltage; generating a first control signal and a second control signal based on the first compensation signal; sending the first control signal into a first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the first control signal; sending the second control signal into a second channel of the isolation circuit to generate a second synchronization signal electrically isolated from the second control signal; providing an upper threshold voltage above the first upper threshold when a peak power demand occurs in the switching converter; providing a peak current signal based on the first synchronization signal, the second synchronization signal, and the upper threshold voltage; and generating a shutdown control signal to shut down the primary switching tube based on a current detection signal representing a current flowing through the primary switching tube and the peak current signal.

[0007] In an embodiment of the present invention, two synchronous signals electrically isolated from the secondary side are received on the primary side via two channels of an isolation circuit. Based on these two synchronous signals, not only can the load on the secondary side be monitored for peak power demand, but the upper threshold voltage of the peak current signal can also be dynamically adjusted to meet the various functional requirements of the load. This embodiment of the present invention does not increase the cost or size of the isolating switch converter, while expanding the effective application range of the isolating switch converter. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a circuit block diagram of an isolated switching converter 100 according to an embodiment of the present invention;

[0009] Figure 2 According to an embodiment of the present invention Figure 1 The circuit schematic diagram of the error amplifier circuit 101 and the control signal generating circuit 102 is shown;

[0010] Figure 3 is a circuit schematic diagram of a peak current generating circuit 105 according to an embodiment of the present invention;

[0011] Figure 4 is a circuit schematic diagram of the upper threshold generating circuit 104 according to an embodiment of the present invention;

[0012] Figure 5 FIG. 3 is a flow chart of a method 300 for adjusting an upper threshold voltage according to an embodiment of the present invention.

[0013] Figure 6 is a circuit diagram of an upper threshold generating circuit 104A according to an embodiment of the present invention;

[0014] Figure 7 is a working waveform diagram of an isolated switching converter according to an embodiment of the present invention;

[0015] Figure 8 FIG. 7 is a flow chart of a control method 700 for an isolated switching converter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0016] Specific embodiments of the present invention will be described in detail below. It should be noted that the embodiments described herein are for illustrative purposes only and are not intended to limit the present invention. In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, it will be apparent to those skilled in the art that these specific details are not necessarily required to practice the present invention. In other instances, well-known circuits, materials, or methods are not specifically described to avoid obscuring the present invention.

[0017] Throughout this specification, references to "one embodiment," "an embodiment," "an example," or "an example" mean that a particular feature, structure, or characteristic described in connection with that embodiment or example is included in at least one embodiment of the present invention. Therefore, the phrases "in one embodiment," "in an embodiment," "an example," or "an example" appearing in various places throughout this specification do not necessarily all refer to the same embodiment or example. Furthermore, the particular features, structures, or characteristics may be combined in any suitable combinations and / or subcombinations in one or more embodiments or examples. Furthermore, those of ordinary skill in the art will appreciate that the figures provided herein are for illustrative purposes and are not necessarily drawn to scale. It should be understood that when an "element" is referred to as being "connected to" or "coupled to" another element, it can be directly connected or coupled to the other element or intervening elements may be present. In contrast, when an element is referred to as being "directly connected to" or "directly coupled to" another element, there are no intervening elements. Identical reference numerals indicate identical elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0018] The present invention can be applied to any isolated converter. In the following detailed description, for the sake of brevity, only a flyback converter is used as an example to explain the specific working principle of the present invention.

[0019] Figure 1 FIG. 1 is a circuit block diagram of an isolated switching converter 100 according to an embodiment of the present invention. Figure 1As shown, an isolated switching converter 100 includes a transformer T, a primary switch 10, a secondary switch MS, and a controller. Transformer T1 has a primary winding and a secondary winding, each of which has a first end and a second end. The first end of the primary winding receives an input voltage Vin, and the first end of the secondary winding provides a DC output voltage Vo, with the second end coupled to a secondary reference ground. Primary switch 10 is coupled between the second end of the primary winding and the primary reference ground. Secondary switch 20 is coupled between the second end of the secondary winding and a load. However, those skilled in the art will appreciate that secondary switch 20 can also be coupled between the first end of the secondary winding and the load.

[0020] exist Figure 1 In the illustrated embodiment, controller 30 of isolated switching converter 100 incorporates quasi-resonant control. In quasi-resonant control, the switching converter operates in a non-continuous current mode. When the current flowing through the energy storage element (transformer T) drops to zero, the parasitic capacitance of the energy storage element and the primary switch 10 begins to resonate, generating a resonant voltage waveform. When the resonant voltage across primary switch 10 is at its minimum, primary switch MP is turned on (commonly referred to as valley conduction), thereby reducing switching losses and electromagnetic interference (EMI) in switching converter 100.

[0021] The controller 30 includes an error amplifier circuit 101, a control signal generator circuit 102, an isolation circuit 103, an upper threshold generator circuit 104, a peak signal generator circuit 105, a peak comparison circuit 106, and a primary logic circuit 107. The control circuits on both the secondary and primary sides are integrated into the same chip. In some embodiments, the controller 30 is integrated into the same chip as the secondary switch 20 and provides a driver circuit for the secondary switch 20.

[0022] exist Figure 1 In the illustrated isolated switching converter 100 , the controller 30 has a plurality of pins, including an output feedback pin FB, a compensation pin COMP, a secondary reference ground pin SGND, a primary current sensing pin CS, a primary control pin PDrv, and a primary reference ground pin PGND.

[0023] The error amplifier circuit 101 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the output feedback pin FB to receive an output feedback signal VFB related to the output signal of the switching converter 100. The second input terminal receives a reference voltage VREF. The output terminal is coupled to the compensation pin COMP.

[0024] exist Figure 1In the illustrated embodiment, a resistor divider is coupled between the output voltage Vo and the controller's output feedback pin FB to sample the switching converter's output voltage Vo and provide an output feedback signal VFB. An error amplifier circuit 101 is coupled between the output feedback pin FB and the compensation pin COMP and generates a first compensation signal Vcomp at its output terminal based on the difference between the output feedback signal VFB and a reference voltage VREF. A control signal generation circuit 102 is coupled to the compensation pin COMP to receive the first compensation signal Vcomp. Based on the first compensation signal Vcomp, the control signal generation circuit 102 generates a first control signal PL1 and a second control signal PL2 at its output terminal, respectively, to control the first threshold voltage VTH and switching frequency of the primary switch 10.

[0025] Isolation circuit 103 has a first channel for transmitting a first control signal PL1 and a second channel for transmitting a second control signal PL2. It has a first input terminal for receiving the first control signal PL1 and provides a first synchronization signal SYNC1 electrically isolated from the first control signal PL1 at a first output terminal. It also has a second input terminal for receiving the second control signal PL2 and provides a second synchronization signal SYNC2 electrically isolated from the second control signal PL2 at a second output terminal. In one embodiment, isolation circuit 103 may include an optocoupler, a transformer, a capacitive isolation device, or any other suitable electrical isolation device. In other embodiments, isolation circuit 103 may be provided external to the controller integrated circuit.

[0026] like Figure 1 As shown, upper threshold generation circuit 104 has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the first output terminal of isolation circuit 103 to receive first synchronization signal SYNC1, and the second input terminal is coupled to the second output terminal of isolation circuit 103 to receive second synchronization signal SYNC2. Based on first synchronization signal SYNC1 and second synchronization signal SYNC2, upper threshold generation circuit 104 provides an upper threshold voltage VMAX at its output terminal. When switching converter 100 experiences peak power demand, upper threshold voltage VMAX is adjusted to above first upper threshold voltage VMX1.

[0027] The peak current generating circuit 105 has a first input terminal, a second input terminal, a third input terminal and an output terminal, wherein the first input terminal is coupled to the first output terminal of the isolation circuit 103 to receive the first synchronization signal SYNC1, the second input terminal is coupled to the second output terminal of the isolation circuit 103 to receive the second synchronization signal SYNC2, and the third input terminal is coupled to the output terminal of the upper threshold generating circuit 104 to receive the upper threshold voltage VMAX. Based on the first synchronization signal SYNC1, the second synchronization signal SYNC2 and the upper threshold voltage VMAX, a peak current signal VTH is provided at the output terminal.

[0028] In one embodiment, the controller 30 further includes a buffer circuit coupled between the output terminal of the upper threshold generating circuit 104 and the third input terminal of the peak current generating circuit 105 to isolate the upper threshold voltage VMAX.

[0029] Peak comparator circuit 106 has a first input, a second input, and an output. The first input is coupled to the primary current sense pin CS to receive a current sense signal VCS representing the current flowing through the primary switch. The second input is coupled to the output of peak current generator circuit 105 to receive a peak current signal VTH. Peak comparator circuit 106 compares current sense signal VCS with peak current signal VTH and provides a shutdown control signal RST at its output to control the shutdown of primary switch 10. Primary logic circuit 107 generates a primary control signal CTRLP at its output based on the second synchronization signal SYNC2 and the shutdown control signal RST. The primary control signal CTRLP is coupled to the control terminal of primary switch 10 via primary control pin PDrv to control the on / off switching of primary switch 10. In one embodiment, primary switch 10 is turned on when the second synchronization signal SYNC2 is active and the resonant voltage across primary switch 10 reaches its minimum value.

[0030] Figure 2 FIG. 1 is a circuit diagram of an error amplifier circuit 101 and a control signal generating circuit 102 according to an embodiment of the present invention. Figure 2 In the illustrated embodiment, the error amplifier circuit 101 includes an error amplifier EA having a non-inverting input terminal, an inverting input terminal, and an output terminal. The inverting input terminal receives an output feedback signal VFB, the non-inverting input terminal receives a reference voltage VREF, and the output terminal provides a first compensation signal Vcomp.

[0031] exist Figure 2 In the embodiment shown, the control signal generating circuit 102 includes a first control signal generating circuit 120 and a second control signal generating circuit 121. Figure 2 As shown, the first control signal generating circuit 120 includes a hysteresis compensation circuit 1201, a first comparison circuit 1202, and a first pulse circuit 1203. The hysteresis compensation circuit 1201 is coupled to the output terminal of the error amplifier circuit 101 to receive the first compensation signal Vcomp. Based on the first compensation signal Vcomp, the circuit provides a second compensation signal Vcomp1 at its output terminal. In one embodiment, the hysteresis compensation circuit 1201 is a superposition signal of the first compensation signal Vcomp and a hysteresis signal. In another embodiment, the second compensation signal Vcomp1 is proportional to the first compensation signal Vcomp, with a proportionality coefficient K1. In one embodiment, K1 is a number greater than 1.

[0032] The first comparison circuit 1202 is coupled to the output of the hysteresis compensation circuit 1201 to receive the second compensation signal Vcomp1, and to the output of the modulation signal generation circuit 1210 to receive the modulation signal VCT. The first comparison circuit 1202 compares the second compensation signal Vcomp1 with the modulation signal VCT and provides a first comparison signal CMP1 at its output. The first comparison circuit 1202A includes a comparator COM1. The comparator COM1 has a non-inverting input terminal that receives the second compensation signal Vcomp1, an inverting input terminal that is coupled to the first terminal of the capacitor CT to receive the modulation signal VCT, and an output terminal that provides the first comparison signal CMP1. The first pulse circuit 1203 receives the first comparison signal CMP1 and provides a pulsed first control signal PL1 at its output terminal. The first control signal PL1 is transmitted to the primary side through the first channel of the isolation circuit 103 to control the current threshold voltage VTH.

[0033] exist Figure 2 In the embodiment shown, the modulation signal generating circuit 1210 includes a voltage source VPK, a switch ST, a capacitor CT, and a resistor RT. Figure 2 As shown, voltage source VPK has a positive terminal and a negative terminal, with the negative terminal coupled to the secondary reference ground. Switching transistor ST has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the positive terminal of voltage source VPK, and the control terminal is connected to the second control signal PL2. Capacitor CT has a first terminal and a second terminal, with the first terminal coupled to the second terminal of switching transistor ST and the second terminal connected to the secondary reference ground. Resistor RT has a first terminal and a second terminal, with the first terminal coupled to the first terminal of capacitor CT and the second terminal connected to the secondary reference ground. A modulation signal VCT is generated at the first terminal of capacitor CT. When the second control signal PL2 is active, modulation signal VCT is pulled up to a peak voltage and then begins to decrease until the second control signal PL2 is again active.

[0034] exist Figure 2 In the illustrated embodiment, the second control signal generating circuit 121 includes a second comparison circuit 1211, a valley detection circuit 1212, a valley lock circuit 1213, and a second pulse circuit 1214. The second comparison circuit 1211 is coupled to the output terminal of the error amplifier circuit 101 to receive the first compensation signal Vcomp, and is coupled to the modulation signal generating circuit 1210 to receive the modulation signal VCT. The second comparison circuit 1211 compares the modulation signal VCT with the first compensation signal Vcomp, and generates a second comparison signal CMP2 at its output terminal. The second comparison circuit 1211A includes a comparator COM2. The comparator COM2 has a non-inverting input terminal that receives the first compensation signal Vcomp, an inverting input terminal that is coupled to the first terminal of the capacitor CT to receive the modulation signal VCT, and provides the second comparison signal CMP2 at its output terminal.

[0035] Valley detection circuit 1212 is used to detect the waveform of the secondary-side resonant voltage. In one embodiment, valley detection circuit 1212 is coupled to secondary switch 20 to detect the waveform of the resonant voltage and output a valley pulse signal VP representing the valley of the resonant voltage. In one embodiment, valley detection circuit 1212 detects whether the switching voltage across the secondary switch 20 is lower than a valley reference signal during the off-state period of the secondary switch 20 and outputs the valley pulse signal VP.

[0036] Valley lock circuit 1213 receives the first comparison signal CMP1, the second comparison signal CMP2, and the valley pulse signal VP, provides a target valley value at its output terminal for controlling the conduction of primary switch 10, and generates a frequency control signal FS corresponding to the target valley value. In one embodiment, valley lock circuit 1213 compares the valley value when modulation signal VCT reaches the second compensation signal Vcomp1 with the currently locked valley value, and determines whether to increase the target valley value based on the comparison result. It also compares the valley value when modulation signal VCT reaches the first compensation signal Vcomp with the currently locked valley value, and determines whether to decrease the target valley value based on the comparison result.

[0037] The second pulse circuit 1214 provides a second control signal PL2 in pulse form at the output end based on the frequency control signal FS, which is transmitted to the primary side through the second channel of the isolation circuit 103 to control the valley conduction and switching frequency of the primary switch tube 10.

[0038] Figure 3 FIG. 1 is a circuit diagram of a peak current generating circuit 105 according to an embodiment of the present invention. Figure 3 As shown, the peak current generating circuit 105 includes a first capacitor C1. Figure 3 As shown, when the rising edge of the second synchronization signal SNYC2 arrives, the voltage across the first capacitor C1 is set to the upper limit threshold voltage VMAX, and then the voltage across the first capacitor C1 begins to decrease at a certain time constant, and when the first synchronization signal SYNC1 arrives, the voltage across the first capacitor C1 is sampled and held to provide a peak current signal VTH.

[0039] exist Figure 3In the illustrated embodiment, the peak current generating circuit 105 further includes a timing circuit 1051, a flip-flop FF1, a voltage source VMIN, switches S1 and S2, a resistor R2, and a sample-and-hold circuit 1052. The timing circuit 1051 has an input and an output. The input is coupled to the second output of the isolation circuit 103 to receive the second synchronization signal SYNC2. The timing circuit 1051 performs timing based on the second synchronization signal SYNC2 and generates a timing signal DLY at the output. The flip-flop FF1 has a set terminal, a reset terminal, and an output terminal. The set terminal receives the second synchronization signal SYNC2, and the reset terminal is coupled to the output of the timing circuit 1051 to receive the timing signal DLY. The voltage source VMIN has a positive terminal and a negative terminal, the negative terminal of which is coupled to the primary reference ground. The switch S1 has a first terminal, a second terminal, and a control terminal. The first terminal is coupled to the first terminal of the first capacitor C1, the second terminal is coupled to the output of the upper threshold generation circuit 104 to receive the upper threshold voltage VMAX, and the control terminal is coupled to the output of the flip-flop FF1. The switch tube S2 has a first terminal, a second terminal and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor C1, the second terminal is coupled to the positive terminal of the voltage source VMIN via the resistor R2, and the control terminal is coupled to the inverting output terminal of the trigger FF1.

[0040] The sampling and holding circuit 1052 has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the first output terminal of the isolation circuit 103 to receive the first synchronization signal SYNC1, and the second input terminal is coupled to the first terminal of the first capacitor C1 to receive the voltage across the first capacitor C1. The sampling and holding circuit 1052 samples and holds the voltage across the first capacitor C1 based on the first synchronization signal SYNC1, and generates a peak current signal VTH at the output terminal.

[0041] Figure 4 FIG. 1 is a circuit diagram of an upper threshold value generating circuit 104 according to an embodiment of the present invention. Figure 4 In the illustrated embodiment, the transformer T of the switching converter further includes an auxiliary winding having a first terminal and a second terminal, wherein the second terminal of the auxiliary winding is coupled to the primary reference ground.

[0042] exist Figure 4 In the illustrated embodiment, the zero-crossing comparator circuit 109 is configured to detect whether the resonant voltage across the primary switch 10 has reached a minimum value, i.e., a valley. In one embodiment, the zero-crossing comparator circuit 109 compares the zero-crossing detection signal VZCD with a zero-crossing threshold voltage VZCD_TH and provides a zero-crossing signal ZCD1 at its output.

[0043] like Figure 4As shown, the upper threshold generation circuit 104 includes a first determination circuit 141, a second determination circuit 142, a peak power control circuit 143, and a threshold generation circuit 144. The first determination circuit 141 receives the first synchronization signal SYNC1 and the second synchronization signal SYNC2, and determines whether the interval between the first synchronization signal SYNC1 and the second synchronization signal SYNC2 is less than a first timing time, thereby generating a first determination signal JD1. The second determination circuit 142 receives the zero-crossing signal ZCD1 and, based on the zero-crossing signal ZCD1, determines whether the valley conduction of the primary switch 10 is locked at the first valley, thereby generating a second determination signal JD2. The peak power control circuit 143 receives the first determination signal JD1 and the second determination signal JD2, and, based on the first determination signal JD1 and the second determination signal JD2, generates an entry control signal ENT and an exit control signal EXT to the threshold generation circuit 144 to determine whether to enter or exit a state where the upper threshold voltage VMAX is above the first upper threshold voltage VMX1.

[0044] Figure 5 The flowchart of the method 300 for adjusting the upper threshold voltage according to one embodiment of the present invention is shown. The method 300 for adjusting the upper threshold voltage VMAX includes steps 301 to 306. In step 301, a first synchronization signal SYNC1 and a second synchronization signal SYNC2 are received on the primary side via an isolation circuit. In step 302, a detection is performed to determine whether the time interval between the first synchronization signal SYNC1 and the second synchronization signal SYNC2 is greater than a first timing time. If so, the process proceeds to step 304 to limit or adjust the upper threshold voltage VMAX below a first upper threshold VMX1. When the time interval between the first synchronization signal SYNC1 and the second synchronization signal SYNC2 is less than the first timing time, the upper threshold voltage VMAX is adjusted to equal the first upper threshold VMX1 (step 303). In step 305, a detection is performed to determine whether the valley conduction of the primary switch is at the first valley. If the valley conduction of the primary switch is detected at the first valley and the upper threshold voltage VMAX is equal to the first upper threshold VMX1, the process proceeds to step 306 to increase the upper threshold voltage VMAX above the first upper threshold VMX1. The process then returns to step 301 to continue the detection process.

[0045] Figure 6 FIG. 1 is a circuit diagram of an upper threshold value generating circuit 104A according to an embodiment of the present invention. Figure 6 In the illustrated embodiment, the upper threshold generating circuit 104A includes a first determination circuit 141A, a peak power control circuit 143A, and a threshold generating circuit 144A.

[0046] exist Figure 6In the illustrated embodiment, the first determination circuit 141A includes a timing circuit 1041, a flip-flop FF2, AND gates AND1 and AND2, and a flip-flop FF3. The first timing circuit has an input terminal and an output terminal, wherein the input terminal receives the second synchronization signal. The timing circuit 1041 performs timing based on the second synchronization signal SYNC2 and generates a timing signal DLY1 at the output terminal. The flip-flop FF2 has a set terminal, a reset terminal, and an output terminal, wherein the set terminal receives the second synchronization signal SYNC2, and the reset terminal is coupled to the output terminal of the timing circuit 1041 to receive the timing signal DLY1. In one embodiment, the first determination circuit 141A can omit the timing circuit 1041 and the flip-flop FF2 and directly multiplex them. Figure 3 The timing circuit 1051 and the trigger FF1 in.

[0047] AND gate AND1 has a first input terminal, a second input terminal, and an output terminal, wherein the first input terminal is coupled to the output terminal of flip-flop FF2, and the second input terminal receives the first synchronization signal SYNC1. AND gate AND2 has a first inverting input terminal, a second input terminal, and an output terminal, wherein the first inverting input terminal is coupled to the output terminal of flip-flop FF2, and the second input terminal receives the first synchronization signal SYNC1. Flip-flop FF3 has a set terminal, a reset terminal, and an output terminal, wherein the set terminal is coupled to the output terminal of AND gate AND1, and the reset terminal is coupled to the output terminal of AND gate AND2, and the first determination signal JD1 is provided at the output terminal.

[0048] Peak power control circuit 143A includes AND gates AND3 and AND gates AND4. AND gate AND3 has a first input, a second input, and an output. The first input is coupled to the output of first determination circuit 141A to receive first determination signal JD1, and the second input is coupled to the output of second determination circuit 142 to receive first determination signal JD2. AND gate AND3 provides an entry control signal ENT at its output. When entry control signal ENT is asserted, upper threshold voltage VMAX is controlled to increase, entering a state where upper threshold voltage VMAX is above first upper threshold voltage VMX1. AND gate AND4 has a first inverting input, a second input, and an output. The first inverting input receives first determination signal JD1, and the second input receives a state indication signal indicating that upper threshold voltage VMAX is greater than first upper threshold voltage VMX1. AND gate AND4 provides an exit control signal EXT at its output. When exit control signal EXT is asserted, upper threshold voltage VMAX is controlled to decrease, exiting a state where upper threshold voltage VMAX is above first upper threshold voltage VMX1.

[0049] exist Figure 6In the illustrated embodiment, the threshold generation circuit 144A includes a second capacitor C2, a second voltage source VMX1, a third voltage source VMX2, a first diode D1, a second diode D2, a charging control unit 1402, and a discharging control unit 1403. The second capacitor C2 has a first terminal and a second terminal, wherein the first terminal provides an upper threshold voltage VMAX and the second terminal is connected to the primary reference ground. The second voltage source VMX1 has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground. The third voltage source VMX2 has a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground. The first diode D1 has an anode and a cathode, wherein the anode is coupled to the positive terminal of the second voltage source VMX1 and the cathode is coupled to the first terminal of the second capacitor C2. The second diode D2 has an anode and a cathode, wherein the anode is coupled to the first terminal of the second capacitor C2 and the cathode is coupled to the positive terminal of the third voltage source VMX2. The charging control unit 1402 includes a charging current source IS1 and a control switch S3. Based on the input control signal ENT, the charging current source IS1 is used to charge the second capacitor C2. The discharge control unit 1403 includes a discharge current source IS2 and a control switch S4 . Based on the exit control signal EXT, the discharge current source IS2 is used to discharge the second capacitor C2 .

[0050] Figure 7 FIG. 1 is a working waveform diagram of an isolated switching converter according to an embodiment of the present invention. Figure 7 As shown, at time t1, when the second synchronization signal SYNC2 arrives, the voltage VC1 across capacitor C1 is increased to an upper threshold voltage VMX1. At time t2, when the second synchronization signal arrives and the resonant voltage of the primary switch reaches its minimum value, primary switch 10 is turned on. At time t3, the primary current sense signal VCS increases to the peak current signal VTH, and primary switch 10 is turned off.

[0051] At time t4 , when the first synchronization signal SYNC1 arrives, the voltage across the capacitor C1 is sampled, and the peak current signal VTH is increased, but still smaller than the first upper threshold voltage VMX1 .

[0052] At time t5, it is detected that the primary switch is conducting at its first valley, and the time interval between the first synchronization signal SYNC1 and the second synchronization signal SYNC2 is less than the first timing time. When the first synchronization signal SYNC1 arrives at time t5, the peak power control circuit 143 begins to increase the upper threshold voltage VMAX, causing the upper threshold voltage VMAX to be greater than the first upper threshold voltage VMX1.

[0053] At time t6, when the first synchronization signal SYNC1 arrives, the peak current signal VTH obtained by sampling and holding is greater than the first upper threshold voltage VMX1. At time t7, the time interval between the first synchronization signal SYNC1 and the second synchronization signal SYNC2 is detected to be greater than the first timing time, i.e., the first determination signal JD1 goes low, and the peak power control circuit 143 begins to reduce the upper threshold voltage VMAX, causing the upper threshold voltage VMAX to no longer be greater than the first upper threshold voltage VMX1. At time t8, when the first synchronization signal SYNC1 arrives, the peak current signal VTH obtained by sampling and holding is less than the first upper threshold voltage VMX1.

[0054] Figure 8 1 is a flow chart of a method 700 for controlling an isolated switching converter according to an embodiment of the present invention. The switching converter includes a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, a secondary switch coupled to the secondary winding, and an isolation circuit. The control method includes steps 701 to 708.

[0055] In step 701, the output signal of the switching converter is sampled to provide an output feedback signal.

[0056] In step 702 , a first compensation signal is generated based on a difference between the output feedback signal and a first reference voltage.

[0057] In step 703 , a first control signal and a second control signal are generated based on the first compensation signal.

[0058] In step 704, the first control signal is sent to the first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the first control signal.

[0059] In step 705, the second control signal is sent to the second channel of the isolation circuit to generate a second synchronization signal electrically isolated from the second control signal.

[0060] At step 706 , upon receiving a peak power demand, an upper threshold voltage above the first upper threshold is provided.

[0061] At step 707, a peak current signal is provided based on the first synchronization signal, the second synchronization signal, and the upper threshold voltage. In one embodiment, the method for generating the peak current signal includes: upon receipt of the second synchronization signal, raising the voltage across the first capacitor to the upper threshold voltage; gradually reducing the voltage across the first capacitor; and, upon receipt of the first synchronization signal, sampling and holding the voltage across the first capacitor to provide the peak current signal.

[0062] In step 708 , a shutdown control signal is generated to turn off the primary switch based on the current detection signal representing the current flowing through the primary switch and the peak current signal.

[0063] In one embodiment, the method for receiving a peak power demand includes: determining whether the interval between a first synchronization signal and a second synchronization signal is less than a first timing time, generating a first determination signal; determining whether the valley conduction of the primary switch tube is locked in the first valley, generating a second determination signal; and based on the first determination signal and the second determination signal, determining whether to enter or exit a state where the upper limit threshold is above the first upper limit threshold.

[0064] In another embodiment, the method for adjusting the upper limit threshold voltage includes: when the time interval between the first synchronization signal and the second synchronization signal is greater than the first timing time, adjusting the upper limit threshold voltage to be below the first upper limit threshold; when the time interval between the first synchronization signal and the second synchronization signal is less than the first timing time, adjusting the upper limit threshold voltage to be equal to the first upper limit threshold; and when the valley bottom conduction of the primary switch tube is locked in the first valley and the upper limit threshold voltage reaches the first upper limit threshold, increasing the upper limit threshold voltage to above the first upper limit threshold.

[0065] In one embodiment, the control method 700 further includes:

[0066] In the specification, relative terms such as first and second, etc. may be used only to distinguish one entity or action from another entity or action, and do not necessarily or imply any entity such relationship or order between these entities or actions. Numerical sequences such as "first", "second", "third", etc. refer only to different individuals in a plurality and do not imply any order or sequence unless specifically defined by the claim language. The order of the text in any claim does not mean that the processing steps must be performed in a temporary or logical order according to such order, unless specifically provided by the claim language. These processing steps can be interchanged in any order without departing from the scope of the invention, as long as such interchange does not contradict the claim language and does not appear logically absurd.

[0067] The above description and embodiments are merely exemplary and are not intended to limit the scope of the present invention. Variations and modifications to the disclosed embodiments are possible, and other feasible alternative embodiments and equivalent variations of the elements in the embodiments will be apparent to those skilled in the art. Other variations and modifications to the disclosed embodiments do not exceed the spirit and scope of the present invention.

Claims

1. A controller for an isolated switching converter, the switching converter comprising a transformer and a primary switch tube, the controller comprising: an error amplifier circuit, receiving an output feedback signal related to an output signal of the switching converter, and generating a first compensation signal at an output terminal based on a difference between the output feedback signal and a reference voltage; a control signal generating circuit, which generates a first control signal and a second control signal at an output end based on the first compensation signal; an isolation circuit having a first channel for transmitting a first control signal and a second channel for transmitting a second control signal, providing a first synchronization signal electrically isolated from the first control signal at a first output terminal, and providing a second synchronization signal electrically isolated from the second control signal at a second output terminal; an upper threshold generating circuit, providing an upper threshold voltage at an output terminal, wherein the upper threshold voltage is adjusted to be above a first upper threshold when a peak power demand occurs in the switching converter; The peak current generating circuit has a first input terminal, a second input terminal, a third input terminal, and an output terminal, wherein the first input terminal receives a first synchronization signal, the second input terminal receives a second synchronization signal, and the third input terminal is coupled to the output terminal of the upper threshold generating circuit to receive an upper threshold voltage. The peak current generating circuit provides a peak current signal at the output terminal based on the first synchronization signal, the second synchronization signal, and the upper threshold voltage. as well as The peak comparison circuit compares the current detection signal representing the current flowing through the primary switch tube with the peak current signal, and generates a shutdown control signal at the output end to control the shutdown of the primary switch tube.

2. The controller according to claim 1, wherein the upper threshold value generating circuit comprises: a first determination circuit for determining whether the interval between the first synchronization signal and the second synchronization signal is less than a first timing time, and generating a first determination signal; A second determination circuit determines whether the valley conduction of the primary switch tube is locked in the first valley, and generates a second determination signal; as well as The peak power control circuit generates an entry control signal and an exit control signal based on the first determination signal and the second determination signal to determine whether to enter or exit a state where the upper threshold voltage is above the first upper threshold.

3. The controller according to claim 2, wherein the upper threshold value generating circuit further comprises a threshold value generating circuit, the threshold value generating circuit comprising: a second capacitor having a first terminal and a second terminal, wherein the first terminal provides the upper threshold voltage and the second terminal is connected to the primary reference ground; a second voltage source having a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground; a third voltage source having a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground; a first diode having an anode and a cathode, wherein the anode is coupled to the positive terminal of the second voltage source and the cathode is coupled to the first terminal of the second capacitor; a second diode having an anode and a cathode, wherein the anode is coupled to the first terminal of the second capacitor and the cathode is coupled to the positive terminal of the third voltage source; a charging control unit, based on the incoming control signal, charging the second capacitor using a charging current source; as well as The discharge control unit discharges the second capacitor using a discharge current source based on the exit control signal.

4. The controller of claim 2 , wherein the first determination circuit further comprises: A first timing circuit has an input terminal and an output terminal, wherein the input terminal receives a second synchronization signal, the first timing circuit performs timing based on the second synchronization signal, and generates a timing signal at the output terminal; A first flip-flop having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the second synchronization signal, and the second input terminal is coupled to the output terminal of the timing circuit to receive the first timing signal; A first AND gate having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first trigger, and the second input terminal receives a first synchronization signal; A second AND gate having a first inverting input terminal, a second input terminal and an output terminal, wherein the first inverting input terminal is coupled to the output terminal of the first trigger, and the second input terminal receives the first synchronization signal; as well as The second trigger has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is coupled to the output terminal of the first AND gate, the second input terminal is coupled to the output terminal of the second AND gate, and the first determination signal is provided at the output terminal.

5. The controller as claimed in claim 1 , wherein the peak current generating circuit comprises a first capacitor, wherein when the second synchronization signal arrives, the voltage across the first capacitor is set to an upper threshold voltage, and then the voltage across the first capacitor gradually decreases, and when the first synchronization signal arrives, the voltage across the first capacitor is sampled and held to provide the peak current signal.

6. The controller of claim 5 , wherein the peak current generating circuit comprises: a second timing circuit having an input terminal and an output terminal, wherein the input terminal receives a second synchronization signal, the second timing circuit performs timing based on the second synchronization signal, and generates a second timing signal at the output terminal; a third flip-flop having a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives the second synchronization signal, and the second input terminal is coupled to the output terminal of the timing circuit to receive the timing signal; a first voltage source having a positive terminal and a negative terminal, wherein the negative terminal is coupled to the primary reference ground; a first switch tube having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor, the second terminal is coupled to the output terminal of the upper threshold generating circuit, and the control terminal is coupled to the output terminal of the third trigger; a second switch tube having a first terminal, a second terminal, and a control terminal, wherein the first terminal is coupled to the first terminal of the first capacitor, the second terminal is coupled to the positive terminal of the first voltage source via the first resistor, and the control terminal is coupled to the inverting output terminal of the third trigger; as well as The sampling and holding circuit has a first input terminal, a second input terminal and an output terminal, wherein the first input terminal receives a first synchronization signal, the second input terminal is coupled to the first terminal of the first capacitor to receive the voltage across the first capacitor, and the sampling and holding circuit samples and holds the voltage across the first capacitor based on the first synchronization signal, and generates a peak current signal at the output terminal. 7 . The controller according to claim 1 , further comprising a buffer circuit coupled between the output terminal of the upper threshold generating circuit and the third input terminal of the peak current generating circuit to isolate the upper threshold voltage.

8. An isolated switching converter comprising: a transformer having a primary winding and a secondary winding; A primary switch tube coupled to the primary winding; A secondary switch tube is coupled to the secondary winding; as well as A controller as claimed in any one of claims 1 to 7.

9. A control method for an isolated switching converter, the switching converter comprising a transformer having a primary winding and a secondary winding, a primary switch coupled to the primary winding, a secondary switch coupled to the secondary winding, and an isolation circuit, the control method comprising: generating an output feedback signal according to an output signal of the switching converter; generating a first compensation signal based on a difference between the output feedback signal and a first reference voltage; generating a first control signal and a second control signal based on the first compensation signal; Sending the first control signal to the first channel of the isolation circuit to generate a first synchronization signal electrically isolated from the first control signal; sending the second control signal into the second channel of the isolation circuit to generate a second synchronization signal electrically isolated from the second control signal; providing an upper threshold voltage above the first upper threshold when a peak power demand occurs in the switching converter; Providing a peak current signal based on the first synchronization signal, the second synchronization signal and the upper threshold voltage; as well as Based on the current detection signal representing the current flowing through the primary switch tube and the peak current signal, a shutdown control signal is generated to shut down the primary switch tube.

10. The control method according to claim 9, wherein the method of detecting the peak power demand comprises: determining whether an interval between the first synchronization signal and the second synchronization signal is less than a first timing time, and generating a first determination signal; determining whether the valley conduction of the primary switch tube is locked in the first valley, and generating a second determination signal; as well as Based on the first determination signal and the second determination signal, it is determined whether to enter or exit a state where the upper limit threshold is above the first upper limit threshold.

11. The control method according to claim 9, wherein the method of adjusting the upper threshold voltage comprises: When the time interval between the first synchronization signal and the second synchronization signal is greater than the first timing time, adjusting the upper threshold voltage to be below the first upper threshold; When the interval between the first synchronization signal and the second synchronization signal is less than the first timing time, adjusting the upper threshold voltage to be equal to the first upper threshold; as well as When the valley conduction of the primary switch tube is locked in the first valley and the upper threshold voltage reaches the first upper threshold, the upper threshold voltage is increased to above the first upper threshold.

12. The control method according to claim 9, wherein the method of generating the peak current signal comprises: When the second synchronization signal arrives, the voltage across the first capacitor is set to an upper threshold voltage; gradually reducing the voltage across the first capacitor; as well as When the first synchronization signal arrives, the voltage across the first capacitor is sampled and held to provide the peak current signal.

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