A cascaded multilevel rectifier topology and a control method thereof

Abstract

The application provides a cascade type multi-level rectifier topology and a control method thereof, a data model is established based on the topology, is discretized, a prediction model is formed, a reference voltage vector at a next moment is predicted, two basic voltage vectors closest to the reference voltage vector are selected by using a first value function, the action time of the two basic voltage vectors is calculated respectively, the action time is distributed to the corresponding basic voltage vectors, and double vector control is realized. The application can have the advantages of various topologies, has less current ripple, and has good control effect.

Description

Technical Field

[0001] This invention belongs to the field of power electronics technology, specifically relating to a cascaded multilevel rectifier topology and its control method. Background Technology

[0002] The statements in this section are merely background information related to the present invention and do not necessarily constitute prior art.

[0003] In recent years, with the development of solar energy, wind energy, and new energy vehicles, power electronic converters, as the bridge between the power grid and equipment, have faced higher requirements. Due to the limitations of IGBT voltage levels, traditional two-level rectifiers cannot meet the requirements of modern power electronic devices in terms of voltage levels and current harmonics. Therefore, developing a high-performance rectifier capable of withstanding higher voltages and lower harmonics is of great significance.

[0004] To overcome the shortcomings of traditional two-level rectifiers, some scholars have proposed multi-level rectifiers. Compared with traditional two-level rectifiers, multi-level rectifiers have significant advantages such as small size, low output voltage and current harmonics, high operating voltage and power, high device switching frequency, and low voltage stress, and therefore have been widely used.

[0005] However, multilevel rectifier circuits are relatively complex, with numerous power switching devices, posing certain challenges in control. Common control strategies for multilevel rectifiers include SPWM control, SVPWM control, and model predictive control. Model predictive control, as an advanced control method, can quickly track current changes and boasts advantages such as good dynamic performance and high robustness. However, achieving rapid current tracking increases the harmonics of the rectifier's AC current, resulting in less than ideal control performance. Summary of the Invention

[0006] To address the aforementioned problems, this invention proposes a cascaded multilevel rectifier topology and its control method. This invention combines the advantages of multiple topologies, resulting in less current ripple and better control performance.

[0007] According to some embodiments, the present invention adopts the following technical solution:

[0008] A cascaded multilevel rectifier topology includes three parallel bridge arms, each phase bridge arm including a cascaded H-bridge unit and a Vienna rectifier.

[0009] The H-bridge unit includes two two-level half-bridge units consisting of four switching transistors connected in series. The upper and lower midpoints of the H-bridge circuit are connected to the two ends of the flying capacitor. The midpoints of the two half-bridge units are respectively connected to the power grid and the Vienna rectifier in the next stage. The Vienna rectifier includes two diodes connected in series. One side of the midpoint of the two diodes is connected to two anti-series switching transistors, and the other side is connected to the H-bridge unit in the previous stage.

[0010] The parallel three-phase bridge arm DC output terminal has two capacitors of the same capacitance connected in series.

[0011] As an alternative implementation, the switching transistors at different positions of each phase bridge arm may employ power devices of different voltage levels or types.

[0012] Based on the above topology control method, a data model is established based on the topology and discretized to form a prediction model. The reference voltage vector at the next moment is predicted. The two basic voltage vectors closest to the reference voltage vector are selected using the first value function. The action time of the two basic voltage vectors is calculated respectively, and the action time is allocated to the corresponding basic voltage vector to realize dual vector control.

[0013] As an alternative implementation, the method further includes constructing a second value function to control the midpoint and flying capacitor voltages, and applying the switching state that minimizes the second value function to the control.

[0014] As an alternative implementation, the method further includes using a PI controller for DC-side voltage control.

[0015] As an alternative implementation method, the specific process of establishing a data model based on topology and discretizing it to form a prediction model includes:

[0016] Based on Kirchhoff's voltage law, a data model of the topology is constructed. The Clarke transform is used to convert the mathematical model in the abc coordinate system to the α-β coordinate system. The model is discretized by backward difference, and the discrete-time equation of the discretized model is pushed forward by one period.

[0017] As an alternative implementation, the first value function is a value function that controls the phase voltage at the input terminal of the rectifier.

[0018] As an alternative implementation method, a seven-level space voltage vector diagram is established, and sectors are divided according to the direction of the three-phase current.

[0019] A control device includes a processor and a computer-readable storage medium, the processor being configured to implement instructions; the computer-readable storage medium being configured to store a plurality of instructions adapted to be loaded by the processor and executed in accordance with the steps of the method.

[0020] A control system for a cascaded multilevel rectifier topology includes:

[0021] The DC-side voltage control module is configured to perform DC-side voltage control;

[0022] The AC side current control module is configured to establish a data model based on topology, and discretize it to form a prediction model. It predicts the reference voltage vector at the next moment, selects the two basic voltage vectors closest to the reference voltage vector using the first value function, calculates the action time of the two basic voltage vectors respectively, and allocates the action time to the corresponding basic voltage vector to realize dual vector control.

[0023] And a capacitor voltage balance control module, configured to perform capacitor voltage balance control.

[0024] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0025] (1) The present invention adopts a cascaded hybrid topology, which can combine the advantages of multiple topologies. The number of power switching devices is small, which can effectively reduce costs. Moreover, the driving signals of the switching devices are complementary or the same, which reduces the control complexity.

[0026] (2) The present invention has fewer switching devices through the current conduction path, resulting in low system conduction loss and redundant conduction path, which is beneficial to capacitor voltage balance control.

[0027] (3) The present invention adopts dual vector model predictive control, which has less current ripple and better control effect. Furthermore, the sector is divided in advance according to the current flow direction, and the number of vector positions in the αβ coordinate system participating in the value function calculation in each control cycle is reduced from 127 to 24, which greatly reduces the computational burden of the controller.

[0028] (4) The present invention realizes the balance control of the midpoint and flying capacitor voltage based on the value function. By setting different weight coefficients, different control effects can be applied to the flying capacitor voltage and the DC side capacitor voltage, thus making it more practical.

[0029] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0030] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0031] Figure 1 This is a schematic diagram of a cascaded seven-level rectifier topology according to an embodiment of the present invention.

[0032] Figure 2 This is a system overall control block diagram according to one embodiment of the present invention.

[0033] Figure 3 This is a seven-level space voltage vector diagram according to one embodiment of the present invention.

[0034] Figure 4 This is a sector distribution diagram of a seven-level rectifier according to an embodiment of the present invention.

[0035] Figure 5 This is a flowchart of a two-vector model predictive control according to an embodiment of the present invention.

[0036] Figure 6(a) is a simulation diagram of the phase voltage at the input terminal of phase a according to an embodiment of the present invention.

[0037] Figure 6(b) is a simulation diagram of the phase voltage at the b-phase input terminal according to an embodiment of the present invention.

[0038] Figure 6(c) is a simulation diagram of the phase voltage at the c-phase input terminal according to an embodiment of the present invention.

[0039] Figure 6(d) is a simulation diagram of the input line voltage according to an embodiment of the present invention.

[0040] Figure 6(e) is a simulation diagram of the three-phase input current according to an embodiment of the present invention.

[0041] Figure 6(f) is a simulation diagram of the DC-side output voltage according to an embodiment of the present invention.

[0042] Figure 6(g) is a simulation diagram of the flying capacitor voltage according to an embodiment of the present invention.

[0043] Figure 6(h) is a simulation diagram of the DC-side capacitor voltage according to an embodiment of the present invention.

[0044] Figure 6(i) is a simulation diagram of the input current FFT according to an embodiment of the present invention. Detailed Implementation

[0045] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0046] It should be noted that the following detailed description is illustrative and intended to provide further explanation of the invention. Unless otherwise specified, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains.

[0047] It should be noted that the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of exemplary embodiments according to the invention. As used herein, the singular form is intended to include the plural form as well, unless the context clearly indicates otherwise. Furthermore, it should be understood that when the terms "comprising" and / or "including" are used in this specification, they indicate the presence of features, steps, operations, devices, components, and / or combinations thereof.

[0048] It should be noted that, unless otherwise specified, the embodiments and features described in this invention can be combined with each other. The invention will now be described in detail with reference to the accompanying drawings and embodiments.

[0049] According to one embodiment of the present invention, a cascaded multilevel rectifier topology is provided. For example... Figure 1 As shown, taking phase a as an example, this hybrid topology consists of a cascaded H-bridge and a Vienna rectifier, S a1 -S a6 For six fully controlled switching devices, D a1 D a2 These are two diodes connected in series, acting as a clamping mechanism. C a For the flying capacitor of the H-bridge, C d1 C d2 These are two capacitors with the same capacitance value on the DC output side, used to equalize the voltage, i.e., U p =U n =U dc / 2. For the H-bridge unit, the upper and lower switching devices of each bridge arm are complementary in conduction, i.e., S a1 With S a2 S a3 With S a4 The drive signals are complementary, and by controlling the on / off state of the four switching devices, the H-bridge can generate -U af , 0, U af There are three voltage levels, therefore the H-bridge unit is a three-level topology. For Vienna rectifiers, the switching device S... a5 With S a6 With the same drive signal, the Vienna rectifier can generate -U by controlling the on / off state of the switching devices. dc / 2、0、U dc / 2 Three levels. Assume the DC-side output voltage U dc For 4E, the flying capacitor C of the H-bridge a The rated voltage is E, and the two capacitors on the DC side are C. d1 C d2The rated voltage is 2E. After cascading the front-stage H-bridge unit with the rear-stage Vienna rectifier, this topology can generate seven voltage levels at point a: +3E, +2E, +E, 0, -E, -2E, and -3E. Therefore, this cascaded topology is a seven-level rectifier. The seven voltage levels from -3E to 3E correspond to nine different conduction paths. When the voltage level at point a is +E or -E, it corresponds to two different conduction paths. Taking phase a as an example, Table 1 shows the switching sequences corresponding to different conduction paths and their impact on the flying capacitor current and the midpoint current.

[0050] Table 1. Switching sequences corresponding to the nine conduction paths of a seven-level rectifier and their impact on current.

[0051]

[0052] According to the present invention, a control method using the above-described topology is also provided.

[0053] Figure 2 The overall system control block diagram of the cascaded seven-level rectifier is given, which specifically includes DC side voltage control, AC side current control and capacitor voltage balance control.

[0054] In this control method, a PI controller is used in the outer voltage loop. The output of the PI controller, after dq transformation, serves as the reference current in the calculation of the prediction model. The output of the prediction model is used as the input of the value function g1. The value function g1 calculates the basic voltage vector closest to the reference voltage vector and the duration of action of the two basic voltage vectors. Finally, the capacitor voltage balance control is achieved by the value function g2, applying the switching state with the minimum value function to the rectifier.

[0055] According to a specific embodiment of the present invention, by Figure 1 A mathematical model of the seven-level rectifier topology is established and discretized to predict the reference voltage vector of the control target at time k+1.

[0056] Specifically, according to Kirchhoff's voltage law, the mathematical model of the rectifier is as follows:

[0057]

[0058] In the formula, U ao U bo U co i is the three-phase input phase voltage of the rectifier. a i b i c For three-phase input current, e a e b e c R represents the mains voltage, R represents the equivalent series resistance, and L represents the filter inductance.

[0059] Using the Clarke transformation, the mathematical model in the abc coordinate system is transformed into the α-β coordinate system:

[0060]

[0061] In the formula, U α U β i represents the components of the three-phase input voltage on the α and β axes. α i β e represents the components of the three-phase input current on the α and β axes. α e β These are the components of the grid voltage on the α and β axes.

[0062] The model is discretized using backward differencing, resulting in the following discretized mathematical model:

[0063]

[0064] In the formula, T s For the sampling period, U x (k) represents the current three-phase input voltage at time k, and i x (k) represents the current three-phase input current at time k, i x (k-1) represents the three-phase input current at the previous time k-1, e x (k) represents the grid voltage at the current time k, where x = α, β.

[0065] Since the time required for analog-to-digital converter and algorithm calculations introduces a delay, which affects the control accuracy of the rectifier, the discrete-time equations of the model need to be shifted forward by one cycle, i.e.:

[0066]

[0067] In the formula: Let e ​​be the three-phase reference input voltage at time k+1. x (k+1) Given a value at time k+1, it can be obtained using quadratic Lagrange interpolation:

[0068] e x (k+1)=3e x (k)-3e x (k-1)+e x (k-2)

[0069]

[0070] According to a specific embodiment of the present invention, the different flow directions of the three-phase currents a, b, and c can be used to... Figure 3The seven-level space vector diagram is divided into six sectors, and the distribution of the six sectors is as follows: Figure 4 As shown, each sector corresponds to 24 vector positions. Therefore, the number of vector positions involved in the value function calculation within each control cycle is 24, not 127. For ease of calculation, the current i in the α-β coordinate system can be used as a reference. α i β The sector where the reference voltage vector is located is determined, and the correspondence between the current and the sector is shown in Table 2.

[0071] Table 2. Correspondence between current and sector

[0072]

[0073] According to a specific embodiment of the present invention, the flowchart of the two-vector model predictive control can be found here. Figure 5 (It should be noted that,) Figure 5 This is merely one example of a specific implementation method. Figure 5 In order to achieve the optimal current tracking setpoint, the value function g1 can be defined as:

[0074]

[0075] The two fundamental voltage vectors U1(k+1) and U2(k+1) closest to the reference voltage vector can be obtained from the value function g1. The durations T1 and T2 of the two fundamental voltage vectors satisfy: T s =T1+T2

[0076] According to the volt-second balance principle:

[0077] U α (k+1)T s =U 1α (k+1)T1+U 2α (k+1)T2

[0078] U β (k+1)T s =U 1β (k+1)T1+U 2β (k+1)T2

[0079] Combine the above two equations and assume We can obtain:

[0080]

[0081] T2 = T s -T1

[0082] In the formula:

[0083] M = [U 1α(k+1)-U 2α (k+1)] 2 +[U 1β (k+1)-U 2β (k+1)] 2

[0084] Finally, time T1 is assigned to voltage vector U1(k+1), and T2 is assigned to voltage vector U2(k+1).

[0085] According to a specific embodiment of the present invention, the capacitor voltage is balanced and controlled based on a value function. Since the current i fx It will affect the voltage across the flying capacitor, and the current i mx This will affect the DC-side capacitor voltage. According to Table 1, the flying capacitor's charging and discharging can be controlled via paths a, c, d, f, g, and i, while the DC-side capacitor's charging and discharging can be controlled via paths d, e, and f. For any set of voltage vectors, the phase voltage at the input terminal may generate seven states: -3, -2, -1, 0, 1, 2, and 3, which correspond exactly to paths a, b, c, e, g, h, and i. When the conduction path is d or f, the corresponding current polarity is uncertain; it may be positive or negative. To facilitate the calculation of the value function, the state of path d is defined as -1.5, and the state of path f is defined as 1.5. In this case, there are a total of nine states, which correspond exactly to nine conduction paths.

[0086] To achieve capacitor voltage balance, the value function can be defined as:

[0087]

[0088] Where: m is the weighting coefficient of the H-bridge flying capacitor, h is the weighting coefficient of the DC-side capacitor, and T s For the sampling period, C dc For the DC side capacitor, i x Let x be the current in phase x (x = a, b, c).

[0089]

[0090] ΔU dc =U p -U n

[0091] U xf U is the voltage across the flying capacitor of the H-bridge in phase x (x = a, b, c). p U n These are the voltages of the upper and lower capacitors on the DC side, respectively.

[0092] sk x With sn xThese are the status flags for the flying capacitor voltage and the DC-side capacitor voltage, respectively, for sk x When the voltage vector state is -3, 1, or -1.5, the current flowing through the flying capacitor is -i. x At this point, take sk x =-1; When the voltage vector state is -1, 1.5, or 3, the current flowing through the flying capacitor is +i x Take sk x =1; When the voltage vector state is -2, 0, and 2, the current does not pass through the flying capacitor, take sk x =0. For sn x When the voltage vector state is -1.5, 0, and 1.5, it will affect the DC-side capacitor. In this case, sn is taken as... x =1; When the voltage vector is in other states, it will not affect the DC-side capacitor, so take sn. x =0.

[0093] Furthermore, due to the unique structure of the Vienna rectifier, the input voltage and current must be in phase; otherwise, current distortion will occur. Therefore, not all voltage vectors can be used. For example, the current directions of phases a, b, and c corresponding to sector I are +--, while the current directions of phases a, b, and c corresponding to voltage vector 322 in this sector are +++. Since the current directions are inconsistent, this voltage vector will cause current distortion and therefore cannot be used as a candidate vector in the value function calculation.

[0094] According to a specific embodiment of the present invention, the topology and control method of a seven-level rectifier were simulated. Figure 6 shows the waveform when the grid voltage is 110V under dual-vector model predictive control. Figures 6(a)-6(c) The waveforms of the three-phase input phase voltages verify that the rectifier proposed in this invention is a seven-level rectifier; in Figure 6(e), the input current has a high degree of sinusoidal rectifier; in Figure 6(f), the output voltage is stable at 200V, with fluctuations of approximately 0.3V (0.15%). Figure 6(g) and 6(h) In the middle, the flying capacitor voltage is maintained at 50V (U dc / 4), the DC-side capacitor voltage is maintained at 100V (U dc / 2), the current FFT analysis is shown in Figure 6(i). It can be seen that the total harmonic distortion rate is 2.94%, which is less than the standard of 5%. Therefore, it can be seen that the cascaded seven-level rectifier with dual-vector model predictive control can not only achieve capacitor voltage balance, but also effectively improve power quality.

[0095] In the description of this specification, the references to terms such as "one embodiment / mode," "some embodiments / modes," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment / mode or example is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments / modes or examples. Furthermore, without contradiction, those skilled in the art can combine and integrate the different embodiments / modes or examples described in this specification, as well as the features of different embodiments / modes or examples.

[0096] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0097] While the specific embodiments of the present invention have been described above in conjunction with the accompanying drawings, this is not intended to limit the scope of protection of the present invention. Those skilled in the art should understand that various modifications or variations that can be made by those skilled in the art without creative effort based on the technical solutions of the present invention are still within the scope of protection of the present invention.

Claims

1. A control method for a cascaded multilevel rectifier topology, characterized in that, A data model is established based on the topology and discretized to form a prediction model. The reference voltage vector at the next moment is predicted. The two basic voltage vectors closest to the reference voltage vector are selected using the first value function. The action time of the two basic voltage vectors is calculated and the action time is allocated to the corresponding basic voltage vectors to realize dual vector control. The method further includes constructing a second value function to control the midpoint and flying capacitor voltages, and applying the switching state with the minimum second value function to the control. The second value function is defined as follows: In the formula: m for H The weighting coefficient of the bridge-crossing capacitor. h This represents the weighting coefficient for the DC-side capacitor. The sampling period is For DC side capacitors, for x The current of the phase, where x = a , b , c ; for x Mutually H The voltage across the capacitor, where, x = a , b , c , , These are the voltages of the upper and lower capacitors on the DC side, respectively; and These are the status flag bits for the flying capacitor voltage and the DC-side capacitor voltage, respectively. When the voltage vector state is -3, 1, or -1.5, the current flowing through the flying capacitor is Take at this time =-1; When the voltage vector state is -1, 1.5, or 3, the current flowing through the flying capacitor is + ,Pick =1; When the voltage vector state is -2, 0, and 2, the current does not pass through the flying capacitor, take =0; for When the voltage vector state is -1.5, 0, and 1.5, it will affect the DC-side capacitor. At this time, take... =1; When the voltage vector is in other states, it will not affect the DC-side capacitor, so take... =0; The cascaded multilevel rectifier topology includes: Parallel three-phase bridge arms, each phase bridge arm includes cascaded... H Bridge unit and Vienna rectifier; The H The bridge unit consists of two two-level half-bridge units, each composed of four switching transistors connected in series. H The midpoints of the bridge circuit are connected to the two ends of the flying capacitor. The midpoints of the two half-bridge units are connected to the power grid and the Vienna rectifier in the next stage, respectively. The Vienna rectifier includes two diodes connected in series. One side of the midpoint of the two diodes is connected to two anti-series switching transistors, and the other side is connected to the previous stage. H Bridge unit connection; The parallel three-phase bridge arm DC output terminal has two capacitors of the same capacitance connected in series.

2. The control method as described in claim 1, characterized in that, The method also includes using PI The controller performs DC-side voltage control.

3. The control method as described in claim 1, characterized in that, The specific process of establishing a data model based on topology and discretizing it to form a prediction model includes: Based on Kirchhoff's voltage law, a data model of the topology is constructed, and then... Clarke Transformation, will abc Mathematical models in coordinate systems are converted to α-β In the coordinate system, backward difference is used to discretize the model, and the discrete-time equation of the discretized model is pushed forward by one period.

4. The control method as described in claim 1, 2, or 3, characterized in that, The first value function is the value function for controlling the phase voltage at the input terminal of the rectifier.

5. The control method as described in claim 4, characterized in that, Establish a seven-level space voltage vector diagram and divide the sector according to the direction of the three-phase current.

6. The control method for a cascaded multilevel rectifier topology as described in claim 1, characterized in that, The switching transistors at different positions in each phase bridge arm are power devices of different voltage levels or types.

7. A control device comprising a processor and a computer-readable storage medium, the processor being configured to implement instructions; the computer-readable storage medium being configured to store a plurality of instructions adapted to be loaded by the processor and executed as steps in a control method for a cascaded multilevel rectifier topology as described in any one of claims 1-6.

8. A control system for a cascaded multilevel rectifier topology employing the control method for a cascaded multilevel rectifier topology as described in any one of claims 1-6, characterized in that, include: The DC-side voltage control module is configured to perform DC-side voltage control; The AC side current control module is configured to establish a data model based on topology, and discretize it to form a prediction model. It predicts the reference voltage vector at the next moment, selects the two basic voltage vectors closest to the reference voltage vector using the first value function, calculates the action time of the two basic voltage vectors respectively, and allocates the action time to the corresponding basic voltage vector to realize dual vector control. And a capacitor voltage balance control module, configured to perform capacitor voltage balance control.

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