Frequency hopping filter and fast tuning method

Abstract

The present invention discloses a fast-tuning frequency-hopping filter, comprising a PIN diode switch capacitor matrix unit, a PIN diode drive unit, and a programmable logic gate array. The PIN diode switch capacitor matrix unit comprises a plurality of PIN diodes, the PIN diode drive unit comprises a plurality of drive circuits, and each drive circuit corresponds to a PIN diode. The drive circuit comprises NPN transistors Q1 and Q2, and a PNP transistor Q3. The timing of Q1 and Q2 is controlled respectively by the programmable logic gate array, thereby reducing the on-off delay between Q1, Q2, and Q3, achieving fast on-off, and thus reducing the tuning time of the frequency-hopping filter.

Description

Technical Field

[0001] The present invention relates to the field of electronic communications, and in particular to a fast tuning frequency hopping filter and method. Background Art

[0002] A frequency hopping filter is a tuned bandpass filter used in frequency hopping receivers and transmitters. It is a spread spectrum technology with the outstanding advantages of strong confidentiality and anti-interference capabilities. It is widely used in major frequency hopping communications such as countering enemy electronic interference, lateral positioning, interception and eavesdropping.

[0003] Today's increasingly dense and complex electromagnetic signals place increasing demands on the anti-interference capabilities of communication countermeasures equipment. Frequency-hopping radios, as a new generation of communication countermeasures, offer strong anti-interference and anti-interception capabilities, demonstrating their significant advantages in modern electronic warfare and communications. Frequency-hopping filters are a key component in the development of this new generation of communication countermeasures. They are placed before the receiver or transmitter power amplifier (high-power frequency-hopping filters are placed after the power amplifier) ​​to segment channels, prevent blocking, and suppress unwanted electromagnetic signals. The shorter the tuning time of a frequency-hopping filter, the lower the probability of interception and eavesdropping by the enemy, and the stronger its anti-interference capabilities. Tuning time is a crucial parameter for frequency-hopping filters.

[0004] The switch capacitor matrix is ​​the core component for achieving frequency hopping. The switch capacitor matrix is ​​generally composed of PIN diodes and capacitor groups. Because the reverse cutoff voltage of the PIN diode requires a DC high voltage of at least 100V, the power supply is complex, and high-voltage protection must be paid attention to during production, testing, and even use. The existing PIN diode drive circuit includes multiple transistors (BJT or MOS transistors) and multiple resistors. The switching on and off time of the PIN diode is affected by two main factors: the transition time of the transistor and the timing of the drive circuit. The technology used in existing products on the market makes it difficult to achieve a tuning time below 10 microseconds. The tuning time is directly related to the hopping speed.

[0005] At present, frequency hopping filters used in various communication products all use parallel multi-stage PIN diodes. By controlling the on-off time of each PIN diode, the capacitor in the bandpass filter is changed to achieve frequency adjustment. Therefore, the on-off time of the PIN diode directly determines the debugging time of the frequency hopping filter. The shorter the on-off response time of the PIN diode, the shorter the tuning time of the frequency hopping filter. However, the current frequency hopping filter generally has the problem of long tuning time and poor consistency. In order to solve the problem of long tuning time of frequency hopping filter, such as Figure 1 As shown, the common practice is to select transistors with shorter switching time (BJT or MOS tube) or choose different transistor circuit combinations. Although this can improve the situation, it cannot fundamentally reduce the on-off response time of the PIN diode. Summary of the Invention

[0006] The main purpose of the present invention is to reduce the tuning time of a frequency hopping filter and achieve fast tuning.

[0007] The technical solution adopted in the present invention is:

[0008] Provided is a fast-tuning frequency hopping filter, comprising a PIN diode switch capacitor matrix unit, a PIN diode drive unit, and a programmable logic gate array, wherein the PIN diode switch capacitor matrix unit comprises a plurality of PIN diodes, the PIN diode drive unit comprises a plurality of drive circuits, and each drive circuit corresponds to a PIN diode;

[0009] The drive circuit includes NPN transistors Q1 and Q2, and a PNP transistor Q3; wherein the base of Q1 is connected to an output control terminal of a programmable logic gate array via a drive resistor; the emitter of Q1 is grounded, and the collector of Q1 is connected to a DC high voltage via a current-limiting resistor; the base of Q2 is connected to another output control terminal of the programmable logic gate array via a drive resistor; the base of Q3 is connected to the collector of Q1, and the emitter is connected to the DC high voltage via a current-limiting resistor; the collector of Q3 is connected to the collector of Q2, and serves as the output terminal of the drive circuit and is connected to a corresponding PIN diode;

[0010] The timing of Q1 and Q2 is controlled separately through a programmable logic gate array to reduce the on-off delay between Q1, Q2, and Q3.

[0011] Following the above technical solution, a voltage dividing resistor is further provided between the collectors of Q1 and Q3.

[0012] According to the above technical solution, the DC high voltage is 80V~400V.

[0013] Following the above technical solution, the programmable logic gate array is CPLD or FPGA.

[0014] According to the above technical solution, when one output control terminal of the programmable logic gate array is at a high level and the other output control terminal is at a low level, Q1 is turned on and Q2 is turned off, thereby Q3 is turned on, and the output end of the driving circuit outputs a high voltage; conversely, Q1 is turned off and Q2 is turned on, thereby Q3 is turned off, and the output end of the driving circuit outputs a low voltage.

[0015] According to the above technical solution, the high level is 3.3V or 5V, and the low level is 0~0.5V.

[0016] According to the above technical solution, Q1 and Q2 are N-channel MOS transistors or NPN BJT transistors, and Q3 is a P-channel MOS transistor or PNP BJT transistor.

[0017] The present invention also provides a method for fast tuning of a frequency hopping filter. This method is based on the fast tuning frequency hopping filter of the above technical solution, and controls the timing of the base extreme levels of Q1 and Q2 respectively through a programmable logic gate array, thereby reducing the on-off delay between Q1, Q2, and Q3.

[0018] When the driving circuit outputs high voltage, it first assigns a high level to the base terminal of Q1 through an output control terminal of the programmable logic gate array, and delays for a certain time, and then assigns a low level to the base terminal of Q2 through another output control terminal of an output control terminal of the programmable logic gate array, Q1 is turned on, Q2 is turned off, and Q3 is turned on;

[0019] When the driving circuit outputs a low voltage, a high level is assigned to the base terminal of Q2 through the programmable logic gate array, and after a preset delay, the base terminal of Q1 is assigned a low level. Then, Q1, Q2, and Q3 are turned on and off respectively according to a certain timing, so that the on-off time of Q3 is only the transition time of the PN junction.

[0020] Following the above technical solution, the delay of Q1 is 15~30us, and the delay of Q2 is 10~30us.

[0021] According to the above technical solution, the time delay of Q3 turning on or off is 1 to 5 μs.

[0022] The beneficial effects of the present invention are as follows: the frequency hopping filter of the present invention replaces the transistor connected between the existing drive circuit and the DC high voltage with a PNP transistor or a P-channel MOS transistor, and replaces the other two transistors with NPN transistors or N-channel MOS transistors, and assigns them a high level or a low level respectively, and adjusts the timing of the PIN diode drive circuit by a digital delay method to achieve fast switching, thereby reducing the tuning time of the frequency hopping filter. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments, in which:

[0024] Figure 1 It is a schematic diagram of a driving circuit of a frequency hopping filter in the prior art;

[0025] Figure 2 is a schematic structural diagram of a frequency hopping filter according to an embodiment of the present invention;

[0026] Figure 3 1 is a schematic diagram of a driving circuit of a frequency hopping filter according to an embodiment of the present invention;

[0027] Figure 4 This is a schematic diagram of a PIN diode drive logic control circuit according to an embodiment of the present invention;

[0028] Figure 5This is the timing diagram of the PIN drive circuit without controlled delay;

[0029] Figure 6 This is the timing diagram of the PIN drive circuit that controls the delay. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the present invention more clearly understood, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present invention and are not intended to limit the present invention.

[0031] Frequency hopping filters are mainly used in various frequency hopping communication systems. The center frequency of the corresponding frequency hopping filter in the system can be quickly changed according to the system requirements. The two main functions of the frequency hopping filter are bandpass filtering and center frequency. The performance of the frequency hopping filter is mainly determined by the filtering performance and the hopping speed (the inverse of the tuning time). Figure 2 As shown, the frequency hopping filter generally includes the following main functional modules: impedance matching and frequency band switching unit, resonance unit, coupling unit, PIN diode switch capacitor matrix unit, digital control interface and power supply unit.

[0032] The resonant unit is the fundamental unit for filtering. Depending on the power level or frequency, different filtering solutions are selected. Generally, an LC filter or a coaxial cavity filter, or both, is used in a single product. An LC filter is a filter composed of a capacitor and an inductor with concentrated parameters connected in parallel and series. A coaxial cavity filter is composed of a series of coupled metal resonant columns. A resonant column is a metal column with one end grounded and the other end loaded with a capacitor. The filter's input and output are formed by metal wires connecting the resonant columns.

[0033] Since the transition time of the transistor is in the nanosecond order and is almost negligible, the frequency hopping filter of the present invention adjusts the timing of the PIN diode drive circuit by digital delay to achieve fast switching, thereby reducing the tuning time of the frequency hopping filter.

[0034] The signal flow of the frequency hopping filter of the present invention is as follows Figure 2As shown, the input signal is fed into the frequency hopping filter via an RF connector with a 50 ohm input impedance. The 50 ohm RF connector is connected to an impedance matching network. The matching network matches the input signal's impedance to 50 ohms to ensure the RF signal's port standing wave ratio is no less than 2, thereby reducing signal loss and improving signal transmission quality. The signal passing through the matching network is then connected to a frequency band switching unit, which consists of a single-pole, multi-throw (SPMT) RF switch. This RF switch divides the operating frequency band into several sub-bands for separate operation. The RF switch is selected based on the bandwidth of the frequency hopping filter. Because frequency hopping filters have a wide operating bandwidth, they are typically divided into several sub-bands (2, 3, or 4). For example, if the design is divided into two sub-bands, a single-pole, double-throw (SPDT) RF switch is recommended; if the design is divided into three sub-bands, a single-pole, three-throw (SPTT) RF switch is recommended, and so on. If a broadband device can be found that can also be designed for a single frequency band, then a SPMT RF switch is not necessary to divide the operating frequency band into sub-bands. The main performance parameters of RF switches are insertion loss and isolation. The current RF switch insertion loss is above 0.3dB and the isolation is below 35dB.

[0035] After passing through the frequency band switching unit, the signal is connected to the basic filter unit consisting of a resonant unit and a coupling unit. Different basic filter units are designed according to the number and frequency of sub-bands, with each sub-band corresponding to a basic filter unit. Generally, the filter unit for low-frequency sub-bands (below 1 GHz) uses an LC filter solution, while the filter unit for high-frequency sub-bands (1 GHz to 3 GHz) uses a coaxial cavity filter solution. The basic filter unit is a fixed-bandwidth filter designed with the sub-band reference frequency as a reference. One end of the tap of the inductor (transformer or resonant column) in the basic filter unit is connected to the output impedance matching and frequency switching unit, and the other end is connected to the PIN switch capacitor matrix unit. After the basic filter unit is loaded with the switch capacitor matrix, frequency hopping can be performed within the designed sub-band.

[0036] The signal is filtered by the resonance unit, coupling unit, and PIN switch capacitor matrix, enters the impedance matching and frequency switching unit at the output end, and is then output through the output RF connector.

[0037] The digital control interface and power supply unit primarily provide external control and power for the frequency-hopping filter. The control interface typically employs an 8-bit or 10-bit parallel interface, providing address and data bits for the module. An SPI interface can also be used. The data bit interface primarily uses high and low voltage levels to control the on / off state of the capacitor matrix to achieve different capacitor combinations. These different capacitor combinations, combined with the resonator, form a frequency-hopping bandpass filter. For example, 8 data bits, calculated in binary, can control 256 frequency points.

[0038] The PIN diode driving unit and the digital control interface unit are connected to the PIN diode switch capacitor matrix unit through a parallel interface, and the conduction and shutdown of the PIN diode are controlled by the high and low level changes of the parallel port.

[0039] The PIN diode driving unit includes a plurality of driving circuits, which are Figure 4 The programmable logic gate array U1 shown in the figure controls the timing. One PIN diode corresponds to one drive circuit, as shown in Figure 3 As shown, for example, the first PIN diode is driven by the first drive circuit, which includes four resistors, R1, R2, R3, R4, and R5, and three transistors, Q1, Q2, and Q3. In this embodiment, R1 is 100 to 470 ohms, R2 is 220 to 510 kiloohms, R3 is 1 to 2 kiloohms, and R4 and R5 are 1 to 5.1 kiloohms. Q1 and Q2 are NPN transistors (such as NPN-type BJT transistors) or N-channel MOS transistors, and Q3 is a PNP transistor (such as NPN-type BJT transistors) or a P-channel MOS transistor. The base of Q1 is connected to an output control terminal of the programmable logic gate array through a driving resistor; the emitter of Q1 is grounded, and the collector of Q1 is connected to the DC high voltage through a current limiting resistor; the base of Q2 is connected to the other output control terminal of the programmable logic gate array through a driving resistor; the base of Q3 is connected to the collector of Q1, and the emitter is connected to the DC high voltage through a current limiting resistor. The collector of Q3 is connected to the collector of Q2, and serves as the output terminal of the driving circuit and is connected to the PIN diode.

[0040] like Figure 3 As shown, VBB is a DC high voltage of 80V to 400V. When the control voltage CTR11 is high (3.3V or 5V) and CTR12 is low (0 to 0.5V), transistor Q1 is turned on and Q2 is turned off, thereby turning on Q3, and VH_OUT outputs a high voltage (80V-400V). Conversely, when CTR11 is low (0 to 0.5V) and CTR12 is high (3.3V or 5V), transistor Q1 is turned off and Q2 is turned on, thereby turning off Q3, and VH_OUT outputs a low voltage (0 to 0.5V). R1 ​​is a current-limiting resistor. R2 and R3 are voltage-dividing resistors, and R4 and R5 are drive resistors.

[0041] Since there is a certain time delay between the on-off of Q1, Q2, and Q3, the on-off response time of the PIN diode is long, which leads to a long tuning time of the frequency hopping filter. Figure 5As shown, when the control levels of Q1 and Q2 are high and low at the same time respectively, it takes a time delay of T1 (15~30us) to cause Q3 to turn on and VH_OUT to output high voltage (80V-400V); when the control levels of Q1 and Q2 are low and high at the same time respectively, it takes a time delay of T2 (20~30us) to cause Q3 to turn off and VH_OUT to output low voltage (0~0.5V).

[0042] The present invention controls the timing of Q1 and Q2 respectively through a programmable logic gate array (CPLD or FPGA), thereby reducing the on-off delay between Q1, Q2, and Q3. When VH_OUT1 is required to output high voltage, it is first Figure 4 The PL2A port of the programmable logic gate array U1 shown in the figure assigns a high level to CTR11, and then according to the actual circuit situation, Figure 6 The delay shown is T3 (15~30us), and then a low level is assigned to CTR12 through the PT2A port of U1, so Q1 is turned on, Q2 is turned off, and Q3 is turned on. The turn-on delay of Q3 can be reduced to within 1~5us.

[0043] The same principle applies. When VH_OUT1 needs to output a low voltage, first assign a high level to CTR12 through the PT2A port of U1. Figure 6 As shown, a delay of T4 (10 to 30 μs) then assigns a low level to CTR11 via U1's PL2A port. This causes Q1, Q2, and Q3 to turn on and off in a specific sequence. Delays T3 and T4 can be pre-set within a programmable logic gate array (CPLD or FPGA) chip via software, ensuring that Q3's turn-on and turn-off are affected solely by the PN junction's transit time (in nanoseconds). This ensures that Q3's turn-off delay is controlled within 1 to 5 μs.

[0044] It is understandable that the delay range between Q1, Q2, and Q3 can be found through experiments, and then a more reasonable timing can be set through the programmable logic gate array program to ensure that the tuning time of the frequency hopping filter is within 1 to 5us.

[0045] It should be understood that those skilled in the art can make improvements or changes based on the above description, and all such improvements and changes should fall within the scope of protection of the appended claims of the present invention.

Claims

1. A fast-tuning frequency-hopping filter, characterized in that: It includes a PIN diode switch capacitor matrix unit, a PIN diode drive unit and a programmable logic gate array, wherein the PIN diode switch capacitor matrix unit includes multiple PIN diodes, the PIN diode drive unit includes multiple drive circuits, and each drive circuit corresponds to a PIN diode; The drive circuit includes NPN transistors Q1 and Q2, and a PNP transistor Q3; wherein the base of Q1 is connected to an output control terminal of a programmable logic gate array via a drive resistor; the emitter of Q1 is grounded, and the collector of Q1 is connected to a DC high voltage via a current-limiting resistor; the base of Q2 is connected to another output control terminal of the programmable logic gate array via a drive resistor; the base of Q3 is connected to the collector of Q1, the emitter of Q3 is connected to the DC high voltage via a current-limiting resistor, and the collector of Q3 is connected to the collector of Q2, and serves as the output terminal of the drive circuit and is connected to a corresponding PIN diode; The process of fast tuning of the frequency hopping filter is as follows: The programmable logic gate array generates delays to control the timing of Q1 and Q2 respectively, reducing the on-off delays between Q1, Q2, and Q3; The timing of the base terminal levels of Q1 and Q2 is controlled separately through a programmable logic gate array to reduce the on-off delay between Q1, Q2 and Q3; When the driving circuit outputs high voltage, it first assigns a high level to the base terminal of Q1 through an output control terminal of the programmable logic gate array, and delays for a certain time, and then assigns a low level to the base terminal of Q2 through another output control terminal of an output control terminal of the programmable logic gate array, Q1 is turned on, Q2 is turned off, and Q3 is turned on; When the driving circuit outputs a low voltage, a high level is assigned to the base terminal of Q2 through the programmable logic gate array, and after a preset delay, the base terminal of Q1 is assigned a low level. Then, Q1, Q2, and Q3 are turned on and off respectively according to a certain timing, so that the on-off time of Q3 is only the transition time of the PN junction.

2. The fast-tuning frequency hopping filter according to claim 1, wherein A voltage divider resistor is also provided between the collectors of Q1 and Q3.

3. The fast tuning frequency hopping filter according to claim 1, wherein The DC high voltage is 80V~400V.

4. The fast-tuning frequency hopping filter according to claim 1, wherein: The programmable logic gate array is CPLD or FPGA.

5. The fast-tuning frequency hopping filter according to claim 1, wherein: When one output control terminal of the programmable logic gate array is at a high level and the other output control terminal is at a low level, Q1 is turned on and Q2 is turned off, thereby Q3 is turned on, and the output end of the driving circuit outputs a high voltage; conversely, Q1 is turned off and Q2 is turned on, thereby Q3 is turned off, and the output end of the driving circuit outputs a low voltage.

6. The fast-tuning frequency-hopping filter according to claim 5, characterized in that: The high level is 3.3V or 5V, and the low level is 0~0.5V.

7. The fast-tuning frequency-hopping filter according to claim 5, wherein: Q1 and Q2 are N-channel MOS tubes or NPN BJT transistors, and Q3 is a P-channel MOS tube or PNP BJT transistor.

8. The fast-tuning frequency-hopping filter according to claim 1, wherein: The delay of Q1 is 15~30us, and the delay of Q2 is 10~30us.

9. The fast-tuning frequency hopping filter according to claim 1, wherein: The time delay of Q3 turning on or off is 1~5us.

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