A programmable delay dithering circuit

Abstract

The application discloses a programmable delay anti-jitter circuit, which comprises a voltage amplification circuit, an input end of the voltage amplification circuit is connected with a programmable reference voltage circuit, and output ends are respectively connected with a programmable current source circuit and a programmable capacitor circuit; the programmable current source circuit and the programmable capacitor circuit are both connected with a shaping circuit; and an output end of the shaping circuit outputs a signal from which a jitter pulse is eliminated. The application can solve the problem that a jitter pulse of 5 ms to 10 ms can be eliminated.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and more particularly to a programmable delay anti-jitter circuit. Background Technology

[0002] Intelligent electronic devices typically include a one-button reset function, which involves a reset operation on the digital circuitry. To prevent abnormal resets from being introduced at the reset port, the input signal needs to be debounced and filtered. Existing debounce circuits often employ RC filters, but RC filters have a large area and poor anti-interference capability for eliminating pulses in the 5ms to 10ms range. Figure 2 As shown, the time constant of the RC filter is τ = R × C. Therefore, the larger the jitter pulse width, the larger the RC area consumed. For eliminating jitter of 5ms to 10ms, the integrated circuit area is very large. After shaping, even weak glitches will be amplified, resulting in poor jitter removal effect. Figure 3 As shown, this structure adds a differentiating circuit and a switching circuit, which can eliminate the jitter of the input port voltage instability, but the filtering effect is not good for eliminating jitter of 5ms to 10ms.

[0003] The second approach uses a pulse generated by a startup circuit to begin counting. Once a predetermined counting cycle is reached, a start signal is output. This second approach can eliminate jitter exceeding 10ms, but it requires an OSC and a counter, resulting in a larger area. Figure 4 As shown, a counter and OSC are used to filter out jitter signals. The jitter width time constant τ = T × N. The counting period and OSC period (T) can be set according to the width of the jitter signal to be filtered out. The filtering effect is good, but the circuit structure is more complex than the RC filter structure. Summary of the Invention

[0004] The purpose of this invention is to provide a programmable delay anti-jitter circuit to solve the technical problems of poor anti-interference capability of RC filtering and large area required to eliminate pulses of 5ms to 10ms.

[0005] The objective of this invention is achieved by the following technical solution: a programmable delay anti-jitter circuit, comprising a voltage amplifier circuit, wherein the input terminal of the voltage amplifier circuit is connected to a programmable reference voltage circuit, and the output terminal is connected to a programmable current source circuit and a programmable capacitor circuit respectively. Both the programmable current source circuit and the programmable capacitor circuit are connected to a shaping circuit, and the output terminal of the shaping circuit outputs a signal of the eliminated jitter pulse.

[0006] Furthermore, the voltage amplification circuit includes a differential amplifier, the input terminals of which are connected to a programmable reference voltage circuit and a filter circuit, respectively.

[0007] Furthermore, the filtering circuit includes an RC filtering circuit.

[0008] Furthermore, the programmable reference voltage circuit includes a resistor divider power supply circuit or a BJT cascaded power supply circuit.

[0009] Furthermore, the output terminal of the voltage amplifier circuit is connected to a programmable current source circuit and a programmable capacitor circuit respectively through transistors.

[0010] Furthermore, the programmable current source circuit includes a programmable constant current source ICH, which is a mirror reference current source, and the output terminal of the mirror reference current source is connected to the shaping circuit.

[0011] Furthermore, the programmable capacitor circuit includes a programmable capacitor CF, which is a gated parallel capacitor connected to the shaping circuit.

[0012] Furthermore, the shaping circuit includes a comparator, the input of which is connected to a programmable current source circuit and a programmable capacitor circuit respectively, and the output of which outputs a signal of the eliminated jitter pulse.

[0013] Furthermore, the signal of the jitter pulse to be eliminated is a jitter pulse signal on the order of 5ms to 10ms.

[0014] The beneficial effects of this invention are as follows: by adding a comparator and setting the flip threshold of the input signal, voltages less than VREF are eliminated, thus solving the problem of poor anti-interference capability; by programming the delay time, it is ensured that pulses of a specified width can be filtered out, thus eliminating jitter pulses of 5ms to 10ms. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the structures shown in these drawings without creative effort.

[0016] Figure 1 This is the circuit schematic diagram of the present invention;

[0017] Figure 2 The principle of existing RC filter circuits Figure 1 ;

[0018] Figure 3 The principle of existing RC filter circuits Figure 2 ;

[0019] Figure 4 Schematic diagram of the dejitter filter circuit;

[0020] Figure 5 Principle of programmable reference voltage circuit Figure 1 ;

[0021] Figure 6 Principle of programmable reference voltage circuit Figure 2 ;

[0022] Figure 7 This is a schematic diagram of a programmable current source circuit.

[0023] Figure 8 This is a schematic diagram of a programmable capacitor circuit.

[0024] Figure 9 This is a schematic diagram of the transmission characteristics of the shaping circuit. Detailed Implementation

[0025] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0026] It should be noted that similar labels and letters in the following figures indicate similar items. Therefore, once an item is defined in one figure, it does not need to be further defined and explained in subsequent figures.

[0027] The following detailed description of some embodiments of the present invention is provided in conjunction with the accompanying drawings. Unless otherwise specified, the following embodiments and features can be combined with each other.

[0028] Example 1:

[0029] See Figure 1 A programmable delay anti-jitter circuit includes a voltage amplifier circuit, the input of which is connected to a programmable reference voltage circuit, and the output of which is connected to a programmable current source circuit and a programmable capacitor circuit, respectively. Both the programmable current source circuit and the programmable capacitor circuit are connected to a shaping circuit, and the output of the shaping circuit outputs a signal of the eliminated jitter pulse.

[0030] In this embodiment, the voltage amplification circuit includes a differential amplifier. The input terminals of the differential amplifier are connected to a programmable reference voltage circuit and a filter circuit, respectively. The filter circuit includes an RC filter circuit. Based on the jittered voltage, a reference voltage VREF is selected. Through the differential amplifier, signals with peak values ​​smaller than VREF can be filtered out. Furthermore, the programmable reference voltage circuit employs a resistor divider power supply circuit. This resistor divider power supply circuit can be obtained by dividing an existing power supply, bandgap reference, etc., using resistors (e.g.,...). Figure 5 (as shown); Furthermore, the programmable reference voltage circuit can also employ a BJT cascaded power supply circuit, which can obtain N times the VBE value through the cascading of BJTs (e.g., Figure 6 (As shown).

[0031] In this embodiment, the output terminal of the differential amplifier is connected to a programmable current source circuit and a programmable capacitor circuit respectively through a transistor. Furthermore, the output terminal of the differential amplifier is connected to the base of the transistor, the collector of the transistor is connected to the programmable current source circuit, and the emitter of the transistor is connected to the programmable capacitor circuit.

[0032] In this embodiment, the programmable current source circuit includes a programmable constant current source ICH, which is a mirror reference current source. The mirror reference current source is obtained by mirroring a reference current source (e.g., ...). Figure 7 As shown in the figure, the output terminal of the mirror reference current source is connected to the shaping circuit.

[0033] In this embodiment, the programmable capacitor circuit includes a programmable capacitor CF. The programmable capacitor CF is a selected parallel capacitor. This selected parallel capacitor achieves scaling of the CF capacitance value by selecting the parallel capacitors (e.g., ...). Figure 8 As shown in the figure, the gate parallel capacitor is connected to the shaping circuit.

[0034] When the peak value of the input signal exceeds VREF, V B =-A0×(V A -VREF); Since A0 is usually very large, the swing of the differential signal can be pulled between the power supply and ground. The programmable constant current source ICH is mainly used to charge the programmable capacitor CF. In order to eliminate the jitter of 5ms to 10ms, it is achieved by the programmable constant current source ICH and the programmable capacitor CF, which can eliminate the time constant of the jitter pulse width. VIH is the input logic high level of the shaping circuit. By setting the programmable constant current source ICH to 20nA, VIH to 4V, and the programmable capacitor CF to 30pF, we can obtain: Since the jitter voltage pulse width is 5ms to 10ms, but its peak value does not exceed VREF for as long as 5ms to 10ms, a reasonable value can be set through a programmable charging time constant.

[0035] In this embodiment, the shaping circuit includes a comparator. The input terminals of the comparator are connected to a programmable constant current source ICH and a programmable capacitor CF, respectively. The output terminal outputs a jitter pulse signal with a duration of 5ms to 10ms eliminated. (See also...) Figure 9 The comparator protects against two toggling thresholds, VIL and VIH. When the input voltage is greater than or equal to VIH, the output logic is high; when the input voltage is less than or equal to VIL, the output logic is low. This is sufficient as long as VIL is greater than or equal to VSS + Vnoise, and VIH is less than or equal to VDD - Vnoise. Here, Vnoise represents system noise. As long as VIL and VIH are identifiable, the hysteresis voltage Window = VIH - VIL should be as large as possible.

[0036] It should be noted that, in the foregoing embodiments, the terms "connection" and "setting" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, features defined with "connection" or "setting" may explicitly or implicitly include one or more of that feature. Furthermore, the terms "connection," "setting," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein.

[0037] The above embodiments describe the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Modifications and variations made by those skilled in the art without departing from the spirit and scope of the invention should be within the protection scope of the appended claims.

Claims

1. A programmable delay anti-jitter circuit, characterized in that, The device includes a voltage amplifier circuit, the input of which is connected to a programmable reference voltage circuit, and the output of which is connected to a programmable current source circuit and a programmable capacitor circuit, respectively. Both the programmable current source circuit and the programmable capacitor circuit are connected to a shaping circuit, and the output of the shaping circuit outputs a signal with eliminated jitter pulses. The voltage amplifier circuit includes a differential amplifier, the input terminals of which are connected to a programmable reference voltage circuit and a filter circuit, respectively; the output terminal of the voltage amplifier circuit is connected to a programmable current source circuit and a programmable capacitor circuit through transistors, respectively. The programmable current source circuit includes a programmable constant current source ICH, which is a mirror reference current source, and the output terminal of the mirror reference current source is connected to the shaping circuit; the programmable capacitor circuit includes a programmable capacitor CF, which is a gated parallel capacitor, and the gated parallel capacitor is connected to the shaping circuit. The shaping circuit includes a comparator, the input of which is connected to a programmable current source circuit and a programmable capacitor circuit respectively, and the output of which outputs a signal of the eliminated jitter pulse; the signal of the eliminated jitter pulse is a jitter pulse signal on the order of 5ms to 10ms that has been eliminated.

2. The anti-jitter circuit with a programmable delay as described in claim 1, characterized in that, The filtering circuit includes an RC filtering circuit.

3. The anti-jitter circuit with a programmable delay as described in claim 1, characterized in that, The programmable reference voltage circuit includes a resistor divider power supply circuit or a BJT cascaded power supply circuit.

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