A synchronous timing signal generating device and a generating method

Abstract

The application provides a synchronous timing signal generation device and a generation method. The synchronous timing signal generation device comprises: a pulse period length register, which stores the period relationship between high and low levels and a reference signal in each pulse period of each synchronous timing signal; a level flip threshold value providing unit, which obtains the flip time of high and low levels of the synchronous timing signal according to the period relationship between high and low levels and the reference signal in each pulse period of the synchronous timing signal; a reference signal period counting unit, which records the period number of the reference signal after receiving a trigger signal; a trigger unit; and a trigger output timing controller, which outputs the synchronous timing signal level flip when the period number of the reference signal reaches the flip time of high and low levels. The synchronous timing signal generation device provided by the application can output a synchronous timing signal.

Description

Technical Field

[0001] This invention belongs to the technical field of timing circuit structures, and specifically relates to a synchronous timing signal generation device and generation method. Background Technology

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensors offer advantages such as high integration, small size, and low power consumption. Currently, CMOS image sensors employ two exposure modes: rolling shutter exposure, which boasts a high signal-to-noise ratio but a lower frame rate, suitable for high-definition imaging of static or slowly moving objects; and global exposure, which has a relatively lower signal-to-noise ratio but a high frame rate, ideal for photographing or recording dynamic objects. For both exposure modes, the image sensor readout circuitry typically needs to generate frame synchronization or line synchronization timing signals to synchronize the chip's operating timing.

[0003] However, due to different exposure modes, different types of frame synchronization or line synchronization timing signals need to be configured, which requires a large number of register resources and electronic units and is very difficult to configure. Therefore, existing technologies cannot meet the requirements for generating different timing signals. Summary of the Invention

[0004] The purpose of this invention is to provide a synchronous timing signal generation device and method that is compatible with both global exposure and rolling shutter exposure modes, and supports exposure time settings that span frame period or line period, thereby improving the compatibility and practicality of the synchronous timing signal generation device.

[0005] To achieve the above objectives, the present invention provides a synchronous timing signal generation device, comprising at least:

[0006] The pulse period duration register stores the periodic relationship between the high and low levels and the reference signal in each pulse period of each of the synchronization timing signals;

[0007] A level-flipping threshold providing unit is electrically connected to the pulse period duration register. The level-flipping threshold providing unit obtains the high and low level flipping time of the synchronization timing signal based on the periodic relationship between the high and low levels and the reference signal in each pulse period of the synchronization timing signal.

[0008] The reference signal period counting unit records the number of periods of the reference signal after receiving the trigger signal;

[0009] A trigger unit is electrically connected to the level-flipping threshold providing unit and the reference signal period counting unit; and

[0010] An output timing controller is electrically connected to the trigger unit. When the number of cycles of the reference signal reaches the high-low level switching time, the synchronization timing signal level output by the output timing controller flips.

[0011] In one embodiment of the present invention, the pulse period duration register includes a first coefficient register, which stores the periodicity coefficients of the high and low levels of the synchronization timing signal in each pulse period, and the periodicity coefficients of the reference signal.

[0012] In one embodiment of the present invention, when the synchronization timing signal is a frame synchronization timing signal, the edge position of the pulse within a frame period is: R0 = P0 * line period + P1 * clock period.

[0013] Where P0 is the row period coefficient and P1 is the clock period coefficient;

[0014] The duration of the voltage level maintenance is:

[0015] R1 = P2 * row period;

[0016] Where P2 is the period coefficient of the reference signal.

[0017] In one embodiment of the present invention, when the synchronization timing signal is a line synchronization timing signal, the edge position of the pulse within one frame period is: R0 = P1 * clock period;

[0018] Where P1 is the clock cycle coefficient;

[0019] The duration of the voltage level maintenance is:

[0020] R1 = P2 * clock cycle;

[0021] Where P2 is the period coefficient of the reference signal.

[0022] In one embodiment of the present invention, the pulse period duration register includes a second coefficient register, which stores the number of line cycles within a frame period and the number of clock cycles within a line period.

[0023] In one embodiment of the present invention, the synchronous timing signal generating device is further provided with a level duration unit selection register.

[0024] In one embodiment of the present invention, the level flipping threshold providing unit includes a reference signal selector. The input terminal of the reference signal selector is electrically connected to the pulse period duration register and the level duration length unit selection register. The reference signal selector selects the output line period coefficient or clock period coefficient according to the length unit stored in the level duration length unit selection register.

[0025] In one embodiment of the present invention, the level-flipping threshold providing unit further includes:

[0026] Adder; its input is electrically connected to the reference signal selector and the pulse period duration register; and

[0027] The subtractor has its input terminal electrically connected to the output terminal of the adder and the pulse period duration register.

[0028] In one embodiment of the present invention, the reference signal period counting unit further includes a clock counter, the input terminal of which is electrically connected to the input clock signal. After receiving a trigger signal, the clock counter records the number of periods of the input clock signal.

[0029] In one embodiment of the present invention, the level flipping threshold providing unit further includes a first selector, which selects the output clock cycle coefficient, the output value of the adder or the output value of the subtractor based on three signals: the level of the output timing signal, the level duration unit selection register, and the cross-cycle indicator signal.

[0030] In one embodiment of the present invention, the reference signal period counting unit further includes a line synchronization signal counter. The input terminal of the line synchronization signal counter is electrically connected to the line synchronization signal. After receiving a trigger signal, the line synchronization signal counter records the number of periods of the line synchronization signal.

[0031] In one embodiment of the present invention, the level inversion threshold providing unit further includes a second selector, which selects the output row period coefficient, the output value of the adder, or the output value of the subtractor based on three signals: the level of the output timing signal, the level duration unit selection register, and the cross-cycle indicator signal.

[0032] In one embodiment of the present invention, the triggering unit includes a first comparator, the input of which is electrically connected to the output of the clock counter and the output of the first selector.

[0033] In one embodiment of the present invention, the triggering unit further includes:

[0034] The input terminal of the second comparator is electrically connected to the output terminal of the line synchronization signal counter and the output terminal of the second selector;

[0035] The controller, with its input electrically connected to the output of the second comparator and the frame synchronization or line synchronization control register; and

[0036] The logic gate has its input terminals electrically connected to the output terminals of the first comparator and the controller.

[0037] In one embodiment of the present invention, the synchronization timing signal generating device further includes a cycle crossing judgment unit, which determines whether a cycle crossing is required based on the duration of the high and low levels within one cycle of the synchronization timing signal and the duration of one cycle of the trigger signal.

[0038] This invention provides a method for generating synchronous timing signals, comprising at least the following steps:

[0039] The relationship between the high and low levels and the period of the reference signal is set in each pulse period of each of the aforementioned synchronization timing signals;

[0040] Based on the periodic relationship between the high and low levels of the synchronization timing signal and the reference signal in each pulse period of the synchronization timing signal, the switching time of the high and low levels of the synchronization timing signal is obtained.

[0041] Upon receiving the trigger signal, record the number of cycles of the reference signal; and

[0042] When the number of cycles of the reference signal reaches the high-low level switching time, the output synchronization timing signal level will be flipped.

[0043] In summary, the synchronous timing signal generation device and method provided by this invention can simultaneously satisfy the flexible and arbitrary timing changes of independent frame synchronization or line synchronization timing signals. Furthermore, frame synchronization or line synchronization, as well as whether to span periods, can be set through registers. It fully utilizes existing clock counters and line synchronization signal counters; only the position register of the synchronous timing signal change and the high (low) level duration register need to be configured to determine the complete timing signal. Therefore, it saves circuit and register resources, and the number of comparators is only related to the number of synchronous timing signals. It is fully compatible with both global exposure and rolling shutter exposure modes. Therefore, the synchronous timing signal generation device and method provided by this invention are not limited to specific application scenarios. When applied to image sensor chips, it is fully compatible with both global exposure and rolling shutter exposure modes and supports exposure time settings spanning frame or line periods, greatly improving the compatibility and practicality of the method and device. Attached Figure Description

[0044] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0045] Figure 1 This is a structural block diagram of an image sensor system according to the present invention.

[0046] Figure 2 This is a schematic diagram of various synchronization timing signals in this invention.

[0047] Figure 3 This is a periodic decomposition diagram of a synchronous timing signal in this invention.

[0048] Figure 4 This is a schematic diagram of a synchronous timing signal generation device according to the present invention.

[0049] Figure 5 This is a schematic diagram of a specific synchronous timing signal generation device in this invention.

[0050] Figure 6 This is a flowchart of a method for generating a synchronous timing signal in this invention.

[0051] Figure 7 This is a flowchart of a method for generating a synchronous timing signal in this invention.

[0052] Figure 8 This is a decomposition diagram of the synchronous timing signal spanning cycles in this invention. Detailed Implementation

[0053] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Preferred embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of the disclosure of this application.

[0054] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0055] In the description of this invention, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing the invention and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0056] Please see Figure 1As shown, the image sensor 200 includes a readout circuit 202 and a control circuit 204 connected to the pixel array 201. A data processing / storage module 203 is connected to the readout circuit 202 to perform data processing and storage operations on the output of the pixel circuit. A status / timing control module 205 is connected to the readout circuit 202 and the control circuit 204 to control the reading of the pixel array 201. The pixel array 201 includes multiple pixel units arranged in rows (R1, R2, R3…Ry) and columns (C1, C2, C3…Cx). The pixel signals output by the pixel array 201 are output to the readout circuit 202 via the column lines. In one embodiment, after each pixel unit acquires image data, the image data is read out by the readout circuit 202 with the readout mode specified by the status / timing control module 205, and then transmitted to the data processing / storage module 203. In specific applications, the readout circuit 202 may include an analog-to-digital converter (ADC) circuit, an amplifier circuit, and others. In some application embodiments, the status / timing control module 205 may include a programmed selection system to determine whether readout is performed in a global exposure mode or a rolling shutter exposure mode. The data processing / storage module 203 may store only image data or image data processed or applied with image effects. In one application example, the readout circuit 202 may run along the readout column lines (e.g., ...). Figure 1 As shown, image data is read out one line at a time, or various other methods may be used to read out image data. The operation of control circuit 204 can be determined by the current settings of state / timing control module 205. For example, control circuit 204 generates a shutter signal to control image acquisition. In some applications, this shutter signal may be a global exposure signal that causes all pixels of pixel array 201 to acquire their image data simultaneously through a single acquisition window.

[0057] Please combine 4 and Figure 5 As shown, in one embodiment of the present invention, the present invention provides a synchronous timing signal generation device and generation method, which can be applied to related chips such as image sensors, image processing or display interfaces, to adjust the operation of control circuits in image sensors, image processing or display interfaces.

[0058] Please see Figures 2 to 8As shown, the present invention provides a synchronization timing signal generation device comprising a pulse period duration register 11, a level switching threshold providing unit 12, a reference signal period counting unit 13, a trigger unit 14, and an output timing controller 15. The pulse period duration register 11 stores the periodic relationship between the high and low levels of each synchronization timing signal and the reference signal in each pulse period. The level switching threshold providing unit 12 is electrically connected to the high and low level duration register, and obtains the switching time of the high and low levels of the synchronization timing signal based on the periodic relationship between the high and low levels of the synchronization timing signal and the reference signal in each pulse period. The switching time of the high and low levels is obtained based on the period count of the reference signal. The reference signal period counting unit 13 begins recording the number of periods of the reference signal after receiving the trigger signal. The trigger unit 14 is electrically connected to the level flip threshold providing unit 12 and the reference signal period counting unit 13. When the number of periods of the reference signal reaches the high and low level flip time, the trigger unit 14 triggers the output timing controller 15, causing the level of the synchronous timing signal output by the output timing controller 15 to flip.

[0059] Please see Figure 2 and Figure 3 As shown, in one embodiment of the present invention, the trigger signal is, for example, a frame synchronization signal (VSYNC) or a line synchronization signal (HSYNC), and the reference signal is, for example, a line synchronization signal or an input clock signal. In this embodiment, the synchronization timing signal generating device can, for example, generate a first type of synchronization timing signal with the frame synchronization signal as the trigger signal and the line synchronization signal and the input clock signal as reference signals. The synchronization timing signal generating device can also, for example, generate a second type of synchronization timing signal with the line synchronization signal as the trigger signal and the input clock signal as the reference signal. The frame synchronization signal, the line synchronization signal, and the input clock signal are all cyclical periodic signals, and the generated synchronization timing signal is, for example, a reset signal RST or a read signal, which is a synchronization timing signal triggered by the rising edge or falling edge of the frame synchronization signal or the line synchronization signal. In this embodiment, the reset signal RST is taken as an example. The reset signal RST includes a reset signal that does not cross the trigger signal cycle and a reset signal that crosses the trigger signal cycle.

[0060] Please see Figure 3 , Figure 4 and Figure 5As shown, in one embodiment of the present invention, the pulse period duration register 11 stores the relationship between the high and low levels of each synchronization timing signal in each pulse period and the reference signal. Specifically, the pulse period duration register 11 includes multiple first coefficient registers 111. Each first coefficient register 111 is configured with a coefficient relating the duration of the high and low levels of the synchronization timing signal in each pulse period to the period of the reference signal. Further, the first coefficient register 111 stores coefficients relating the high and low levels of the first type of synchronization timing signal and the period of the reference signal in each pulse period. In this embodiment, for the first type of synchronization timing signal, the pulse edge position (rising edge or falling edge position) R0 = P0 * line period + P1 * clock period within one frame period, and the level maintenance length (high level or low level maintenance length) R1 = P2 * line period. For the second type of synchronization timing signal, the pulse edge position (rising edge or falling edge position) R0 = P1 * clock period within one line period, and the level maintenance length (high level or low level maintenance length) R1 = P2 * line period. Wherein, P0 is the line period coefficient, specifically the number of cycles of the line synchronization signal from the moment the trigger signal (frame synchronization signal or line synchronization signal) is triggered (falling edge or rising edge trigger) until the synchronization timing signal level flips. P1 is the clock period coefficient. When the synchronization signal is a first-type synchronization timing signal, P1 is specifically the number of cycles of the input clock signal from the falling edge of the line synchronization signal to the moment the first-type synchronization timing signal level flips within a period other than one line synchronization signal cycle, after calculating an integer number of line synchronization signals triggered by the frame synchronization signal (falling edge or rising edge trigger). When the synchronization timing signal is a second-type synchronization timing signal, P1 is specifically the number of cycles of the input clock signal from the moment the line synchronization signal is triggered (falling edge or rising edge trigger) until the moment the second-type synchronization timing signal level flips. P2 is the reference signal period coefficient, specifically the number of cycles of the reference signal corresponding to the time the high (low) level is maintained after the first level flip of the synchronization timing signal (first-type or second-type synchronization timing signal). You can set up, for example, three first coefficient registers 111, and configure P0, P1 and P2 in the first coefficient registers 111 in sequence.

[0061] Please see Figure 4 and Figure 5 As shown in one embodiment of the present invention, the pulse period duration register 11 further includes a plurality of second coefficient registers 112, which store the number of line cycles VP and the number of clock cycles HP within a line cycle in a frame period.

[0062] Please see Figure 3As shown, in one embodiment of the present invention, a synchronization timing signal is provided that uses a frame synchronization signal as a trigger signal. Upon receiving the trigger signal, the edge position R0 of the synchronization timing signal is equal to, for example, 3 line cycles plus, for example, 5 clock cycles, then P0 = 3 and P1 = 5. After the level flips, the level maintenance length R1 is equal to 5 line cycles, i.e., 5 reference signal cycles, then P2 = 5. Furthermore, the number of line cycles in one frame cycle of this synchronization timing signal is 12, i.e., VP = 12.

[0063] Please see Figure 4 and Figure 5 As shown, in one embodiment of the present invention, a level duration unit selection register 113 is also configured, which stores the line period and the clock period.

[0064] Please see Figure 4 and Figure 5 As shown, in one embodiment of the present invention, the level inversion threshold providing unit 12 includes a reference signal selector 121, an adder 122, a subtractor 123, a first selector 124, and a second selector 125. The input of the reference signal selector 121 is electrically connected to the first coefficient register 111 and the level duration unit selection register 113 in the pulse period duration register 11. Upon receiving a trigger, within one frame period or line period, the line period coefficient P0 or the clock period coefficient P1 is input to the reference signal selector 121. The reference signal selector 121 selects the output according to the length unit stored in the level duration unit selection register 113. When the level duration unit selection register 113 outputs a line period unit, the reference signal selector 121 outputs the line period coefficient P0; when the level duration unit selection register 113 outputs a clock period unit, the reference signal selector 121 outputs the clock period coefficient P1.

[0065] Please see Figure 4 and Figure 5As shown, in one embodiment of the present invention, the input terminal of adder 122 is electrically connected to reference signal selector 121 and the first coefficient register 111 in pulse period duration register 11. After the output signal of reference signal selector 121 and the synchronization timing signal are flipped for the first time, the reference signal period coefficient P2 corresponding to the duration of the high level (low level) is input to adder 122. Then, when the unit is row period, the output value of adder 122 is CNT_REF1 = P0 + P2. When the unit is clock period, the output value of adder 122 is CNT_REF1 = P1 + P2. The input terminal of subtractor 123 is electrically connected to the output terminal of adder 122 and the second coefficient register 112 in pulse period duration register 11. When the unit is row period, the output value of subtractor 123 is CNT_REF2 = P0 + P2 - VP. When measured in clock cycles, the output value of subtractor 123 is CNT_REF2 = P1 + P2 - HP.

[0066] Please see Figure 4 and Figure 5 As shown, in one embodiment of the present invention, the input terminals of the first selector 124 and the second selector 125 are electrically connected to the first coefficient register 111 in the pulse period duration register 11, and the row period coefficient P0 is input to the second selector 125, while the clock period coefficient P1 is input to the first selector 124. The input terminals of the first selector 124 and the second selector 125 are also electrically connected to the output terminals of the adder 122 and the subtractor 123. The first selector 124 and the second selector 125 are also electrically connected to the level duration unit selection register 113, the cross-cycle indication signal, and the output terminal of the output timing controller 15.

[0067] For details, please refer to Figure 4 and Figure 5 As shown, the first selector 124 selects the clock cycle coefficient P1 using three signals: the level of the output timing signal, the level duration unit selection register 113, and the cross-cycle indicator signal. The output value CNT_REF1 of the adder 122 or the output value CNT_REF2 of the subtractor 123 is given to the reference input of the first comparator 141. The second selector 125 selects the row cycle coefficient P0 using three signals: the level of the output timing signal, the level duration unit selection register 113, and the cross-cycle indicator signal. The output value CNT_REF1 of the adder 122 or the output value CNT_REF2 of the subtractor 123 is given to the reference input of the second comparator 142. The truth tables of the first selector 124 and the second selector 125 are shown in Table 1 and Table 2, respectively.

[0068] Table 1 Truth Table of First Selector

[0069]

[0070] Table 2 Truth Table for the Second Selector

[0071]

[0072] Please see Figure 4 and Figure 5 As shown, in one embodiment of the present invention, the cross-cycle indication signal is output by the cross-cycle judgment unit 16. The input terminal of the cross-cycle judgment unit 16 is electrically connected to the output terminal of the output timing controller 15. The input clock signal, frame synchronization signal and line synchronization signal can determine whether a cross-cycle is required based on the duration of the high level and low level of the set synchronization timing signal in one cycle and the duration of the trigger signal (frame cycle signal or) in one cycle.

[0073] Please see Figure 4 and Figure 5 As shown, in one embodiment of the present invention, the reference signal period counting unit 13 begins recording the number of periods of the reference signal after receiving a trigger signal. Specifically, the reference signal period counting unit 13 includes a clock counter 131 and a horizontal synchronization signal counter 132. The input terminal of the clock counter 131 is electrically connected to the input clock signal, and records the number of periods of the input clock signal after receiving the trigger signal. The input terminal of the horizontal synchronization signal counter 132 is electrically connected to the horizontal synchronization signal, and records the number of periods of the horizontal synchronization signal after receiving the trigger signal.

[0074] Please see Figure 4 and Figure 5As shown, in one embodiment of the present invention, the trigger unit 14 includes a first comparator 141, a second comparator 142, a controller 143, and a logic gate 144. The input of the first comparator 141 is electrically connected to the output of the clock counter 131 and the output of the first selector 124. The input of the second comparator 142 is electrically connected to the output of the horizontal synchronization signal counter 132 and the output of the second selector 125. The input of the controller 143 is electrically connected to the output of the second comparator 142 and the frame synchronization or horizontal synchronization control register. The input of the logic gate 144 is electrically connected to the output of the first comparator 141 and the output of the controller 143. The controller 143 determines whether the comparison result of the second comparator 142 is needed based on the value of the frame synchronization or horizontal synchronization control register. The frame synchronization or horizontal synchronization control register outputs a frame synchronization or horizontal synchronization control signal. For the frame synchronization signal, the results of the first comparator 141 and the second comparator 142 must both pass through the logic gate 144 before being finally output to the output timing controller 15. For the horizontal synchronization signal, the comparison result of the second comparator 142 is directly masked. Only the results of the first comparator 141 and the controller 143 are passed through the logic gate 144 and finally output to the output timing controller 15. The output timing controller 15 is electrically connected to the output terminal of the logic gate 144, the input clock signal, and the cycle crossing indicator signal, so that the output timing controller 15 controls the output timing to flip the output level at R0 and R0+R1 or R0+R1-VP / HP (controlled by the cycle crossing indicator signal), thereby generating a cyclic timing signal for frame synchronization or horizontal synchronization.

[0075] Please see Figures 4 to 7 As shown, in one embodiment of the present invention, when a synchronization timing signal is obtained using a synchronization timing signal generation device provided by the present invention, the synchronization timing signal generation method is specifically described as follows.

[0076] Please see Figure 2 , Figure 5 and Figure 6As shown, in one embodiment of the present invention, when the synchronization timing signal is a first type of synchronization timing signal, i.e., a frame synchronization timing signal, the synchronization timing signal generation method is as shown in steps S101 to S113. First, in the first coefficient register 111 of the pulse period duration register 11, the line period coefficient P0 and the clock period coefficient P1 at position R0, and the reference signal period coefficient P2 in the level maintenance length R1 are configured. When the frame synchronization signal (VSYNC) trigger edge has not arrived, the output timing controller 15 outputs the synchronization timing signal at an initial level (low level). The trigger edge is usually a falling edge, but it can also be a rising edge. When the frame synchronization signal (VSYNC) trigger edge arrives, the horizontal synchronization signal counter 132 and the clock counter 131 are cleared and start counting. When the count value of the horizontal synchronization signal counter 132 reaches P0, that is, CNT_HS = P0 and the count value of the clock counter 131 reaches the clock cycle coefficient P1, that is, CNT_CLK = P1, the output timing controller 15 changes the output synchronization timing signal level to high level (or low level), and the horizontal synchronization signal counter 132 and the clock counter 131 continue to count. When the sum of the line period coefficient P0 at position R0 and the reference signal period coefficient P2 for the duration of the high (or low) level in the synchronization timing signal does not exceed the number of line periods VP within one frame period (i.e., P0 + P2 ≤ VP), and when the count value of the line synchronization signal counter 132 reaches P0 + P2, and the count value of the clock counter 131 reaches the clock period coefficient P1 (i.e., CNT_HS = P0 + P2, CNT_CLK = P1), the output synchronization timing signal level is changed to low (or high) again. Afterwards, the line synchronization signal counter 132 and the clock counter 131 continue counting until the trigger edge of the next frame synchronization timing signal arrives again. At this point, the line synchronization signal counter 132 and the clock counter 131 are reset to zero and then count again, cyclically generating the following... Figure 2 The first type of synchronization timing signal RST_VS1 shown does not cross a cycle.

[0077] Please see Figure 2 , Figure 5 and Figure 6 As shown, in another embodiment of the present invention, when the sum of the line period coefficient P0 at position R0 and the reference signal period coefficient P2 for the length of time the high (or low) level is maintained in the synchronization timing signal exceeds the number of line periods VP within one frame period, i.e., P0 + P2 > VP, when the next frame synchronization trigger edge arrives, the output timing signal level is changed to low (or high) at this time based on the value of whether the overflow register is supported. When the overflow register is invalid, the output timing signal level is changed to low (or high) at this time, thereby generating as shown in the figure. Figure 2The first type of synchronization timing signal RST_VS2 shown does not cross a period.

[0078] Please see Figure 2 , Figure 5 and Figure 6 As shown, in another embodiment of the present invention, when the sum of the line period coefficient P0 at position R0 and the reference signal period coefficient P2 for the duration of the high (or low) level in the synchronization timing signal exceeds the number of line periods VP within one frame period, i.e., P0 + P2 > VP, when the next frame synchronization trigger edge arrives, the output timing signal level is changed to low (or high) at this time depending on whether the overflow register value is supported. When the overflow register is valid, the output timing signal level remains unchanged at this time, the line synchronization signal counter 132 and the clock counter 131 are cleared, and then the counting starts again. When the count value of the line synchronization signal counter 132 reaches P0 + P2 - VP, i.e., CNT_HS = P0 + P2 - VP, and the count value of the clock counter 131 reaches the clock period coefficient P1, i.e., CNT_CLK = P1, the output timing signal level is changed to low (or high) again, thereby generating the following... Figure 2 The first type of synchronization timing signal RST_VS3 shown here spans one frame period.

[0079] Please see Figure 2 , Figure 5 and Figure 7As shown, in one embodiment of the present invention, when the synchronization timing signal is a second type of synchronization timing signal, i.e., a horizontal synchronization timing signal, the synchronization timing signal generation method is as shown in steps S201 to S213. First, in the first coefficient register 111 of the pulse period duration register 11, a clock period coefficient P1 at position R0 and a reference signal period coefficient P2 at level maintenance length R1 are configured. When the horizontal synchronization signal (HSYNC) trigger edge has not arrived, the timing signal outputs an initial level (low level). The trigger edge is usually a falling edge, but it can also be a rising edge. When the horizontal synchronization signal (HSYNC) trigger signal arrives, the clock counter 131 is cleared and starts counting. When the count value of the clock counter 131 reaches the clock period coefficient P1, i.e., CNT_CLK = P1, the output timing signal level is changed to a high level (or a low level), and the clock counter 131 continues to count. When the sum of the clock cycle coefficient P1 at position R0 and the reference signal cycle coefficient P2 for the level holding length R1 does not exceed the number of clock cycles HP within one line cycle (i.e., P1 + P2 ≤ HP), and the clock counter 131 reaches P1 + P2 (i.e., CNT_CLK = P1 + P2), the output timing signal level is changed to low (or high) again. The clock counter 131 continues counting until the next line synchronization signal trigger edge arrives, at which point the clock counter 131 is reset to zero and starts counting again, repeating this cycle. Figure 2 The second type of synchronization timing signal RST_HS1 shown does not cross a period.

[0080] Please see Figure 2 , Figure 5 and Figure 7 As shown, in another embodiment of the present invention, when the sum of the clock cycle coefficient P1 at position R0 and the reference signal cycle coefficient P2 of the level maintenance length R1 exceeds the number of clock cycles HP in one row cycle, i.e., P1 + P2 > HP, when the next row synchronization signal trigger edge arrives, the output timing signal level is changed to low (or high) at this time depending on the value of the overflow register. When the overflow register is invalid, the output timing signal level is changed to low (or high) at this time, thereby generating the following... Figure 2 The second type of synchronization timing signal RST_HS2 shown does not cross a period.

[0081] Please see Figure 2 , Figure 5 and Figure 7As shown, in another embodiment of the present invention, when the sum of the clock cycle coefficient P1 at position R0 and the reference signal cycle coefficient P2 of the level maintenance length R1 exceeds the number of clock cycles HP in one row cycle, i.e., P1+P2>HP, when the next row synchronization signal trigger edge arrives, the output timing signal level is changed to low (or high) at this time depending on whether the overflow register is supported. When the overflow register is valid, the output timing signal level remains unchanged at this time, the clock counter 131 is cleared, and then counts again. When the count value of the clock counter 131 reaches P1+P2-HP, i.e., CNT_CLK=P1+P2-HP, the output timing signal level is changed to low (or high) again, thereby generating the following... Figure 2 The second type of synchronization timing signal RST_HS3 shown here spans one row cycle.

[0082] It is worth noting that many modifications and variations can be made to the concept of this invention in practical applications. For example, the level maintenance length R1 in the frame synchronization signal can also be configured as R1 = P2 * line period + P3 * clock period or R1 = P2 * clock period, extending the single-pulse change in this invention to a multi-pulse change (the timing signal level changes more than twice within each frame period or line period), etc., and these technical solutions still fall within the protection scope of this invention. For details, please refer to [link / reference]. Figure 8 As shown, this invention can respectively convert the timing signals of frame synchronization or line synchronization that span the frame period or line period into timing signals that do not cross the new frame period within a new frame period whose frame period time is twice the original frame period time, and timing signals that do not cross the new line period within a new line period whose line period time is twice the original line period time. For example, a new HSYNC (e.g., HSYNC) can be obtained from the original HSYNC and VSYNC signals. Figure 7 The HSYNC1 signal (with a line period twice the original line period) and VSYNC (such as...) Figure 7 The VSYNC1 signal (with a frame period twice that of the original frame period) is used. Then, based on the new HSYNC (HSYNC1) and VSYNC (VSYNC1) signals and the counter, the RST_VS2 or RST_HS2 signal is generated according to the timing signal generation method that does not cross one frame period or line period. The basic timing diagram is as follows. Figure 8 However, this solution obviously requires more circuit resources compared to the present solution. At the same time, this solution is a technical solution that can be obtained by those skilled in the art without creative labor by making modifications according to the concept of the present invention, and should also be regarded as the point to be protected by the present invention.

[0083] In this application, the various registers, counters, adders, selectors, comparators, and output timing controllers in the synchronous timing signal generation device are universal. In practical applications, the required electrical components can be selected according to the type of timing signal to be generated.

[0084] In summary, the synchronization timing signal generation apparatus and method provided by this invention use a pulse period duration register to store the periodic relationship between the high and low levels of each synchronization timing signal and the reference signal in each pulse period. The level-flipping threshold providing unit obtains the high-low level flipping time of the synchronization timing signal based on the periodic relationship between the high and low levels of the synchronization timing signal and the reference signal in each pulse period. The reference signal period counting unit starts recording the number of reference signal periods after receiving a trigger signal. When the number of reference signal periods reaches the high-low level flipping time, the trigger unit triggers the output timing controller, causing the synchronization timing signal output by the output timing controller to flip, thereby forming the synchronization timing signal.

[0085] The embodiments of the present invention disclosed above are merely illustrative of the invention. The embodiments do not exhaustively describe all details, nor do they limit the invention to the specific implementations described. Clearly, many modifications and variations can be made based on the content of this specification. This specification selects and specifically describes these embodiments to better explain the principles and practical applications of the invention, thereby enabling those skilled in the art to better understand and utilize the invention. The invention is limited only by the claims and their full scope and equivalents.

Claims

1. A synchronous timing signal generation device, characterized in that, include: A pulse period duration register stores the periodic relationship between the high and low levels of each of the synchronization timing signals and the reference signal in each pulse period; wherein, the pulse period duration register includes a first coefficient register, which stores coefficients relating the duration of the high and low levels of each of the synchronization timing signals to the periodic relationship of the reference signal in each pulse period; A level-flipping threshold providing unit is electrically connected to the pulse period duration register. The level-flipping threshold providing unit obtains the high and low level flipping time of the synchronization timing signal based on the periodic relationship between the high and low levels and the reference signal in each pulse period of the synchronization timing signal. The reference signal period counting unit records the number of periods of the reference signal after receiving the trigger signal; A trigger unit is electrically connected to the level-flipping threshold providing unit and the reference signal period counting unit; and An output timing controller is electrically connected to the trigger unit. When the number of cycles of the reference signal reaches the high-low level switching time, the synchronization timing signal level output by the output timing controller flips. Wherein, when the synchronization timing signal is a frame synchronization timing signal, within one frame period, the edge position of the pulse is: R0=P0 row period + P1 Clock cycle; Where P0 is the row period coefficient and P1 is the clock period coefficient; The duration of the voltage level is: R1 = P2 row cycle; Wherein, P2 is the reference signal period coefficient corresponding to the level maintenance length; When the synchronization timing signal is a horizontal synchronization timing signal, the pulse edge position within one horizontal cycle is: R0 = P1 Clock cycle; The duration of the voltage level is: R1 = P2 Clock cycle.

2. The synchronous timing signal generation device according to claim 1, characterized in that, The pulse period duration register includes a second coefficient register, which stores the number of line cycles within a frame period and the number of clock cycles within a line period.

3. The synchronous timing signal generation device according to claim 1, characterized in that, The synchronous timing signal generating device is also equipped with a level duration unit selection register.

4. The synchronous timing signal generating device according to claim 3, characterized in that, The level flip threshold providing unit includes a reference signal selector. The input of the reference signal selector is electrically connected to the pulse period duration register and the level duration length unit selection register. The reference signal selector selects the output line period coefficient or clock period coefficient according to the length unit stored in the level duration length unit selection register.

5. A synchronous timing signal generating device according to claim 4, characterized in that, The level-flipping threshold providing unit further includes: Adder; its input is electrically connected to the reference signal selector and the pulse period duration register; and The subtractor has its input terminal electrically connected to the output terminal of the adder and the pulse period duration register.

6. A synchronous timing signal generating device according to claim 5, characterized in that, The reference signal period counting unit also includes a clock counter, the input of which is electrically connected to the input clock signal. After receiving a trigger signal, the clock counter records the number of periods of the input clock signal.

7. A synchronous timing signal generating device according to claim 6, characterized in that, The level flip threshold providing unit further includes a first selector, which selects the output clock cycle coefficient, the output value of the adder, or the output value of the subtractor based on three signals: the level of the output timing signal, the level duration unit selection register, and the cross-cycle indicator signal.

8. A synchronous timing signal generating device according to claim 7, characterized in that, The reference signal period counting unit also includes a line synchronization signal counter. The input terminal of the line synchronization signal counter is electrically connected to the line synchronization signal. After receiving a trigger signal, the line synchronization signal counter records the number of periods of the line synchronization signal.

9. A synchronous timing signal generating device according to claim 8, characterized in that, The level inversion threshold providing unit further includes a second selector, which selects the output row period coefficient, the output value of the adder, or the output value of the subtractor based on three signals: the level of the output timing signal, the level duration unit selection register, and the cross-cycle indicator signal.

10. A synchronous timing signal generating device according to claim 9, characterized in that, The triggering unit includes a first comparator, the input of which is electrically connected to the output of the clock counter and the output of the first selector.

11. A synchronous timing signal generating device according to claim 10, characterized in that, The triggering unit further includes: The input terminal of the second comparator is electrically connected to the output terminal of the line synchronization signal counter and the output terminal of the second selector; The controller, with its input electrically connected to the output of the second comparator and the frame synchronization or line synchronization control register; and The logic gate has its input terminals electrically connected to the output terminals of the first comparator and the controller.

12. A synchronous timing signal generation device according to claim 1, characterized in that, The synchronization timing signal generating device further includes a cycle crossing judgment unit, which determines whether a cycle crossing is required based on the duration of the high and low levels within one cycle of the synchronization timing signal and the duration of one cycle of the trigger signal.

13. A method for generating a synchronous timing signal, characterized in that, At least the following steps are included: Set the periodic relationship between the high and low levels of each of the synchronization timing signals and the reference signal in each pulse period; set the periodic relationship coefficient between the duration of the high and low levels of each of the synchronization timing signals and the reference signal in each pulse period; Based on the periodic relationship between the high and low levels of the synchronization timing signal and the reference signal in each pulse period of the synchronization timing signal, the switching time of the high and low levels of the synchronization timing signal is obtained; After receiving the trigger signal, record the number of cycles of the reference signal; as well as When the number of cycles of the reference signal reaches the high-low level switching time, the output synchronization timing signal level will be flipped. Wherein, when the synchronization timing signal is a frame synchronization timing signal, within one frame period, the edge position of the pulse is: R0=P0 row period + P1 Clock cycle; Where P0 is the row period coefficient and P1 is the clock period coefficient; The duration of the voltage level is: R1 = P2 row cycle; Wherein, P2 is the reference signal period coefficient corresponding to the level maintenance length; When the synchronization timing signal is a horizontal synchronization timing signal, the pulse edge position within one horizontal cycle is: R0 = P1 Clock cycle; The duration of the voltage level is: R1 = P2 Clock cycle.

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