Power supply control method, device, system and terminal

Abstract

The application provides a power supply control method, device, system and terminal, and belongs to the technical field of communication. The method comprises the following steps: controlling the power supply of a first processing module and a first storage module in a target chip according to a time interval between a first time period and a second time period, wherein the first time period is a time period for executing a first task, the second time period is a time period for executing a second task, the first storage module is used for storing firmware of the target chip, and the first processing module is used for executing the first task and the second task by accessing the first storage module. The method can control the power supply of the first processing module and the first storage module in the target chip based on the time interval between the time period for executing the first task and the time period for executing the second task, so that a power supply mode with smaller power consumption can be flexibly selected based on the size of the time interval, and the power consumption is effectively reduced.

Description

Technical Field

[0001] This application relates to the field of communication technology, and in particular to a power supply control method, device, system and terminal. Background Technology

[0002] Typically, a terminal needs to perform multiple tasks. For example, the radio frequency processing chip on the terminal needs to be woken up in order to listen to PDCCH (Physical Downlink Control Channel) subframes. In order to reduce power consumption, the communication system introduces DRX (Discontinuous Reception) technology. The UE (User Equipment) periodically enters a sleep state. In the sleep state, the UE does not listen to PDCCH subframes. After waking up from the sleep state, it listens to PDCCH subframes.

[0003] However, even with DRX technology, power consumption remains high. Summary of the Invention

[0004] This application provides a power supply control method, device, system, and terminal that can reduce power consumption. The technical solution is as follows:

[0005] According to one aspect of the embodiments of this application, a power supply control method is provided, the method comprising:

[0006] The power supply to the first processing module and the first storage module in the target chip is controlled according to the time interval between the first time period and the second time period, wherein the first time period is the time period for executing the first task, the second time period is the time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to execute the first task and the second task by accessing the first storage module.

[0007] According to another aspect of the embodiments of this application, a power supply control device is provided, the device comprising:

[0008] The control module is used to control the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period, wherein the first time period is the time period for executing the first task, the second time period is the time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to execute the first task and the second task by accessing the first storage module.

[0009] According to another aspect of the embodiments of this application, a power supply control system is provided, including a control module, a first processing module of the target chip, and a first storage module of the target chip:

[0010] The control module is used to control the power supply of the first processing module and the first storage module according to the time interval between the first time period and the second time period, wherein the first time period is the time period for executing the first task, the second time period is the time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to execute the first task and the second task by accessing the first storage module.

[0011] According to another aspect of the embodiments of this application, a control module is provided, the control module including a processor, the processor being used to implement the power supply control method described above.

[0012] According to another aspect of the embodiments of this application, a terminal is provided, the terminal including the control module described above.

[0013] The power supply control scheme provided in this application embodiment can control the power supply to the first processing module and the first storage module in the target chip based on the time interval between the time period of executing the first task and the time period of executing the second task. In this way, the power supply method with lower power consumption can be flexibly selected based on the size of the time interval, thereby effectively reducing power consumption. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This application shows a schematic diagram of the structure of a power supply control system provided in an exemplary embodiment;

[0016] Figure 2 This application shows a schematic diagram of the structure of another power supply control system provided in an exemplary embodiment;

[0017] Figure 3 This application shows a schematic diagram of the structure of another power supply control system provided in an exemplary embodiment;

[0018] Figure 4 A schematic diagram of a baseband processing chip and a radio frequency processing chip provided in an exemplary embodiment of this application is shown;

[0019] Figure 5 This application shows a schematic diagram of the structure of another power supply control system provided in an exemplary embodiment;

[0020] Figure 6 This application shows a schematic diagram of the structure of another power supply control system provided in an exemplary embodiment;

[0021] Figure 7 This application shows a schematic diagram of the structure of another power supply control system provided in an exemplary embodiment;

[0022] Figure 8 A flowchart illustrating a power supply control method provided in an exemplary embodiment of this application is shown;

[0023] Figure 9 A flowchart of another power supply control method provided by an exemplary embodiment of this application is shown;

[0024] Figure 10 A flowchart of another power supply control method provided by an exemplary embodiment of this application is shown;

[0025] Figure 11 This illustration shows a schematic diagram of an SSB and paging message provided in an exemplary embodiment of this application;

[0026] Figure 12 A schematic diagram of a DRX cycle provided by an exemplary embodiment of this application is shown;

[0027] Figure 13 This illustration shows a schematic diagram of various time periods during power supply in a related art provided by an exemplary embodiment of this application;

[0028] Figure 14 This illustration shows a schematic diagram of various time periods during power supply in another related technology provided by an exemplary embodiment of this application;

[0029] Figure 15 This illustration shows a schematic diagram of various time periods during power supply in an idle state, provided by an exemplary embodiment of this application.

[0030] Figure 16 This illustration shows a schematic diagram of various time periods during power supply in an idle state, provided by an exemplary embodiment of this application.

[0031] Figure 17 This illustration shows a schematic diagram of various time periods during power supply in a connected state, provided by an exemplary embodiment of this application.

[0032] Figure 18This illustration shows a schematic diagram of various time periods during power supply in another connected state, provided by an exemplary embodiment of this application.

[0033] Figure 19 A structural block diagram of a power supply control device provided in an exemplary embodiment of this application is shown. Detailed Implementation

[0034] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be described in further detail below with reference to the accompanying drawings.

[0035] In this article, "at least one" refers to one or more, and "multiple" refers to two or more. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. The character " / " generally indicates that the preceding and following related objects have an "or" relationship.

[0036] It should be noted that the information (including but not limited to user device information, user personal information, etc.), data (including but not limited to data used for analysis, data stored, data displayed, etc.) and signals involved in this application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data must comply with the relevant laws, regulations and standards of the relevant countries and regions.

[0037] Figure 1 This is a schematic diagram of a power supply control system provided in an embodiment of this application. See also... Figure 1 The power supply control system 101 includes a control module 1011, a first processing module 1012 for the target chip, and a first storage module 1013 for the target chip.

[0038] Optionally, the power supply control system can be a SOC (System On Chip), a PCB (Printed Circuit Board) carrying the chip, or a terminal. The terminal can be various types of devices such as mobile phones, laptops, tablets, smart TVs, and vehicle terminals. This application embodiment does not impose any limitations on these devices.

[0039] See Figure 2 The control module 1011 can control the power-on or power-off of the first processing module 1012 and the first storage module 1013 of the target chip respectively. For details, please refer to the following embodiment of the power supply control method.

[0040] In the first alternative approach, the target chip can be an RF processing chip, and the control module 1011 can be a baseband processing chip. This application embodiment does not limit the types of the target chip and the control module 1011.

[0041] Optionally, see Figure 2 The power supply control system 101 also includes a power management chip 1014. The control module 1011 can control the power-on or power-off of the first processing module 1012 and the first storage module 1013 of the target chip through the power management chip 1014.

[0042] Optionally, see Figure 3 The target chip is an RF processing chip, and the control module 1011 is a baseband processing chip. The RF processing chip and the baseband processing chip work together to complete wireless communication. That is, the signal received by the power supply control system 101 first passes through the RF front-end chip, then passes through the RF processing chip to become a baseband signal, and then passes through the baseband processing chip for digital demodulation and decoding to recover the original signal.

[0043] Optionally, see Figure 4 The radio frequency (RF) processing chip includes a first storage module, a first processing module, and a bus, etc., with the first storage module and the first processing module respectively connected to the bus. The first storage module includes a memory, and the first processing module includes a high-speed interface, analog devices, a processor, etc. The baseband processing chip includes a second storage module, a second processing module, a third storage module, and a bus, etc., with the second storage module, the second processing module, and the third storage module respectively connected to the bus. The second storage module includes a first memory used to store the firmware of the RF processing chip. The third storage module includes a second memory used to store the firmware of the baseband processing chip. The second processing module includes a high-speed interface and a processor, etc. Furthermore, the RF processing chip and the baseband processing chip transmit data through the high-speed interface, enabling the baseband processing chip to process the signals sent by the RF processing chip.

[0044] Optionally, see Figure 5 The power management chip 1014 supplies power to the radio frequency processing chip and the baseband processing chip. The baseband processing chip can also control the power management chip 1014 to supply power to the radio frequency processing chip through the control interface. For example, the power management chip 1014 can control the power supply to the first processing module and the first storage module in the radio frequency processing chip respectively.

[0045] Both the RF processing chip and the baseband processing chip require firmware to be loaded before initialization can be performed, and they can only work normally after initialization is complete.

[0046] Each time the baseband processing chip is powered on, it loads the firmware into its memory. Optionally, the power supply control system 101 also includes an application processor configured with the firmware of the baseband processing chip. The baseband processing chip loads the firmware from the application processor and stores it in its memory.

[0047] In addition, the baseband processing chip will load the firmware of the radio frequency processing chip into the second storage module of the baseband processing chip. Then, the radio frequency processing chip will read the firmware from the second storage module of the baseband processing chip through a high-speed interface and load it into the memory of the radio frequency processing chip.

[0048] Optionally, the baseband processing chip includes multiple storage modules, some of which store the firmware of the baseband processing chip, while others store the firmware of the radio frequency (RF) processing chip. For example, the firmware of the baseband processing chip is stored in DDR (Double Data Rate Synchronous Dynamic Random Access Memory), and the firmware of the RF processing chip is stored in SRAM (Static Random Access Memory).

[0049] Optionally, the power supply control system 101 also includes an application processor configured with firmware for the radio frequency processing chip, which loads the firmware from the application processor.

[0050] In the second alternative approach, the target chip can be a baseband processing chip. See also Figure 6 The baseband processing chip includes a control module 1011, a first processing module 1012, and a first storage module 1013. The control module 1011 can control the power-on or power-off of the first processing module 1012 and the first storage module 1013 of the baseband processing chip, respectively.

[0051] Optionally, see Figure 7 The power management chip 1014 supplies power to the baseband processing chip. Inside the baseband processing chip, the control module 1011 controls the power-on or power-off of the first processing module 1012 and the first storage module 1013 of the baseband processing chip, respectively.

[0052] Figure 8 This is a flowchart illustrating a power supply control method provided in an embodiment of this application. The method is executed by a control module; see [link to relevant documentation]. Figure 8 The method includes:

[0053] 801. The control module controls the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period.

[0054] The target chip can be a baseband processing chip or a radio frequency processing chip, and this application embodiment does not limit it.

[0055] In this embodiment, the target chip executes a first task and a second task. A first time period is the time period during which the first task is executed, and a second time period is the time period during which the second task is executed. The first and second tasks are two adjacent tasks that the target chip needs to execute, and can be any type of task. The first and second tasks may include tasks such as receiving data, sending data, processing data, and switching states. This embodiment does not limit the type of task. The first and second tasks can be related, meaning that the first task must be executed before the second task can be executed. Alternatively, the first and second tasks can be two independent tasks that do not affect each other. This embodiment does not limit the relationship between the first and second tasks.

[0056] Optionally, the target chip executes the second task periodically, and the time period for each execution of the second task can be determined according to the period. In this case, the second task refers to the first second task executed after the first task.

[0057] In this embodiment, the target chip includes a first processing module and a first storage module. The first storage module stores the firmware of the target chip, and the first processing module performs a first task and a second task by accessing the first storage module.

[0058] In this embodiment, the second task is executed after the first task, while the step of determining the time interval occurs after the execution of the first task and before the execution of the second task. That is, when the target chip executes the first task, the control module can determine the time period for executing the first task, i.e., the first time period. Furthermore, although the target chip has not yet executed the second task, the control module can determine a pre-configured time period for executing the second task, i.e., the second time period. Based on the first time period and the second time period, the control module determines the time interval between the first time period and the second time period.

[0059] The target chip can only function properly when powered on; that is, it can only execute the first and second tasks when powered on. After executing the first task, the target chip will execute the second task after a certain period. During the time interval between the first and second time periods, supplying power to the first processing module and the first storage module of the target chip may consume power, resulting in some power consumption. While stopping power supply to the first storage module can save power during this time interval, it is necessary to re-supply the first storage module when executing the second task. After power-on, the firmware needs to be reloaded to the first storage module and initialized, which also causes some power consumption and latency. Therefore, the control module can control the power supply to the first processing module and the first storage module according to the length of the time interval between the first and second time periods.

[0060] In this embodiment, the power supply to the first processing module and the first storage module in the target chip is controlled based on the time interval between the execution of the first task and the execution of the second task. This allows for flexible selection of a power supply method with lower power consumption based on the size of the time interval, thereby effectively reducing power consumption while taking into account latency.

[0061] Based on the above embodiments, different power supply methods can be used depending on the time interval. The following embodiments will describe this process in detail.

[0062] Figure 9 This is a flowchart of another power supply control method provided in an embodiment of this application. The method is executed by a control module, which can control the power supply to the first processing module and the first storage module based on the difference in the time interval between the first time period and the second time period. See also... Figure 9 The method includes:

[0063] 901. The control module maintains power supply to the first processing module and the first storage module when the time interval is less than the first threshold.

[0064] In this embodiment, supplying power to the first processing module and the first storage module may consume power and cause a certain amount of power consumption. If the power supply to the first processing module and the first storage module is stopped, then after the power supply is restored, both the first processing module and the first storage module will cause a certain amount of power consumption. For example, the target chip needs to load the firmware required for the first processing module to run into the first processing module, and it also needs to load the firmware of the target chip into the first storage module. In this way, the target chip can perform initialization operations based on the firmware loaded in the first storage module. Only after the initialization operation is completed can it work normally and execute tasks.

[0065] Therefore, the control module sets a first threshold, which assumes that the power consumption of supplying power to the first processing module and the first storage module is relatively low when the time interval is less than the first threshold. Thus, power can be maintained to the first processing module and the first storage module during this time interval. In this way, when the second time interval arrives, the target chip does not need to restart the first processing module and the first storage module, nor does it need to reload the firmware. Furthermore, the initialization operation performed by the target chip is simpler, effectively saving power.

[0066] Optionally, the first threshold is 20 milliseconds, meaning that the control module maintains power supply to the first processing module and the first storage module when the time interval is less than 20 milliseconds.

[0067] 902. When the time interval is not less than the first threshold and less than the second threshold, the control module stops supplying power to the first processing module and continues to supply power to the first storage module.

[0068] In this embodiment, supplying power to the first processing module and the first storage module may consume power and result in some power consumption. If the power supply to the first processing module is stopped while the power supply to the first storage module is maintained, then after the power supply to the first processing module is restored, the target chip does not need to load the target chip firmware into the first storage module, nor does it need to perform initialization operations, thus saving some power consumption.

[0069] To address this, the control module sets a second threshold. If the power consumption of supplying power to the first processing module is considered high when the time interval is not less than the first threshold but less than the second threshold, then power supply to the first processing module is stopped to reduce power consumption. The power consumption of maintaining power to the first storage module is less than the power consumption of loading the target chip's firmware into the first storage module and performing initialization operations. Therefore, to reduce power consumption, power to the first storage module can be maintained during this time interval. When the second time interval arrives, power to the first processing module is restored, and the target chip can load the firmware required for the first processing module to run into the first processing module, without needing to reload the target chip's firmware into the first storage module. Furthermore, the initialization operations performed by the target chip are simpler, effectively saving power.

[0070] Optionally, the second threshold is 40 milliseconds, meaning that when the time interval is between 20 milliseconds and 40 milliseconds, the control module stops supplying power to the first processing module and continues to supply power to the first storage module.

[0071] Optionally, if power to the first processing module is stopped and then restored, a first delay will occur. The first threshold set in this embodiment can be determined based on this first delay. For example, if the first threshold is greater than the first delay, power to the first processing module is maintained when the time interval is less than the first threshold. If the time interval is not less than the first threshold, the time interval is greater than the first delay, meaning that even after power to the first processing module is stopped and then restored, the second task can still be executed in time.

[0072] 903. The control module stops supplying power to the first processing module and the first storage module when the time interval is not less than the second threshold.

[0073] In this embodiment, it can be considered that, when the time interval is not less than the second threshold, the power consumption caused by maintaining power to the first processing module is greater than the power consumption caused by loading the firmware required for the first processing module to run onto the first processing module, and the power consumption caused by maintaining power to the first storage module is also greater than the power consumption caused by reloading the firmware of the target chip to the first storage module and performing initialization operations. Therefore, in order to reduce power consumption, power supply to the first processing module and the first storage module can be stopped during this time interval. In this way, when the second time interval arrives, the power consumption caused by loading the firmware required for the first processing module to run onto the first processing module, loading the firmware of the target chip to the first storage module, and performing initialization operations is less than the power consumption caused by maintaining power to the first storage module and the first processing module, thus effectively saving power consumption.

[0074] Optionally, if the time interval is not less than a second threshold, the control module first loads the data stored in the first storage module into the second storage module, and then stops supplying power to the first storage module. This way, even if power to the first storage module is stopped and the data stored in the first storage module disappears, the stored data can be reloaded through the second storage module later. The second storage module can be located inside or outside the target chip; this embodiment does not limit its location.

[0075] For example, the second storage module is located outside the target chip. The second storage module can be DDR or other types of storage modules. Therefore, even if the power supply to the first storage module is stopped, the second storage module can maintain power, and the data in the second storage module will not be lost.

[0076] Optionally, after power is restored to the first storage module, the data from the second storage module is loaded into the first storage module. This allows the data stored in the first storage module before the power outage to be reloaded into the first storage module, thus preventing the loss of data stored in the first storage module.

[0077] Optionally, the second threshold is 40 milliseconds, meaning that the control module stops supplying power to the first processing module and the first storage module when the time interval is greater than 40 milliseconds.

[0078] Optionally, if power to the first storage module is stopped and then restored, a second delay will occur. The second threshold set in this embodiment can be determined based on this second delay. For example, if the second threshold is greater than the second delay, it ensures that power is maintained to the first storage module when the time interval is less than the second threshold. If the time interval is not less than the second threshold, it ensures that the time interval is greater than the second delay, meaning that even after power is stopped and then restored to the first storage module, the second task can still be executed in time.

[0079] In this embodiment, after executing the first task for a first period of time, the control module controls the power supply to the first processing module and the first storage module based on the time interval between the execution of the first task and the execution of the second task, as well as a first threshold and a second threshold. If the time interval is less than the first threshold, the control module continues to supply power to both the first processing module and the first storage module. If the time interval is not less than the first threshold but less than the second threshold, the control module stops supplying power to the first processing module while maintaining power to the first storage module. If the time interval is not less than the second threshold, the control module stops supplying power to both the first processing module and the first storage module. This allows for flexible selection of a lower power supply method based on the time interval, the first threshold, and the second threshold, thereby effectively reducing power consumption.

[0080] Based on the above embodiments, the target chip may include a radio frequency processing chip. The following embodiments will be described with respect to the target chip being a radio frequency processing chip.

[0081] Figure 10 This is a flowchart of another power supply control method provided in an embodiment of this application. This embodiment takes a radio frequency (RF) processing chip as an example, which includes a first storage module and a first processing module. The method is executed by a baseband processing chip, which can control the power supply to the first processing module and the first storage module based on the difference in the time interval between a first time period and a second time period. See [link to relevant documentation]. Figure 10 The method includes:

[0082] 1001. The baseband processing chip maintains power supply to the first processing module and the first storage module when the time interval is less than the first threshold.

[0083] In this embodiment of the application, during the wireless communication process, the radio frequency (RF) processing chip transmits and receives signals. However, in order to reduce power consumption, the RF processing chip does not continuously transmit and receive signals, but periodically enters a sleep state. In the sleep state, it does not transmit or receive signals. The RF processing chip can only transmit and receive signals after waking up from the sleep state. Moreover, before transmitting and receiving signals, it also needs to receive an SSB (Synchronization Signal Block) to perform pre-synchronization based on the received SSB.

[0084] To address this, the communication system introduced DRX (Discontinuous Reception) technology. The radio frequency processing chip periodically enters a sleep state. In the sleep state, the radio frequency processing chip does not listen to PDCCH subframes. After waking up from the sleep state, it then listens to PDCCH subframes. DRX is further divided into idle state and connected state.

[0085] The DRX mechanism in idle state is a paging mechanism. The RF processing chip in idle state can periodically wake up according to the DRX cycle and receive paging messages. See also... Figure 11 The DRX cycle is 1.28 seconds. The RF processing chip will wake up every 1.28 seconds and receive paging messages. In the first DRX cycle, the RF processing chip will wake up early and receive SSB.

[0086] Accordingly, the first task is to receive the synchronization signal block SSB, and the second task is to receive the paging message when the RF processing chip is in an idle state.

[0087] When the RF processing chip is in the connected state, see Figure 12 The DRX cycle includes a wake-up phase and a sleep phase. During the sleep phase, the RF processing chip is in a sleep state and does not listen to PDCCH subframes. After waking up from the sleep state, it enters the wake-up phase, where the RF processing chip resumes listening to PDCCH subframes. The longer the sleep state lasts, the lower the power consumption of the RF processing chip. Correspondingly, when the RF processing chip is in a connected state, its first task is to receive SSBs, and its second task is to switch from sleep state to wake-up state.

[0088] In this embodiment of the application, the first task is to receive SSB, and the first time period is the time period during which the radio frequency processing chip receives SSB.

[0089] The radio frequency (RF) processing chip includes a first storage module, which is used to load the firmware of the RF processing chip. When the baseband processing chip stops supplying power to the first storage module, the data in the first storage module will be lost. Therefore, after the baseband processing chip resumes supplying power to the first storage module, it needs to reload the firmware of the RF processing chip and perform initialization operations. The RF processing chip also includes a first processing module. Stopping and resuming power to the first processing module will also cause some power consumption, for example, the RF processing chip needs to load the firmware required for the first processing module to run. When this time interval is less than a first threshold, the power consumption caused by supplying power to the first processing module and the first storage module is relatively small. Therefore, to reduce power consumption, power can be maintained to the first processing module and the first storage module during this time interval. In this way, when the time period for receiving paging messages arrives in the idle state, or when the time period for switching from sleep state to wake-up state arrives in the connected state, the RF processing chip does not need to reload the firmware required for the first processing module to run, nor does it need to reload the firmware of the RF processing chip itself. Furthermore, the initialization operations are relatively simple, effectively saving power.

[0090] Optionally, the first threshold is 20 milliseconds, meaning that the baseband processing chip maintains power supply to the first processing module and the first storage module when the time interval is less than 20 milliseconds.

[0091] 1002. When the time interval is not less than a first threshold and less than a second threshold, the baseband processing chip stops supplying power to the first processing module and continues to supply power to the first storage module.

[0092] The radio frequency processing chip also includes a first processing module, which includes a high-speed interface, analog devices, and a processor. When the time interval is not less than a first threshold and less than a second threshold, after the first time interval, the baseband processing chip continues to supply power to the first storage module and stops supplying power to the first processing module.

[0093] If the power consumption of supplying power to the first processing module is too high when the time interval is not less than the first threshold and less than the second threshold, then power supply to the first processing module will be stopped to reduce power consumption. The power consumption of maintaining power supply to the first storage module is less than the power consumption of the RF processing chip loading its firmware into the first storage module and performing initialization operations. Therefore, to reduce power consumption, power supply to the first storage module can be maintained during this time interval. In this way, when the time period for receiving paging messages arrives in the idle state, or when the time period for switching from sleep to wake-up arrives in the connected state, power supply to the first processing module is restored. The RF processing chip can then load the firmware required for the first processing module to run into the first processing module, without needing to reload the RF processing chip's firmware into the first storage module, and the initialization operations performed by the RF processing chip will be simpler. Therefore, maintaining power supply to the first storage module but stopping power supply to the first processing module when the time interval is not less than the first threshold and less than the second threshold can effectively reduce power consumption.

[0094] Optionally, the second threshold is 40 milliseconds, meaning that when the time interval is between 20 milliseconds and 40 milliseconds, the baseband processing chip stops supplying power to the first processing module and continues to supply power to the first storage module.

[0095] It should be noted that, in the embodiments of this application, during the execution of steps 1001 or 1002 above, the power management chip continues to supply power to the radio frequency processing chip, but the power supply to a certain module can be stopped within the radio frequency processing chip. For example, when executing step 1002, the power management chip still supplies power to the radio frequency processing chip, but the power supply to the first processing module is stopped within the radio frequency processing chip.

[0096] 1003. When the time interval is not less than the second threshold, the baseband processing chip stops supplying power to the first processing module and the first storage module.

[0097] Specifically, when the time interval is not less than the second threshold, the power consumption caused by maintaining power to the first processing module is greater than the power consumption caused by the RF processing chip loading the firmware required for the first processing module to run into the first processing module, and the power consumption caused by maintaining power to the first storage module is also greater than the power consumption caused by reloading the firmware of the RF processing chip into the first storage module and performing initialization operations. Therefore, to reduce power consumption, power can be stopped for the first storage module and the first processing module during this time interval. Thus, when the time period for receiving paging messages arrives in the idle state, or the time period for switching from sleep to wake-up state arrives in the connected state, the RF processing chip loads the firmware required for the first processing module to run into the first processing module, loads the firmware of the RF processing chip into the first storage module, and performs initialization operations. The power consumption caused by this is less than the power consumption caused by maintaining power to the first storage module and the first processing module, effectively saving power.

[0098] Optionally, the second threshold is 40 milliseconds, meaning that the baseband processing chip stops supplying power to the first processing module and the first storage module when the time interval is greater than 40 milliseconds.

[0099] It should be noted that the baseband processing chip executes steps 1001-1003 of the above embodiment, and when executing step 1003, after the time period when the radio frequency processing chip receives the SSB, the baseband processing chip controls the power management chip to continue to supply power to the radio frequency processing chip, and controls the radio frequency processing chip to stop supplying power to the first storage module and the first processing module.

[0100] In this embodiment, the baseband processing chip can control the power supply to the first storage module and the first processing module in the radio frequency processing chip based on the time interval between the time period of receiving SSB in the idle state and the time period of receiving paging messages, or the time interval between the time period of receiving SSB in the connected state and the time period of switching from the sleep state to the wake-up state, which can effectively reduce the power consumption of the radio frequency processing chip.

[0101] It should be noted that the above embodiments take the baseband processing chip controlling the power supply of the radio frequency processing chip as an example. However, in practical applications, any chip can control the power supply of the radio frequency processing chip, and this application embodiment does not limit this.

[0102] The workflow for various scenarios is explained below:

[0103] Related technology: The RF processing chip stops supplying power after performing its task.

[0104] Figure 13 The display shows the processor voltage, processor current, high-speed interface current, and analog circuit current of the RF processing chip. These parameters reflect the power consumption of the RF processing chip.

[0105] See Figure 13 After power is supplied to the RF processing chip, the processor voltage and current rise, as does the high-speed interface current, in preparation for loading the RF processing chip's firmware via the high-speed interface. Once loading is complete, the high-speed interface current drops to zero, and initialization begins. The RF processing chip then receives downlink signals; at this point, the high-speed interface current, processor current, and analog circuit current all increase. After receiving the downlink data, the analog devices enter standby mode, and all currents except the RF processing chip's processor current drop to zero. Finally, power supply to the RF processing chip is stopped. The power-down process can be divided into internal power-down and power supply power-down. Internal power-down means that power is only supplied to one or more modules of the RF processing chip; the processor still has voltage. Power supply power-down means that power is stopped to the entire RF processing chip; the processor voltage is zero at this point.

[0106] exist Figure 13 Based on this, see the processor current and high-speed interface current for each time period. Figure 14 Where T1 is the time from the start of powering the RF processing chip to the start of high-speed interface preparation, approximately 1ms; T2 is the time for high-speed signal preparation and loading the RF processing chip firmware, approximately 2.5ms; T3 is the time for initialization operations, approximately 5.5ms; T4 is the time for the RF processing chip to receive downlink signals; T5 is the time for storing signals, approximately 3ms; T6 is the time for receiving the power-down signal and performing internal power-down. After T6, power supply to the entire RF processing chip stops. T1 + T2 + T3 = 9ms, meaning that it takes 9ms from the start of powering the RF processing chip to the RF processing chip starting normal operation, and approximately 3ms from the end of operation to the internal power-down.

[0107] The method provided in this application embodiment controls the power supply to the first storage module and the first processing module in the radio frequency processing chip based on the time interval between the time period for receiving SSBs in the idle state and the time interval for receiving paging messages, or the time interval between the time period for receiving SSBs in the connected state and the time interval for switching from the sleep state to the wake-up state. The following describes various scenarios provided in this application embodiment.

[0108] Scenario 1: The RF processing chip is in an idle state and continues to be powered after receiving the SSB:

[0109] See Figure 15Time period T1 is the period from the start of powering the RF processing chip to the start of high-speed interface preparation. During time period T1, the processor current increases. During time period T2, the high-speed interface is prepared and the firmware of the RF processing chip is loaded, causing the high-speed interface current to increase. During time period T3, initialization operations are performed, at which point the high-speed interface current drops to 0, but processor current still exists. During time period T4, the RF processing chip receives SSBs, at which point both the high-speed interface current and processor current increase. After receiving the SSB, the signal is stored during time period T5, at which point only processor current exists. If the time interval between the SSB reception period and the paging message reception period in the idle state is less than a first threshold, power is maintained to the first storage module and the first processing module in the RF processing chip during time period T6, at which point processor current still exists, but it is lower. Therefore, before the paging message reception period, i.e., during the subsequent time period T3, only a simple initialization operation is required, without reloading the RF processing chip firmware. During this time, the processor current increases, but the high-speed interface current remains 0. During time period T7, the RF processing chip receives paging messages, at which point both the high-speed interface current and processor current increase. After time period T7, the received signal is stored. At this point, the high-speed interface current is 0, but processor current still exists. After storage is complete, power supply to the RF processing chip is stopped.

[0110] The second scenario: The RF processing chip is in an idle state and stops supplying power after receiving the SSB.

[0111] See Figure 16 Time period T1 is the period from the start of powering the RF processing chip to the start of high-speed interface preparation. During time period T1, the processor current increases. During time period T2, the high-speed interface is prepared and the firmware of the RF processing chip is loaded, causing the high-speed interface current to increase. During time period T3, initialization is performed, at which point the high-speed interface current drops to 0, but the processor current remains. During time period T4, the RF processing chip receives the SSB, at which point both the high-speed interface current and the processor current increase. After receiving the SSB, the signal is stored during time period T5, at which point only the processor current remains. If the time interval between the SSB reception period and the paging message reception period in the idle state is not less than the second threshold, power supply to the first storage module and the first processing module in the RF processing chip is stopped during time period T6. Therefore, before the paging message reception period, i.e., during time period T2, the firmware of the RF processing chip needs to be reloaded, at which point both the processor current and the high-speed interface current increase. During time period T3, initialization is performed, at which point the high-speed interface current drops to 0, but the processor current remains. During time period T7, the RF processing chip receives the paging message, at which point both the high-speed interface current and the processor current increase. After the T7 time period, power supply to the first storage module and the first processing module in the radio frequency processing chip is stopped.

[0112] The third scenario: The RF processing chip is in a connected state and continues to be powered after receiving the SSB:

[0113] See Figure 17 Time period T1 is the period from the start of powering the RF processing chip to the start of high-speed interface preparation. During time period T1, the processor current increases. During time period T2, the high-speed interface is prepared and the firmware of the RF processing chip is loaded, causing the high-speed interface current to increase. During time period T3, initialization is performed, at which point the high-speed interface current drops to 0, but processor current still exists. During time period T4, the RF processing chip receives the SSB, at which point both the high-speed interface current and processor current increase. After receiving the SSB, the signal is stored during time period T5, at which point only processor current exists. If the time interval between the SSB reception period in connected state and the time period for switching from sleep state to wake-up state is less than a first threshold, power is maintained to the first storage module and the first processing module in the RF processing chip during time period T6. At this time, processor current still exists, but it is lower. Therefore, before the time period for switching from sleep state to wake-up state, i.e., during time period T3, only a simple initialization operation is required, without reloading the firmware of the RF processing chip. During this time, the processor current increases, but the high-speed interface current remains 0. During time period T7, the RF processing chip switches from sleep mode to wake-up mode and begins listening to PDCCH subframes. At this time, both the high-speed interface current and the processor current increase. After time period T7, the received signal is stored. At this point, the high-speed interface current is 0, but the processor current still exists. After storage is complete, power supply to the first storage module and the first processing module in the RF processing chip is stopped.

[0114] The fourth scenario: The RF processing chip is in a connected state and stops supplying power after receiving the SSB.

[0115] See Figure 18Time period T1 is the period from the start of powering the RF processing chip to the start of high-speed interface preparation. During time period T1, the processor current increases. During time period T2, the high-speed interface is prepared and the firmware of the RF processing chip is loaded, causing the high-speed interface current to increase. During time period T3, initialization is performed, at which point the high-speed interface current drops to 0, but the processor current remains. During time period T4, the RF processing chip receives the SSB, at which point both the high-speed interface current and the processor current increase. After receiving the SSB, the signal is stored during time period T5, at which point only the processor current remains. If the time interval between the SSB reception period in connected state and the time period for switching from sleep state to wake-up state is not less than the second threshold, power supply to the first storage module and the first processing module in the RF processing chip is stopped during time period T6. Therefore, before the time period for switching from sleep state to wake-up state, i.e., during time period T2, the firmware of the RF processing chip needs to be reloaded, at which point both the processor current and the high-speed interface current increase. During time period T3, initialization is performed, at which point the high-speed interface current drops to 0, but the processor current remains. During time period T7, the RF processing chip switches from sleep mode to wake-up mode and begins listening to PDCCH subframes. At this time, both the high-speed interface current and the processor current increase. After time period T7, power supply to the first storage module and the first processing module in the RF processing chip is stopped.

[0116] Using the method described in this application, experiments were conducted on two power supply methods—one with power supply maintained and the other with power supply stopped—while the radio frequency processing chip was in an idle state. The resulting power consumption of each method can be determined. Figure 15 and Figure 16 Based on the above two power supply methods, the power consumption of the RF processing chip in the time periods T5, T6 and T2 are shown in Table 1.

[0117] Table 1

[0118] Power supply method T5 T6 T2 Keep power supply 15 6 0 Power outage 15 0 15

[0119] Referring to Table 1, with power maintained, the power consumption during time period T5 is 15, and during time period T6, the power consumption caused by maintaining power is 6. Since the firmware of the RF processing chip does not need to be reloaded while power is maintained, the power consumption during time period T2 is 0. With power off, the power consumption during time period T5 is 15, and during time period T6, the power consumption is 0. During time period T2, the power consumption caused by reloading the firmware of the RF processing chip is 15. T5 is 3ms, T6 is the specific time period for power supply or power off (denoted by x), and T2 is 2.5ms. Therefore, the difference between the power consumption caused by power off and power maintained during time periods T5, T6, and T2 is 37.5 - 6x. Thus, the power supply to the RF processing chip can be controlled based on the total duration of time periods T5, T6, and T2 to optimize the power consumption of the RF processing chip to the greatest extent.

[0120] The above embodiments are only illustrated using radio frequency processing chips as an example. For baseband processing chips or other related chips, the power supply control method provided in the above embodiments can also be used, and the specific process will not be repeated.

[0121] It should be noted that when the target chip is a baseband processing chip, the baseband processing chip also includes a control module. The control module can use the method provided in the above embodiments to control the power supply of the first processing module and the first storage module in the baseband processing chip according to the time interval between the first time period and the second time period.

[0122] Optionally, the first time period is the time period during which the baseband processing chip processes the SSB sent by the radio frequency processing chip, and the second time period is the time period during which the baseband processing chip processes the paging message sent by the radio frequency processing chip.

[0123] Optionally, the first storage module in the baseband processing chip stores the firmware of the radio frequency (RF) processing chip, and the second storage module stores the firmware of the baseband processing chip. Powering the first storage module may consume power, resulting in some power consumption. If power to the first storage module is stopped, the baseband processing chip needs to reload the RF processing chip's firmware to the first storage module after power is restored, so that the RF processing chip can load the firmware from the first storage module and perform initialization operations. Therefore, if the time interval between the first and second time periods is not less than a second threshold, the control module loads the data stored in the first storage module into the second storage module and then stops powering the first storage module. After power is restored to the first storage module, the control module loads the data from the second storage module into the first storage module, so that the RF processing chip can load the firmware from the first storage module and perform initialization operations.

[0124] It should be noted that while the control module controls the power supply of the first processing module and the first storage module in the baseband processing chip according to the time interval between the first time period and the second time period, the power management chip continues to supply power to the baseband processing chip. However, the baseband processing chip can control the cessation of power supply to the first storage module and the first processing module.

[0125] The following are embodiments of the apparatus described in this application, which can be used to execute the embodiments of the method described in this application. For details not disclosed in the apparatus embodiments of this application, please refer to the embodiments of the method described in this application.

[0126] Please refer to Figure 19 The diagram illustrates a structural block diagram of a power supply control device provided in an exemplary embodiment of this application, the power supply control device comprising:

[0127] The control module 1901 is used to control the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period, wherein the first time period is the time period for executing the first task, the second time period is the time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to execute the first task and the second task by accessing the first storage module.

[0128] In one possible implementation, the target chip includes a radio frequency processing chip.

[0129] In one possible implementation, the first task is to receive the synchronization signal block SSB, and the second task is to receive the paging message when the RF processing chip is in an idle state; or, when the RF processing chip is in a connected state, the second task is to switch from a sleep state to a wake-up state.

[0130] In one possible implementation, the control module 1901 is a baseband processing chip.

[0131] In one possible implementation, the target chip includes a baseband processing chip.

[0132] In one possible implementation, the baseband processing chip includes a control module 1901.

[0133] In one possible implementation, the control module 1901 includes:

[0134] The first control unit is configured to maintain power supply to the first processing module and the first storage module when the time interval is less than a first threshold.

[0135] Alternatively, the second control unit is configured to stop supplying power to the first processing module and maintain power supply to the first storage module when the time interval is not less than a first threshold and less than a second threshold.

[0136] Alternatively, a third control unit may be used to stop supplying power to the first processing module and the first storage module when the time interval is not less than a second threshold.

[0137] In one possible implementation, the first threshold is 20 milliseconds and the second threshold is 40 milliseconds.

[0138] In one possible implementation, the third control unit is used for:

[0139] If the time interval is not less than the second threshold, after loading the data stored in the first storage module into the second storage module, the power supply to the first storage module is stopped.

[0140] In one possible implementation, the device further includes:

[0141] The loading module is used to load data from the second storage module into the first storage module after power is restored to the first storage module.

[0142] It should be noted that the power supply control device provided in the above embodiments is only illustrated by the division of the above functional modules. In actual applications, the above functions can be assigned to different functional modules as needed, that is, the internal structure of the terminal can be divided into different functional modules to complete all or part of the functions described above. In addition, the power supply control device and the power supply control method embodiments provided in the above embodiments belong to the same concept, and the specific implementation process can be found in the method embodiments, which will not be repeated here.

[0143] This application also provides a power supply control system, including a control module, a first processing module for the target chip, and a first storage module for the target chip:

[0144] The control module is used to control the power supply of the first processing module and the first storage module in the target chip according to the time interval between the first time period and the second time period, wherein the first time period is the time period for executing the first task, the second time period is the time period for executing the second task, the first storage module is used to store the firmware of the target chip, and the first processing module is used to execute the first task and the second task by accessing the first storage module.

[0145] Optionally, the power supply control system also includes a power management chip.

[0146] Optionally, the control module is used to control the power supply of the first processing module and the first storage module of the target chip through the control power management chip.

[0147] Optionally, the target chip may include a radio frequency processing chip.

[0148] Optionally, the first task is to receive the synchronization signal block SSB, and the second task is to receive the paging message when the radio frequency processing chip is in an idle state.

[0149] Alternatively, when the RF processing chip is in a connected state, the second task is to switch from a sleep state to a wake-up state.

[0150] Optionally, the control module is a baseband processing chip.

[0151] Optionally, the target chip includes a baseband processing chip.

[0152] Optionally, the baseband processing chip includes a control module.

[0153] The specific functions of the control module, target chip, and power management chip are as shown in the embodiments of the power supply control method described above, and will not be repeated here.

[0154] This application also provides a control module, which includes a processor for implementing the power supply control method shown in the above embodiments.

[0155] This application also provides a terminal that includes the control module shown in the above embodiments.

[0156] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0157] Those skilled in the art will understand that all or part of the steps in the methods of the above embodiments can be implemented by hardware, or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk. The above descriptions are merely optional embodiments of this application and are not intended to limit the application. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of this application should be included within the protection scope of this application.

Claims

1. A power supply control method characterized by, The method comprises: acquiring a time interval between a first time period and a second time period, the first time period being a time period for performing a first task, the second time period being a time period for performing a second task, the first task being receiving a synchronization signal block (SSB), and the second task being receiving a paging message in a case where a target chip is in an idle state, or the second task being switching from a sleep state to a wake-up state in a case where the target chip is in a connected state; in a case where the time interval is less than a first threshold value, keeping power supply to a first processing module and a first storage module, the first storage module being configured to store firmware of the target chip, and the first processing module being configured to perform the first task and the second task by accessing the first storage module, the first storage module needing to reload the firmware of the target chip after being powered off and then powered on again; in a case where the time interval is not less than the first threshold value and is less than a second threshold value, stopping power supply to the first processing module and keeping power supply to the first storage module; in a case where the time interval is not less than the second threshold value, stopping power supply to the first processing module, loading data stored in the first storage module to a second storage module, and then stopping power supply to the first storage module; after resuming power supply to the first storage module, loading data of the second storage module to the first storage module.

2. The method of claim 1, wherein, The target chip comprises a radio frequency processing chip.

3. The method of claim 2, wherein, The method further comprises: controlling, by a baseband processing chip, power supply of the first processing module and the first storage module in the radio frequency processing chip according to the time interval.

4. The method of claim 1, wherein, The target chip comprises a baseband processing chip.

5. The method of claim 4, wherein, The baseband processing chip comprises a control module, and the method further comprises: controlling, by the control module, power supply of the first processing module and the first storage module in the baseband processing chip according to the time interval.

6. The method of claim 1, wherein, The first threshold value is 20 milliseconds, and the second threshold value is 40 milliseconds.

7. A power supply control device characterized by comprising: The apparatus comprises: The control module is configured to obtain a time interval between a first time period and a second time period, the first time period is a time period for performing a first task, the second time period is a time period for performing a second task, the first task is receiving a synchronization signal block (SSB), and the second task is receiving a paging message in a case where the target chip is in an idle state; or the second task is switching from a sleep state to a wake-up state in a case where the target chip is in a connected state; in a case where the time interval is less than a first threshold, maintaining power supply to a first processing module and a first storage module, the first storage module is configured to store firmware of the target chip, the first processing module is configured to perform the first task and the second task by accessing the first storage module, and the first storage module needs to reload the firmware of the target chip after being powered off and powered on again; in a case where the time interval is not less than the first threshold and is less than a second threshold, stopping power supply to the first processing module and maintaining power supply to the first storage module; in a case where the time interval is not less than the second threshold, stopping power supply to the first processing module, stopping power supply to the first storage module after loading data stored in the first storage module to a second storage module; and loading data of the second storage module to the first storage module after resuming power supply to the first storage module.

8. A power supply control system characterized by comprising: The power supply control system comprises a control module, a first processing module of a target chip, and a first storage module of the target chip. The control module is configured to obtain a time interval between a first time period and a second time period; in a case where the time interval is less than a first threshold, maintaining power supply to a first processing module and a first storage module; in a case where the time interval is not less than the first threshold and is less than a second threshold, stopping power supply to the first processing module and maintaining power supply to the first storage module; in a case where the time interval is not less than the second threshold, stopping power supply to the first processing module, stopping power supply to the first storage module after loading data stored in the first storage module to a second storage module; and loading data of the second storage module to the first storage module after resuming power supply to the first storage module, wherein the first time period is a time period for performing a first task, the second time period is a time period for performing a second task, the first task is receiving a synchronization signal block (SSB), and the second task is receiving a paging message in a case where the target chip is in an idle state; or the second task is switching from a sleep state to a wake-up state in a case where the target chip is in a connected state, the first storage module is configured to store firmware of the target chip, and the first processing module is configured to perform the first task and the second task by accessing the first storage module, and the first storage module needs to reload the firmware of the target chip after being powered off and powered on again.

9. The power supply control system of claim 8, wherein, The power supply control system further comprises a power management chip.

10. The power supply control system of claim 9, wherein, The control module is configured to control the power supply management chip to control power supply of the first processing module of the target chip and the first storage module of the target chip.

11. The power supply control system of claim 8, wherein, The target chip comprises a radio frequency processing chip.

12. The power supply control system of claim 11, wherein, The control module is a baseband processing chip.

13. The power supply control system of claim 8, wherein, The target chip comprises a baseband processing chip.

14. The power supply control system of claim 13, wherein, The baseband processing chip comprises the control module.

15. A control module, characterized by The control module comprises a processor configured to implement the power supply control method according to any one of claims 1 to 6.

16. A terminal, characterized by The terminal comprises the control module according to claim 15.

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