Semiconductor memory structure and method of making same, and semiconductor memory

Abstract

The embodiment of the present disclosure provides a semiconductor storage structure and a preparation method thereof and a semiconductor memory, and the semiconductor storage structure comprises: a substrate; a write transistor arranged on the substrate, the write transistor comprising a first indium gallium zinc oxide structure extending along a first direction, the first direction being a direction perpendicular to a top surface of the substrate; a storage node arranged on the write transistor and embedded in an end portion of the first indium gallium zinc oxide structure; and a read transistor arranged on the storage node, the read transistor comprising a second indium gallium zinc oxide structure arranged on the storage node and insulated from the storage node, and the storage node serving as a gate of the read transistor. The above technical solution uses the crown-shaped storage node embedded in the end portion of the first indium gallium zinc oxide structure, thereby expanding the contact area, making the conduction efficiency higher and the performance of the transmitted signal more stable.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor memory, and more particularly to a semiconductor memory structure, a method for fabricating the same, and a semiconductor memory. Background Technology

[0002] Unlike conventional Dynamic Random Access Memory (DRAM), which consists of transistors and capacitors, 2T0C DRAM consists of two transistors and no capacitors. Given a certain size (and appropriate doping), small transistors can also store charge without any capacitors. Embedding DRAM into processor chips has been commercialized, but it has its limitations.

[0003] Metal oxide materials, such as indium gallium zinc oxide (IGZO), are typically used as amorphous materials for 2T0C DRAMs. IGZO has advantages such as the ability to drive large currents and faster write speeds. In addition, it leaks very little charge when off, resulting in longer bit lifetimes. However, IGZO requires multiple etching processes during fabrication, thus leading to over-etching issues.

[0004] Therefore, how to improve the etching process of metal oxide materials, increase the integration density of 2T0C DRAM, reduce manufacturing costs, and improve chip quality are problems that need to be solved at present. Summary of the Invention

[0005] This disclosure provides a semiconductor memory structure, a method for fabricating the same, and a semiconductor memory, which can improve the etching process of metal oxide materials, increase the integration density of 2T0C DRAM, reduce fabrication costs, and improve chip quality.

[0006] This disclosure provides a semiconductor memory structure, including: a substrate; a write transistor disposed on the substrate, the write transistor including a first indium gallium zinc oxide structure extending along a first direction, the first direction being a direction perpendicular to the top surface of the substrate; a memory node disposed on the write transistor and fitted into an end of the first indium gallium zinc oxide structure; and a read transistor disposed on the memory node, the read transistor including a second indium gallium zinc oxide structure disposed on the memory node and insulated from the memory node, the memory node serving as the gate of the read transistor.

[0007] In one embodiment, the cross-section of the second indium gallium zinc oxide structure is circular.

[0008] In one embodiment, the write transistor includes: a write bit line disposed on the surface of the substrate and extending along a second direction, the second direction being parallel to the top surface of the substrate, and a first indium gallium zinc oxide structure disposed on the surface of the write bit line; a first isolation layer disposed on the surface of the write bit line and surrounding a portion of the first indium gallium zinc oxide structure; a write word line disposed on the surface of the first isolation layer and extending along a third direction, the write word line surrounding a portion of the first indium gallium zinc oxide structure, the second direction being parallel to the top surface of the substrate, and the second direction intersecting the third direction; a first gate dielectric layer disposed between the write word line and the first indium gallium zinc oxide structure; a second isolation layer disposed on the surface of the write word line, and the memory node disposed on the surface of the second isolation layer.

[0009] In one embodiment, the semiconductor memory structure includes a plurality of write transistors arranged in an array along a second direction and a third direction, wherein adjacent write transistors in the second direction share the same write bit line, and adjacent write transistors in the third direction share the same write word line.

[0010] In one embodiment, the read transistor includes: a second gate dielectric layer disposed on the surface of the memory node, and a second indium gallium zinc oxide structure disposed on the second gate dielectric layer; a read word line disposed on the surface of the second indium gallium zinc oxide structure; and a read bit line disposed on the surface of the second indium gallium zinc oxide structure, wherein the read bit line and the read word line are independent of each other.

[0011] In one embodiment, the semiconductor memory structure includes a plurality of read transistors arranged in an array along a second direction and a third direction, wherein adjacent read transistors in the second direction share the same read bit line, and adjacent read transistors in the third direction share the same read word line.

[0012] In one embodiment, the read word line is located at the boundary region of two adjacent read transistors in the second direction, and the two adjacent read transistors in the second direction share the same read word line; the read bit line is located at the boundary region of two adjacent read transistors in the second direction, and the two adjacent read transistors in the second direction share the same read bit line, and the read word line and the read bit line are alternately arranged.

[0013] This disclosure provides a method for fabricating a semiconductor memory structure, comprising the following steps: providing a substrate; forming a write transistor on the surface of the substrate, the write transistor including a first indium gallium zinc oxide structure extending along a first direction, the first direction being a direction perpendicular to the top surface of the substrate; forming a memory node on the surface of the write transistor, the memory node being fitted into the end of the first indium gallium zinc oxide structure; forming a read transistor on the surface of the memory node, the read transistor including a second indium gallium zinc oxide structure, the second indium gallium zinc oxide structure being disposed on the memory node and insulated from the memory node, the memory node serving as the gate of the read transistor.

[0014] In one embodiment, the step of forming a write transistor on the substrate surface includes: forming a plurality of write bit lines on the substrate surface, the write bit lines extending along a second direction and the plurality of write bit lines being spaced apart along a third direction; forming a patterned sacrificial layer on the surface of the write bit lines, the sacrificial layer having a plurality of arrayed first holes, the first holes exposing the write bit lines; filling the first holes with indium gallium zinc oxide to form a first indium gallium zinc oxide structure; removing a portion of the sacrificial layer, the sacrificial layer remaining between the first indium gallium zinc oxide structures serving as a first isolation layer; forming a first gate dielectric layer on the surface of the first indium gallium zinc oxide structure; forming a plurality of write word lines spaced apart along the second direction on the surface of the first isolation layer and the surface of the first gate dielectric layer, the write word lines surrounding the first indium gallium zinc oxide structure and extending along a third direction; and forming a second isolation layer on the surface of the write word lines.

[0015] In one embodiment, forming multiple write bit lines on the substrate surface further includes the following steps: growing a first insulating layer on the substrate surface; etching a first channel along a first direction on the surface of the first insulating layer; and forming a first conductive layer in the first channel as the write bit line.

[0016] In one embodiment, forming a patterned sacrificial layer on the surface of the write bit line further includes the following steps: forming a first nitride layer on the surface of the write bit line and the first insulating layer; forming a first dielectric layer spaced apart along the third direction within the first nitride layer, the first dielectric layer contacting the first insulating layer; forming a second dielectric layer spaced apart along the second direction within the first nitride layer, the first dielectric layer and the second dielectric layer intersecting to form the sacrificial layer; etching back the first nitride layer to expose the write bit line, the first dielectric layer and the second dielectric layer defining the first hole.

[0017] In one embodiment, after the step of forming a plurality of independent first indium gallium zinc oxide structures, the method further includes the step of polishing the first indium gallium zinc oxide structures to form rounded corners.

[0018] In one embodiment, forming a patterned sacrificial layer on the surface of the write bit line further includes the following steps: forming a first dielectric layer on the surfaces of the first conductive layer and the first insulating layer; etching the first dielectric layer to form the first hole.

[0019] In one embodiment, forming a plurality of writing lines spaced apart along a second direction on the surface of the first isolation layer further includes the following steps: forming a second conductive layer between the first indium gallium zinc oxide structures; forming a fourth insulating layer between the first indium gallium zinc oxide structures, the fourth insulating layer covering the second conductive layer; etching the fourth insulating layer, the second conductive layer, and the first isolation layer along the third direction to form a second channel; forming a third dielectric layer within the second channel, such that the second conductive layer is separated to form the writing lines, wherein the retained portion of the fourth insulating layer and the third dielectric layer constitute the second isolation layer.

[0020] In one embodiment, forming a memory node on the surface of the write transistor further includes the following steps: forming a third insulating layer on the surface of the second isolation layer; etching the third insulating layer and a portion of the second isolation layer to form an array of second holes, the bottom of which exposes a portion of the first indium gallium zinc oxide structure, and the second holes are circular holes; forming a memory node in the second holes, the memory node being fitted into the end of the first indium gallium zinc oxide structure.

[0021] In one embodiment, forming a read transistor on the surface of the memory node further includes the following steps: forming a second gate dielectric layer on the surface of the memory node; filling the second hole with indium gallium zinc oxide to form a second indium gallium zinc oxide structure; and forming a plurality of read word lines and read bit lines on the surface of the second indium gallium zinc oxide structure, wherein the read word lines and the read bit lines are independent of each other.

[0022] In one embodiment, forming read words and read bits on the surface of the second indium gallium zinc oxide structure further includes: forming a patterned fourth insulating layer on the surface of the second indium gallium zinc oxide structure, the fourth insulating layer having a third channel extending along the third direction, each third channel exposing the boundary region of two adjacent columns of the second indium gallium zinc oxide structure; forming a third conductive layer within the third channel as the read word; forming a fifth insulating layer on the surface of the fourth insulating layer; etching the fourth insulating layer and the fifth insulating layer to form an array of third holes, each third hole exposing the boundary region of two adjacent columns of the second indium gallium zinc oxide structure, and the third hole being located between two read words; forming a fourth conductive layer within the third hole as a read bit connection structure; forming a patterned sixth insulating layer on the surface of the fifth insulating layer, the sixth insulating layer having a fourth channel extending along the second direction; forming a fifth conductive layer within the fourth channel as the read bit.

[0023] In one embodiment, forming read words and read bits on the surface of the second indium gallium zinc oxide structure further includes: forming a patterned fourth insulating layer on the surface of the second indium gallium zinc oxide structure, the fourth insulating layer having a third channel extending along the third direction, each third channel exposing one side of a row of the second indium gallium zinc oxide structures; forming a third conductive layer within the fifth channel as the read words; forming a fifth insulating layer on the surface of the fourth insulating layer; etching the fourth and fifth insulating layers to form an array of third holes, each third hole exposing the other side of the second indium gallium zinc oxide structure; forming a fourth conductive layer within the third holes as a read bit connection structure; forming a patterned sixth insulating layer on the surface of the fifth insulating layer, the sixth insulating layer having a fourth channel extending along the second direction; and forming a fifth conductive layer within the fourth channel as the read bits.

[0024] This disclosure provides a semiconductor memory, including one or more stacked semiconductor memory structures.

[0025] The above technical solution, by employing a crown-shaped storage node embedded at the end of the first indium gallium zinc oxide structure, ensures that the storage node contacts both the top and sides of the first indium gallium zinc oxide structure, thereby increasing the contact area, resulting in higher conductivity and more stable signal transmission performance. It also enhances structural stability, making the chip more durable.

[0026] Furthermore, this solution optimizes the fabrication process of the read transistor. When forming the second indium gallium zinc oxide structure, holes are directly etched on the oxide layer and then filled with the memory node and the second indium gallium zinc oxide structure. Compared with the existing technology that forms a sacrificial layer on the memory node and fills it with indium gallium zinc oxide, this reduces the step of etching back the sacrificial layer and avoids corrosion of the second gate dielectric layer, indium gallium zinc oxide and memory node when etching back the sacrificial layer. Attached Figure Description

[0027] Appendix Figure 1 The diagram shown is a circuit diagram of a 2T0C DRAM in the prior art.

[0028] Appendix Figure 2A The diagram shown is a schematic representation of an embodiment of the semiconductor memory structure described in this disclosure.

[0029] Appendix Figure 2B The diagram shown is a schematic representation of a second embodiment of the semiconductor memory structure described in this disclosure.

[0030] Appendix Figure 3 The diagram shows a step-by-step illustration of an embodiment of the method for fabricating the semiconductor memory structure described in this disclosure.

[0031] Appendix Figure 4A -Appendix Figure 4W This is a schematic diagram of the process structure of one embodiment of the method for fabricating the semiconductor memory structure described in this disclosure.

[0032] Appendix Figure 5 The diagram shown is a structural schematic of an embodiment of the semiconductor memory described in this disclosure. Detailed Implementation

[0033] The semiconductor memory structure and its fabrication method, as well as specific embodiments of the semiconductor memory, provided in this disclosure will be described in detail below with reference to the accompanying drawings. In detailing the embodiments of this application, for ease of explanation, the schematic diagrams may be partially enlarged without adhering to general proportions, and these schematic diagrams are merely examples and should not limit the scope of protection of this application. Furthermore, in actual fabrication, the three-dimensional spatial dimensions of length, width, and depth should be included.

[0034] Appendix Figure 1The diagram shows a circuit diagram of a 2T0C DRAM. The 2T0C DRAM includes a first transistor and a second transistor. The control terminal of the first transistor is connected to the write word line (WWL), the source of the first transistor is connected to the write bit line (WBL), the drain of the first transistor is connected to the control terminal of the second transistor, the source of the second transistor is connected to the read bit line, and the drain of the second transistor is connected to the read word line. With a certain size (and appropriate doping), small transistors can also store charge without any capacitor; charge stored on the gate of the transistor indicates that current can flow there. Since writing and reading involve different devices, data can be read from the 2T0C DRAM cell without erasing and rewriting data. When there is charge on the gate of the transistor, it indicates that current is flowing, and the transistor is turned on; when there is no charge on the gate, it indicates that no current is flowing, and the transistor is turned off.

[0035] Metal oxide materials, such as indium gallium zinc oxide (IGZO), are commonly used as amorphous materials for 2T0C DRAMs. IGZO offers advantages such as the ability to drive large currents and faster write speeds. Furthermore, it leaks very little charge when off, resulting in longer bit lifetimes. However, the fabrication process requires multiple etching steps for IGZO. On one hand, dry etching equipment is very expensive to maintain, including the main body, external gas supply system, chlorine-containing waste gas treatment, and power consumption, and it also suffers from problems such as particulate contamination and short equipment lifespan. On the other hand, because wet etching is isotropic, it suffers from lateral over-etching under the mask.

[0036] Therefore, the present invention provides a semiconductor memory structure and its fabrication method to improve the above-mentioned problems.

[0037] Appendix Figure 2AThe diagram shows a schematic representation of an embodiment of the semiconductor memory structure disclosed herein. The semiconductor memory structure includes: a substrate 200; a write transistor 210 disposed on the substrate 200, the write transistor 210 including a first indium gallium zinc oxide structure 211 extending along a first direction D1, the first direction D1 being perpendicular to the top surface of the substrate 200; a memory node 220 disposed on the write transistor 210 and fitted into the end of the first indium gallium zinc oxide structure 211; and a read transistor 230 disposed on the memory node 220, the read transistor 230 including a second indium gallium zinc oxide structure 231 disposed on the memory node 220 and insulated from the memory node 220, the memory node 220 serving as the gate of the read transistor 230. The storage node 220 is crown-shaped and fitted into the end of the first indium gallium zinc oxide structure 211, so that the storage node 220 makes contact with the top and sides of the first indium gallium zinc oxide structure 211, thereby increasing the contact area, improving conductivity, and making the signal transmission performance more stable. At the same time, it increases the stability of the structure, making the chip more durable.

[0038] The substrate 200 can be made of single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the substrate 200 is made of single-crystal silicon (Si).

[0039] In this embodiment, the write transistor 210 further includes: a write bit line 212 disposed on the surface of the substrate 200 and extending along a second direction D2, the second direction D2 being parallel to the top surface of the substrate 200; a first indium gallium zinc oxide structure 211 disposed on the surface of the write bit line 212; a first isolation layer 213 disposed on the surface of the write bit line 212 and surrounding a portion of the first indium gallium zinc oxide structure 211; and a write word line 214 disposed on the surface of the first isolation layer 213 and extending along a third direction D3. Word line 214 surrounds a portion of the first indium gallium zinc oxide structure 211. The second direction D2 is parallel to the top surface of the substrate 200 and intersects with the third direction D3. A first gate dielectric layer (not shown) is disposed between the write word line 214 and the first indium gallium zinc oxide structure 211, insulating the write word line 214 from the first indium gallium zinc oxide structure 211. A second isolation layer 215 is disposed on the surface of the write word line 214, and the memory node 220 is disposed on the surface of the second isolation layer 215. The memory node 220 serves not only as the drain of the write transistor 210 but also as the gate of the read transistor 230, acting as a connection node between the write transistor 210 and the read transistor 230.

[0040] As a specific embodiment, the semiconductor memory structure disclosed herein includes a plurality of write transistors 210 arranged in an array along a second direction D2 and a third direction D3. Adjacent write transistors 210 in the second direction D2 share the same write bit line 212, and adjacent write transistors 210 in the third direction D3 share the same write word line 214.

[0041] In this embodiment, the read transistor 230 includes: a second gate dielectric layer (not shown) disposed on the surface of the memory node 220, and a second indium gallium zinc oxide structure 231 disposed on the second gate dielectric layer; a read word line 232 disposed on the surface of the second indium gallium zinc oxide structure 231; and a read bit line 233 disposed on the surface of the second indium gallium zinc oxide structure 231, wherein the read bit line 233 and the read word line 232 are independent of each other. In other embodiments, the read bit line 233 may be disposed on the surface of the second indium gallium zinc oxide structure 231, and the read word line may be disposed on the surface of the second indium gallium zinc oxide structure 231, and the read word line may be connected to the second indium gallium zinc oxide structure through a read word line connection structure.

[0042] As a specific embodiment, the semiconductor memory structure includes a plurality of read transistors 230 arranged in an array along a second direction D2 and a third direction D3. Adjacent read transistors 230 in the second direction D2 share the same read bit line 233, and adjacent read transistors 230 in the third direction D3 share the same read word line 232.

[0043] In one specific embodiment, the read word line 232 is located at the boundary region of two adjacent read transistors 230 in the second direction D2, and two adjacent read transistors 226 in the second direction D2 share the same read word line 232; the read bit line 233 is located at the boundary region of two adjacent read transistors 230 in the second direction D2, and two adjacent read transistors 230 in the second direction D2 share the same read bit line 233, and the read word line 232 and the read bit line 233 are alternately arranged. Figure 2A As shown, the first read transistor 241 and the second read transistor 242 share the first read bit line 248; the second read transistor 242 and the third read transistor 243 share the first read word line 249. In this embodiment, the wiring method of two transistors sharing a read word line 232 or a read bit line 233 can reduce the number of wires, reduce costs and operational difficulty.

[0044] In other embodiments, adjacent read transistors 230 may not share the read bit line 233 and the read word line 232, for example, as shown in the attached figure. Figure 2B As shown, the read word line 232 is located on one side of the read transistor 230 along the second direction D2, and the read transistor 230 on the second direction D2 independently uses the read word line 232; the read bit line 233 is located on the other side of the read transistor 230 along the second direction D2, and the read transistor 230 on the second direction D2 independently uses the read bit line 233. This embodiment adopts a wiring method of independent transistor wiring to reduce signal interference between adjacent transistors 230 during operation. The independent use of word lines and bit lines by adjacent transistors can improve the read and write efficiency of the 2T0C transistor. The above technical solution, by using the crown-shaped memory node 220, is embedded in the end of the first indium gallium zinc oxide structure 211, so that the memory node 220 has contact with the top and sides of the first indium gallium zinc oxide structure 211, expanding the contact area, making the conduction efficiency higher and the signal transmission performance more stable. At the same time, it increases the stability of the structure and makes the chip more durable.

[0045] In this embodiment, the cross-section of the second indium gallium zinc oxide structure 231 on the plane extending along the first direction D1 and the second direction D2 is circular. The second indium gallium zinc oxide structure 231 can provide a more sufficient contact area, further ensuring good conductivity.

[0046] This disclosure also provides a method for fabricating the above-described semiconductor memory structure, with appended... Figure 3 The diagram illustrates the steps of an embodiment of the semiconductor memory structure fabrication method of the present disclosure, including the following steps: Step S31, providing a substrate; Step S32, forming a write transistor on the surface of the substrate, the write transistor including a first indium gallium zinc oxide structure extending along a first direction, the first direction being perpendicular to the top surface of the substrate; Step S33, forming a memory node on the surface of the write transistor, the memory node being fitted into the end of the first indium gallium zinc oxide structure; Step S34, forming a read transistor on the surface of the memory node, the read transistor including a second indium gallium zinc oxide structure, the second indium gallium zinc oxide structure being disposed on the memory node and insulated from the memory node, the memory node serving as the gate of the read transistor.

[0047] Appendix Figure 4A -Appendix Figure 4W This is a schematic diagram of the process structure of one embodiment of the method for fabricating the semiconductor memory structure described in this disclosure.

[0048] Refer to step S31 and appendix Figure 4A A substrate 200 is provided. The material of the substrate 200 can be single-crystal silicon (Si), single-crystal germanium (Ge), or silicon-germanium (GeSi), silicon carbide (SiC); it can also be silicon-on-insulator (SOI), germanium-on-insulator (GOI); or it can be other materials, such as gallium arsenide or other group III-V compounds. In this embodiment, the material of the substrate 200 is single-crystal silicon (Si).

[0049] Refer to step S32 and appendix Figure 4M A write transistor 210 is formed on the surface of the substrate 200. The write transistor 210 includes a first indium gallium zinc oxide structure 211 extending along a first direction D1, where the first direction D1 is perpendicular to the top surface of the substrate 200.

[0050] Please refer to the attached document. Figure 4D ~Attached Figure 4M As a specific embodiment, this disclosure provides a method for forming a write transistor 210 on the surface of the substrate 200, comprising the following steps: Figure 4D As shown, multiple write bit lines 212 are formed on the surface of the substrate 200. The write bit lines 212 extend along a second direction D2, and the multiple write bit lines 212 are arranged at intervals along a third direction D3. Both the second direction D2 and the third direction D3 are parallel to the top surface of the substrate 200, and the second direction D2 intersects the third direction D3. Figure 4HAs shown, a patterned sacrificial layer is formed on the surface of the write bit line 212. The sacrificial layer has a plurality of first holes arranged in an array along the second direction D2 and the third direction D3, and the first holes expose the write bit line 212; Figure 4I As shown, indium gallium zinc oxide is filled into the first hole to form a first indium gallium zinc oxide structure 211; as shown in the attached figure. Figure 4J As shown, a portion of the sacrificial layer is removed to form multiple independent first indium gallium zinc oxide structures 211, with the sacrificial layer remaining between the first indium gallium zinc oxide structures 211 serving as a first isolation layer 213; as shown in the attached figure. Figure 4M As shown, a first gate dielectric layer is formed on the surface of the first indium gallium zinc oxide structure 211; a plurality of write lines 214 are formed on the surface of the first isolation layer 213 and the surface of the first gate dielectric layer, which are spaced apart along the second direction D2, the write lines 214 surround the first indium gallium zinc oxide structure 211 and extend along the third direction D3; a second isolation layer 215 is formed on the surface of the write lines 214.

[0051] As a specific embodiment, see the attached document. Figure 4B ~Attached Figure 4D As shown, this disclosure provides a method for forming multiple write bit lines 212 on the surface of the substrate 200, comprising the following steps:

[0052] As attached Figure 4B As shown, a first insulating layer 253 is grown on the surface of the substrate 200. The first insulating layer 253 may be a silicon dioxide layer. In some embodiments, methods for forming the silicon dioxide layer include, but are not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.

[0053] As attached Figure 4C As shown, a first channel 291 is formed by etching along a first direction D1 on the surface of the first insulating layer 253. In a specific embodiment, the first channel 291 is formed by etching a portion of the surface of the first insulating layer 253, and the first channel 291 extends along a second direction D2 and multiple first channels 291 are arranged at intervals along a third direction D3.

[0054] A first conductive layer is formed within the first channel 291, serving as the write bit line 212, and forming an attachment. Figure 4D The structure is shown. In some embodiments, a metal material can be filled into the first channel 291 using processes such as chemical vapor deposition or atomic layer deposition to form the first conductive layer. The metal material includes, but is not limited to, tungsten, metal silicide, copper, and copper-tungsten alloys. The write bit lines 212 extend along the second direction D2, and a plurality of the write bit lines are arranged at intervals along the third direction D3, with adjacent write bit lines 212 isolated by a first insulating layer 253.

[0055] As a specific embodiment, see the attached document. Figure 4E ~Attached Figure 4H As shown, forming a patterned sacrificial layer on the surface of the write bit line 212 further includes the following steps:

[0056] As attached Figure 4E As shown, a first nitride layer 270 is formed on the surface of the write bit line 212 and the first insulating layer 253. The first dielectric layer 254 and the second dielectric layer 255 may be silicon dioxide layers. In some embodiments, the method for forming the silicon dioxide layer includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. The first nitride layer 270 may be a silicon nitride layer. In some embodiments, the method for forming the silicon nitride layer includes, but is not limited to, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.

[0057] As attached Figure 4F As shown, a first dielectric layer 254 is formed within the first nitride layer 270, spaced apart along the third direction D3. The first dielectric layer 254 extends along the second direction D2 and contacts the first insulating layer 253. A second dielectric layer 255 is formed within the first nitride layer 270, spaced apart along the second direction D2. The second dielectric layer 255 extends along the third direction D3. The first dielectric layer 254 and the second dielectric layer 255 intersect to form the first sacrificial layer 271. In some embodiments, the first nitride layer 270 may be patterned first to form a fifth channel, and oxide may be filled in the fifth channel to form the first dielectric layer 254. Then, the first nitride layer 270 and the first dielectric layer 254 may be patterned to form a sixth channel, and oxide may be filled in the sixth channel to form the second dielectric layer 255. The first dielectric layer 254 and the second dielectric layer 255 may be silicon dioxide layers. In some embodiments, the methods for forming the silicon dioxide layer include, but are not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.

[0058] As attached Figure 4G As shown, the first nitride layer 270 is etched back to expose the write line 212, and the first dielectric layer 254 and the second dielectric layer 255 define the first hole 297. In this step, the first nitride layer 270 is completely removed. In some embodiments, after forming the first hole 297, a rounding process can be performed to form a circular first hole 297, which can eliminate the need for further polishing after the subsequent deposition of the first indium gallium zinc oxide structure 211.

[0059] In other specific embodiments, when forming the first sacrificial layer 271, a nitride layer may not be formed; instead, an oxide layer may be formed directly, and holes may be drilled in the oxide layer to form the first hole 297. For example... Figure 4H As shown, forming a patterned first sacrificial layer 271 on the surface of the write bit line 212 further includes the following steps: forming a first dielectric layer 254 on the surface of the first conductive layer and the first insulating layer 253; etching the first dielectric layer 254 to form the first hole 297. The first hole 297 is a circular hole, and the circular hole formed by this method can eliminate the need for further polishing after the subsequent deposition of the first indium gallium zinc oxide structure 211.

[0060] As a specific embodiment, see the attached document. Figure 4I As shown, indium gallium zinc oxide is filled into the first hole 297 to form a first indium gallium zinc oxide structure 211. In some embodiments, the first indium gallium zinc oxide structure 211 can be deposited using an atomic layer deposition process.

[0061] As a specific embodiment, see the attached document. Figure 4J As shown, a portion of the sacrificial layer is removed to form a plurality of independent first indium gallium zinc oxide structures 211. The sacrificial layer retained between the first indium gallium zinc oxide structures 211 serves as a first isolation layer 213. A first gate dielectric layer (not shown) is formed on the surface of the first indium gallium zinc oxide structures 211.

[0062] In this embodiment, after forming multiple independent first indium gallium zinc oxide structures 211, the following step is further included: polishing the first indium gallium zinc oxide structures 211 to form rounded corners. If the first hole 297 has already been polished into a round hole in the aforementioned step of forming the first hole 297, then the step of polishing the first indium gallium zinc oxide structures 211 to form rounded corners can be omitted. The first isolation layer 213 is used to insulate the write bit line 212 and the write word line 214. The first gate dielectric layer is distributed on the surface of the first indium gallium zinc oxide structure 211 and is used to insulate the first indium gallium zinc oxide structure 211 and the write word line 214.

[0063] As a specific embodiment, see the attached document. Figure 4M As shown, a plurality of write lines 214 are formed on the surface of the first isolation layer 213 and the surface of the first gate dielectric layer, and the write lines 214 are arranged at intervals along the second direction D2. The write lines 214 surround the first indium gallium zinc oxide structure 211 and extend along the third direction D3.

[0064] As a specific embodiment, see the attached document. Figure 4K ~Attached Figure 4MAs shown, forming multiple writing lines 214 spaced apart along the second direction D2 on the surface of the first isolation layer 213 further includes the following steps:

[0065] As attached Figure 4K A second conductive layer 283 is formed between the first indium gallium zinc oxide structures 211. The second conductive layer 283 is located on the first isolation layer 213 and covers the first gate dielectric layer. In some embodiments, the metal material may be deposited using a chemical vapor deposition process or an atomic layer deposition process to form the second conductive layer 283. The metal material includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.

[0066] As attached Figure 4L A fourth insulating layer 256 is formed between the first indium gallium zinc oxide structures 211, and the fourth insulating layer 256 covers the second conductive layer 283. The fourth insulating layer 256 may be a silicon dioxide layer. In some embodiments, the method for forming the silicon dioxide layer includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.

[0067] As attached Figure 4M The fourth insulating layer 256, the second conductive layer 283, and the first isolation layer 213 are etched along the third direction D3 to form a second channel; a third dielectric layer 257 is formed within the second channel, such that the second conductive layer 283 is separated to form the write line 214, and the retained portion of the fourth insulating layer 256 and the third dielectric layer 257 constitute the second isolation layer 215. The third dielectric layer 257 may be a silicon dioxide layer. In some embodiments, the method for forming the silicon dioxide layer includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.

[0068] After completing the above steps, you will obtain the attached document. Figure 4M The write transistor 210 shown on the surface of the substrate 200 has the first indium gallium zinc oxide structure 211 region corresponding to the write word line 214 as the channel region of the write transistor 210, and the region where the first indium gallium zinc oxide structure 211 connects to the write bit line 212 as the source region of the write transistor 210. The first indium gallium zinc oxide structure 211 and the memory node 220 (shown on...) Figure 4P The area connected in the middle is the drain region of the write transistor 210.

[0069] Continue to refer to step S33 and the appendix Figure 4PA storage node 220 is formed on the surface of the write transistor 210, and the storage node 220 is fitted into the end of the first indium gallium zinc oxide structure 211.

[0070] In this embodiment, as shown in the appendix Figure 4N ~Attached Figure 4P As shown, forming a memory node 220 on the surface of the write transistor 210 further includes the following steps:

[0071] As attached Figure 4N A third insulating layer 258 is formed on the surface of the second insulating layer 215. The third insulating layer 258 may be a silicon dioxide layer. In some embodiments, the method for forming the silicon dioxide layer includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition.

[0072] As attached Figure 4O The third insulating layer 258 and a portion of the second insulating layer 215 are etched to form second holes 298 arranged in an array along the second direction D2 and the third direction D3. A portion of the first indium gallium zinc oxide structure 211 is exposed at the bottom of the second holes 298, and the second holes 298 are circular. In this step, the second insulating layer 215 is partially etched, and the ends of the first indium gallium zinc oxide structure 211 and the sidewalls at a predetermined distance below the ends are exposed in the second holes 298.

[0073] As attached Figure 4P A storage node 220 is formed in the second aperture 298, and the storage node 220 is fitted into the end of the first indium gallium zinc oxide structure 211. A first metal structure is deposited within the second aperture 298 as the storage node 220. In some embodiments, the second aperture 298 can be filled with metal material using processes such as chemical vapor deposition or atomic layer deposition to form the first metal structure. The metal material includes, but is not limited to, tungsten, metal silicide, copper, and copper-tungsten alloys. The storage node 220 is crown-shaped and fitted into the end of the first indium gallium zinc oxide structure 211, so that the storage node 220 is in contact with the top and sides of the first indium gallium zinc oxide structure 211, thereby increasing the contact area, improving conductivity, and making the signal transmission performance more stable. It also increases the structural stability, making the chip more durable.

[0074] After completing the above steps, you will obtain the attached document. Figure 4P The memory node 220 is formed in the write transistor 210 shown.

[0075] In this embodiment, the first nitride layer is etched to form the first hole 297, and the first indium gallium zinc oxide structure 211 is directly filled into the first hole 297. Then, a memory node 220 is formed on the first indium gallium zinc oxide structure 211. The entire process does not require etching of the first indium gallium zinc oxide structure 211, thus avoiding the adverse effects of etching the first indium gallium zinc oxide structure 211, such as the maintenance cost of etching equipment, waste gas treatment, and equipment pollution.

[0076] Continue to refer to step S34 and the appendix Figure 4T The formation of a read transistor 230 on the surface of the storage node 220 further includes the following steps: a second gate dielectric layer on the surface of the storage node 220; filling the second hole 298 with indium gallium zinc oxide to form a second indium gallium zinc oxide structure 231; and forming a plurality of read word lines 232 and read bit lines 233 on the surface of the second indium gallium zinc oxide structure 231, wherein the read word lines 232 and the read bit lines 233 are independent of each other.

[0077] As a specific embodiment, see the attached document. Figure 4Q As shown, the storage node 220 has a second gate dielectric layer on its surface; indium gallium zinc oxide (IGZO) is filled into the second hole 298 to form the second IGZO structure 231. In this disclosure, before forming the storage node 220, an array of second holes 298 are formed in the third insulating layer 258 and a portion of the second isolation layer 215, and then the storage node 220, the second gate oxide layer, and the second IGZO structure 231 are formed sequentially. In some embodiments, the second IGZO structure 231 can be deposited using an atomic layer deposition process.

[0078] In this embodiment, after forming the second gate dielectric layer in the second hole 298, indium gallium zinc oxide is directly filled to form the second indium gallium zinc oxide structure 231. Compared with the scheme of forming the second gate dielectric layer on the surface of the storage node 220, forming a sacrificial layer and etching the sacrificial layer to fill in indium gallium zinc oxide, the step of etching back the sacrificial layer is reduced, avoiding damage to the second gate dielectric layer when etching back the sacrificial layer, thereby avoiding affecting the performance of the read transistor 230.

[0079] As a specific embodiment, see the attached document. Figure 4R~4T As shown, forming read word lines 232 and read bit lines 233 on the surface of the second indium gallium zinc oxide structure 231 further includes:

[0080] As attached Figure 4RA patterned fourth insulating layer 259 is formed on the surface of the second indium gallium zinc oxide structure 231 and the eighth oxide layer 258. The fourth insulating layer 259 has a third channel extending along the third direction D3, and each third channel exposes the boundary region of two adjacent columns of the second indium gallium zinc oxide structure 231. A third conductive layer is formed within the third channel 293 as the read bit line 232. In other specific embodiments, the third conductive layer can also serve as the read bit line 233. The fourth insulating layer 259 can be a silicon dioxide layer. In some embodiments, the method for forming the silicon dioxide layer includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. In some embodiments, the third conductive layer can be formed using processes such as chemical vapor deposition and atomic layer deposition. The metal material includes, but is not limited to, tungsten, metal silicide, copper, and copper-tungsten alloys.

[0081] As attached Figure 4S A fifth insulating layer 260 is formed on the surface of the fourth insulating layer 259 and the read line 232; the fourth insulating layer 259 and the fifth insulating layer 260 are etched to form an array of third holes 299, each of the third holes 299 exposing the boundary region between two adjacent columns of the second indium gallium zinc oxide structures 231, and the third hole 299 is located between two read lines 232; a fourth conductive layer is formed in the third holes as a read line connection structure 234. In other specific embodiments, the fourth conductive layer can also serve as a read line connection structure. The fifth insulating layer 260 can be a silicon dioxide layer. In some embodiments, the method for forming the silicon dioxide layer includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. In some embodiments, the fourth conductive layer can be formed using processes such as chemical vapor deposition and atomic layer deposition. The metal material includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.

[0082] As attached Figure 4TA patterned sixth insulating layer 261 is formed on the surface of the fifth insulating layer 260. The eleventh oxide layer 261 has a fourth channel extending along the second direction D2. A fifth conductive layer is formed within the fourth channel as the read bit line 233. In other embodiments, the fifth conductive layer may also serve as the read bit line 232. The sixth insulating layer 261 may be a silicon dioxide layer. In some embodiments, methods for forming the silicon dioxide layer include, but are not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. In some embodiments, the fifth conductive layer may be formed using processes such as chemical vapor deposition and atomic layer deposition. The metallic material includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.

[0083] After completing the above steps, you will obtain the attached document. Figure 4T The multiple read word lines 232 and read bit lines 233 are shown. After forming the multiple read word lines 232 and read bit lines 233, the read transistor 230 is obtained. The region of the second indium gallium zinc oxide structure 231 corresponding to the memory node 220 serves as the channel region of the read transistor 230. The read word lines 232 are connected to the drain region of the read transistor 230, and the read bit lines 233 are connected to the source region of the read transistor 230. The memory node 220 serves not only as the gate of the read transistor 230 but also as the connection structure between the write transistor 210 and the read transistor 230.

[0084] After completing the above steps, the read transistor 230 is formed, thus obtaining the attached... Figure 2A The aforementioned semiconductor memory structure.

[0085] This disclosure also proposes other specific embodiments for forming read word lines 232 and read bit lines 233 on the surface of the second indium gallium zinc oxide structure 231, as shown in the appendix. Figure 4U ~Attached Figure 4W As shown, the following steps are further taken:

[0086] As attached Figure 4U ,exist Figure 4QBased on this, a patterned fourth insulating layer 259 is formed on the surface of the second indium gallium zinc oxide structure 231. The fourth insulating layer 259 has a third channel 293 extending along the third direction D3, with each third channel exposing one side of a row of the second indium gallium zinc oxide structures 231. A third conductive layer is formed within the third channel as the read bit line 232. In other embodiments, the third conductive layer can also serve as a read bit line 233. The fourth insulating layer 259 can be a silicon dioxide layer. In some embodiments, the method for forming the silicon dioxide layer includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. In some embodiments, the third conductive layer can be formed using processes such as chemical vapor deposition and atomic layer deposition. The metal material includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.

[0087] As attached Figure 4V A fifth insulating layer 260 is formed on the surface of the fourth insulating layer 259; the fourth insulating layer 259 and the fifth insulating layer 260 are etched to form an array of third holes, each of which exposes the other side of the second indium gallium zinc oxide structure 231; a fourth conductive layer is formed within the third holes as a read bit line connection structure 234. In other specific embodiments, the fourth conductive layer can also serve as a read word line connection structure. The fifth insulating layer 260 can be a silicon dioxide layer. In some embodiments, the method for forming the silicon dioxide layer includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. In some embodiments, the fourth conductive layer can be formed using processes such as chemical vapor deposition and atomic layer deposition. The metal material includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.

[0088] As attached Figure 4W A patterned sixth insulating layer 261 is formed on the surface of the fifth insulating layer 260. The sixth insulating layer 261 has a fourth channel extending along the second direction D2. A fifth conductive layer is formed within the fourth channel as the read bit line 233. In other embodiments, the fifth conductive layer may also serve as a read word line 232. The sixth insulating layer 261 may be a silicon dioxide layer. In some embodiments, the method for forming the silicon dioxide layer includes, but is not limited to, thermal oxidation, chemical vapor deposition, plasma chemical vapor deposition, and atomic layer deposition. In some embodiments, the fifth conductive layer may be formed using processes such as chemical vapor deposition and atomic layer deposition. The metal material includes, but is not limited to, tungsten, metal silicides, copper, and copper-tungsten alloys.

[0089] After completing the above steps, you will obtain the attached document. Figure 4WThe multiple read word lines 232 and read bit lines 233 are shown. After forming the multiple read word lines 232 and read bit lines 233, the read transistor 230 is obtained. The region of the second indium gallium zinc oxide structure 231 corresponding to the memory node 220 serves as the channel region of the read transistor 230. The read word lines 232 are connected to the drain region of the read transistor 230, and the read bit lines 233 are connected to the source region of the read transistor 230. The memory node 220 serves not only as the gate of the read transistor 230 but also as the connection structure between the write transistor 210 and the read transistor 230.

[0090] After completing the above steps, the read transistor 230 is formed, thus obtaining the attached... Figure 2B The semiconductor memory structure shown.

[0091] In this embodiment, the first nitride layer is etched to form the first hole 297, and the first indium gallium zinc oxide structure 211 is directly filled into the first hole 297. Then, a memory node 220 is formed on the first indium gallium zinc oxide structure 211. The entire process does not require etching of the first indium gallium zinc oxide structure 211, thus avoiding the adverse effects of etching the first indium gallium zinc oxide structure 211, such as the maintenance cost of etching equipment, waste gas treatment, and equipment pollution.

[0092] In this embodiment, after forming the second gate dielectric layer in the second hole 298, indium gallium zinc oxide is directly filled to form the second indium gallium zinc oxide structure 231. Compared with the scheme of forming the second gate dielectric layer on the surface of the storage node 220, forming a sacrificial layer and etching the sacrificial layer to fill in indium gallium zinc oxide, the step of etching back the sacrificial layer is reduced, avoiding damage to the second gate dielectric layer when etching back the sacrificial layer, thereby avoiding affecting the performance of the read transistor 230.

[0093] Appendix Figure 5 The diagram shown is a structural schematic of an embodiment of the semiconductor memory described in this disclosure. The semiconductor memory 500 includes one or more stacked components as shown in the attached diagram. Figure 2A Or attached Figure 2B The semiconductor memory structure 501. This embodiment is a two-layer... Figure 2A The semiconductor memory 500 is composed of the semiconductor memory structure 501 shown. In other embodiments, the semiconductor memory 500 may further include three layers of the semiconductor memory structure 501.

[0094] This embodiment employs a crown-shaped storage node 220, which is fitted into the end of the first indium gallium zinc oxide structure 211. This ensures that the storage node 220 makes contact with both the top and sides of the first indium gallium zinc oxide structure 211, increasing the contact area and resulting in higher conductivity and more stable signal transmission performance. It also enhances structural stability, making the chip more durable.

[0095] Furthermore, the circular first indium gallium zinc oxide structure 211 and the second indium gallium zinc oxide structure 231 can provide a more sufficient contact area, further ensuring good conductivity.

[0096] In this embodiment, the first nitride layer is etched to form the first hole 297, and the first indium gallium zinc oxide structure 211 is directly filled into the first hole 297. Then, a memory node 220 is formed on the first indium gallium zinc oxide structure 211. The entire process does not require etching of the first indium gallium zinc oxide structure 211, thus avoiding the adverse effects of etching the first indium gallium zinc oxide structure 211, such as the maintenance cost of etching equipment, waste gas treatment, and equipment pollution.

[0097] In this embodiment, after forming the second gate dielectric layer in the second hole 298, indium gallium zinc oxide is directly filled to form the second indium gallium zinc oxide structure 231. Compared with the scheme of forming the second gate dielectric layer on the surface of the storage node 220, forming a sacrificial layer and etching the sacrificial layer to fill in indium gallium zinc oxide, the step of etching back the sacrificial layer is reduced, avoiding damage to the second gate dielectric layer when etching back the sacrificial layer, thereby avoiding affecting the performance of the read transistor 230.

[0098] The above description is only a preferred embodiment of this disclosure. It should be noted that those skilled in the art can make several improvements and modifications without departing from the principles of this disclosure, and these improvements and modifications should also be considered within the scope of protection of this disclosure.

Claims

1. A semiconductor memory structure, characterized in that, include: Substrate; A write transistor is disposed on the substrate, the write transistor comprising a first indium gallium zinc oxide structure extending along a first direction, the first direction being a direction perpendicular to the top surface of the substrate; A storage node is disposed on the write transistor and embedded in the end of the first indium gallium zinc oxide structure; A read transistor is disposed on the memory node. The read transistor includes a second indium gallium zinc oxide structure, which is disposed on the memory node and insulated from the memory node. The memory node serves as the gate of the read transistor. The write transistor includes: A write bit line is disposed on the surface of the substrate and extends along a second direction, the second direction being parallel to the top surface of the substrate, and the first indium gallium zinc oxide structure is disposed on the surface of the write bit line; A first isolation layer is disposed on the surface of the write bit line and surrounds a portion of the first indium gallium zinc oxide structure; a write word line is disposed on the surface of the first isolation layer and extends along a third direction, the write word line surrounds a portion of the first indium gallium zinc oxide structure, the second direction is a direction parallel to the top surface of the substrate, and the second direction intersects with the third direction; A first gate dielectric layer is disposed between the word line and the first indium gallium zinc oxide structure; A second isolation layer is disposed on the surface of the writing line, and the storage node is disposed on the surface of the second isolation layer.

2. The semiconductor memory structure according to claim 1, characterized in that, The cross-section of the second indium gallium zinc oxide structure is circular.

3. The semiconductor memory structure according to claim 1, characterized in that, The semiconductor memory structure includes a plurality of write transistors arranged in an array along a second direction and a third direction. Adjacent write transistors in the second direction share the same write bit line, and adjacent write transistors in the third direction share the same write word line.

4. The semiconductor memory structure according to claim 1, characterized in that, The read transistor includes: A second gate dielectric layer is disposed on the surface of the memory node, and a second indium gallium zinc oxide structure is disposed on the second gate dielectric layer; Reading lines are disposed on the surface of the second indium gallium zinc oxide structure; The read bit line is disposed on the surface of the second indium gallium zinc oxide structure, and the read bit line is independent of the read word line.

5. The semiconductor memory structure according to claim 4, characterized in that, The semiconductor memory structure includes a plurality of read transistors arranged in an array along a second direction and a third direction. Adjacent read transistors in the second direction share the same read bit line, and adjacent read transistors in the third direction share the same read word line.

6. The semiconductor memory structure according to claim 5, characterized in that, The read word line is located at the boundary region of two adjacent read transistors in the second direction, and the two adjacent read transistors in the second direction share the same read word line; The read bit line is located at the boundary region of two adjacent read transistors in the second direction. The two adjacent read transistors in the second direction share the same read bit line, and the read word line and the read bit line are alternately arranged.

7. A method for fabricating a semiconductor memory structure, characterized in that, Includes the following steps: Provide a substrate; A write transistor is formed on the surface of the substrate, the write transistor comprising a first indium gallium zinc oxide structure extending along a first direction, the first direction being a direction perpendicular to the top surface of the substrate; A memory node is formed on the surface of the write transistor, and the memory node is fitted into the end of the first indium gallium zinc oxide structure; A read transistor is formed on the surface of the memory node. The read transistor includes a second indium gallium zinc oxide structure, which is disposed on the memory node and is insulated from the memory node. The memory node serves as the gate of the read transistor. The step of forming a write transistor on the substrate surface includes: forming a plurality of write bit lines on the substrate surface, the write bit lines extending along a second direction and the plurality of write bit lines being spaced apart along a third direction; A patterned sacrificial layer is formed on the surface of the write bit line, the sacrificial layer having a plurality of first holes arranged in an array, the first holes exposing the write bit line; The first hole is filled with indium gallium zinc oxide to form a first indium gallium zinc oxide structure; The sacrificial layer is partially removed, and the sacrificial layer remaining between the first indium gallium zinc oxide structures serves as a first isolation layer. A first gate dielectric layer is formed on the surface of the first indium gallium zinc oxide structure; Multiple writing lines are formed on the surface of the first isolation layer and the surface of the first gate dielectric layer, spaced apart along the second direction. The writing lines surround the first indium gallium zinc oxide structure and extend along the third direction. A second insulating layer is formed on the surface of the writing line.

8. The method according to claim 7, characterized in that, Forming multiple write lines on the substrate surface further includes the following steps: A first insulating layer is grown on the surface of the substrate; A first channel is formed by etching along a first direction on the surface of the first insulating layer; A first conductive layer is formed within the first channel, serving as the write bit line.

9. The method according to claim 8, characterized in that, Forming a patterned sacrificial layer on the surface of the write bit line further includes the following steps: A first nitride layer is formed on the write bit line and the surface of the first insulating layer; A first dielectric layer is formed within the first nitride layer, spaced apart along the third direction, and the first dielectric layer is in contact with the first insulating layer; A second dielectric layer is formed within the first nitride layer, spaced apart along the second direction, with the first dielectric layer and the second dielectric layer intersecting to form the sacrificial layer; The first nitride layer is etched back to expose the write bit line, and the first dielectric layer and the second dielectric layer define the first hole.

10. The method according to claim 9, characterized in that, After the step of forming multiple independent first indium gallium zinc oxide structures, the method further includes the following step: polishing the first indium gallium zinc oxide structures to form rounded corners.

11. The method according to claim 8, characterized in that, Forming a patterned sacrificial layer on the surface of the write bit line further includes the following steps: A first dielectric layer is formed on the surfaces of the first conductive layer and the first insulating layer; The first dielectric layer is etched to form the first hole.

12. The method according to claim 7, characterized in that, Forming a plurality of writing lines spaced apart along a second direction on the surface of the first isolation layer further includes the following steps: A second conductive layer is formed between the first indium gallium zinc oxide structures; A fourth insulating layer is formed between the first indium gallium zinc oxide structures, the fourth insulating layer covering the second conductive layer; The fourth insulating layer, the second conductive layer, and the first isolation layer are etched along the third direction to form a second channel; A third dielectric layer is formed within the second channel, thereby separating the second conductive layer to form the writing line. The retained portion of the fourth insulating layer and the third dielectric layer constitute the second isolation layer.

13. The method according to claim 12, characterized in that, Forming a memory node on the surface of the write transistor further includes the following steps: A third insulating layer is formed on the surface of the second insulating layer; The third insulating layer and part of the second isolation layer are etched to form an array of second holes, the bottom of which exposes part of the first indium gallium zinc oxide structure, and the second holes are circular holes; A storage node is formed in the second hole, and the storage node is fitted into the end of the first indium gallium zinc oxide structure.

14. The method according to claim 13, characterized in that, Forming a read transistor on the surface of the storage node further includes the following steps: A second gate dielectric layer is formed on the surface of the storage node; The second hole is filled with indium gallium zinc oxide to form the second indium gallium zinc oxide structure; Multiple read lines and read bit lines are formed on the surface of the second indium gallium zinc oxide structure, wherein the read lines and read bit lines are independent of each other.

15. The method according to claim 14, characterized in that, Forming read word lines and read bit lines on the surface of the second indium gallium zinc oxide structure further includes: A patterned fourth insulating layer is formed on the surface of the second indium gallium zinc oxide structure. The fourth insulating layer has a third channel extending along the third direction, and each third channel exposes the boundary region between two adjacent columns of the second indium gallium zinc oxide structure. A third conductive layer is formed within the third channel to serve as the readout line; A fifth insulating layer is formed on the surface of the fourth insulating layer; The fourth insulating layer and the fifth insulating layer are etched to form an array of third holes, each of which exposes the boundary region between two adjacent columns of the second indium gallium zinc oxide structure, and the third hole is located between the two read lines; A fourth conductive layer is formed inside the third hole to serve as a read line connection structure. A patterned sixth insulating layer is formed on the surface of the fifth insulating layer, the sixth insulating layer having a fourth channel extending along the second direction; A fifth conductive layer is formed within the fourth channel, serving as the read line.

16. The method according to claim 14, characterized in that, Forming read word lines and read bit lines on the surface of the second indium gallium zinc oxide structure further includes: A patterned fourth insulating layer is formed on the surface of the second indium gallium zinc oxide structure, the fourth insulating layer having a third channel extending along the third direction, each of the third channels exposing one side of a row of the second indium gallium zinc oxide structure; A third conductive layer is formed within the third channel to serve as the readout line; A fifth insulating layer is formed on the surface of the fourth insulating layer; The fourth and fifth insulating layers are etched to form an array of third holes, each of which exposes the other side of the second indium gallium zinc oxide structure. A fourth conductive layer is formed inside the third hole to serve as a read line connection structure. A patterned sixth insulating layer is formed on the surface of the fifth insulating layer, the sixth insulating layer having a fourth channel extending along the second direction; A fifth conductive layer is formed within the fourth channel to serve as the read bit line.

17. A semiconductor memory, characterized in that, It includes one or more stacked semiconductor memory structures as described in any one of claims 1 to 6.

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